JPS6193899U - - Google Patents
Info
- Publication number
- JPS6193899U JPS6193899U JP17680784U JP17680784U JPS6193899U JP S6193899 U JPS6193899 U JP S6193899U JP 17680784 U JP17680784 U JP 17680784U JP 17680784 U JP17680784 U JP 17680784U JP S6193899 U JPS6193899 U JP S6193899U
- Authority
- JP
- Japan
- Prior art keywords
- logic gate
- input terminal
- biasing
- logic
- biasing means
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims 2
- 239000000758 substrate Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Semiconductor Memories (AREA)
Description
第１図及び第２図はそれぞれ本考案の第１及び
第２の実施例の入力回路を示す回路図、第３図は
本考案の第１、第２の実施例の構成を示すブロツ
ク図である。
１……ＬＳＩ、２……ＲＯＭ、３……入力回路
、４……制御回路、５……出力回路、６……正電
源、７……負電源、８，９……抵抗、１０，１１
……接続端、１２，１３……入力端、１４……入
力端子、１５……論理ゲート、１６……Ｐチヤン
ネルＭＯＳトランジスタ、１７……Ｎチヤンネル
ＭＯＳトランジスタ。
1 and 2 are circuit diagrams showing the input circuits of the first and second embodiments of the present invention, respectively, and FIG. 3 is a block diagram showing the configuration of the first and second embodiments of the present invention. be. 1...LSI, 2...ROM, 3...Input circuit, 4...Control circuit, 5...Output circuit, 6...Positive power supply, 7...Negative power supply, 8, 9...Resistance, 10, 11
... Connection end, 12, 13 ... Input end, 14 ... Input terminal, 15 ... Logic gate, 16 ... P channel MOS transistor, 17 ... N channel MOS transistor.
Claims (1)
リと入力回路を含む半導体集積回路において、前
記入力回路が、論理ゲートと、該論理ゲートの入
力端子を所定のインピーダンスで第１の論理レベ
ルにバイアスする第１のバイアス手段及び所定の
インピーダンスで第２の論理レベルにバイアスす
る第２のバイアス手段と、前記論理ゲートの入力
端に対し前記第１のバイアス手段のみを接続する
かあるいに前記第２のバイアス手段のみを接続す
るかあるいは前記第１及び第２のバイアス手段の
いずれも接続しないかの接続選択手段とを含むこ
とを特徴とする半導体集積回路。 In a semiconductor integrated circuit including at least a read-only memory and an input circuit on the same semiconductor substrate, the input circuit includes a logic gate and a first logic gate that biases an input terminal of the logic gate to a first logic level with a predetermined impedance. and a second biasing means for biasing to a second logic level with a predetermined impedance, and only the first biasing means is connected to the input terminal of the logic gate, or the second biasing means is connected to the input terminal of the logic gate. and connection selection means for connecting only the bias means or neither of the first and second bias means.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17680784U JPS6193899U (en) | 1984-11-21 | 1984-11-21 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17680784U JPS6193899U (en) | 1984-11-21 | 1984-11-21 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6193899U true JPS6193899U (en) | 1986-06-17 |
Family
ID=30734391
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17680784U Pending JPS6193899U (en) | 1984-11-21 | 1984-11-21 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6193899U (en) |
-
1984
- 1984-11-21 JP JP17680784U patent/JPS6193899U/ja active Pending
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