JPS5984933U - level shift circuit - Google Patents

level shift circuit

Info

Publication number
JPS5984933U
JPS5984933U JP17115283U JP17115283U JPS5984933U JP S5984933 U JPS5984933 U JP S5984933U JP 17115283 U JP17115283 U JP 17115283U JP 17115283 U JP17115283 U JP 17115283U JP S5984933 U JPS5984933 U JP S5984933U
Authority
JP
Japan
Prior art keywords
shift circuit
level shift
output terminal
current
constant current
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP17115283U
Other languages
Japanese (ja)
Other versions
JPS602681Y2 (en
Inventor
須山 勝彦
Original Assignee
富士通株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 富士通株式会社 filed Critical 富士通株式会社
Priority to JP17115283U priority Critical patent/JPS602681Y2/en
Publication of JPS5984933U publication Critical patent/JPS5984933U/en
Application granted granted Critical
Publication of JPS602681Y2 publication Critical patent/JPS602681Y2/en
Expired legal-status Critical Current

Links

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

°第1図及び第2図は従来例の回路図、第3図は! 第2図従来例を集積回路装置として構成した場合の要部
平面図、第4図は本考案−実施例に於けるドレイン電流
を説明する為の線図、第5図は本考案−実施例の回路図
、第6図は第5図実施例の集積回路装置メして構成した
場合の要部平面図である。 図に於いて、Q工は駆動用トランジスタ、Q2は   
 ′定電流源用トランジスタ、Aは入力端、Xは出力端
、Dはドレイン、Gはゲート、Sはソースである。
°Figures 1 and 2 are circuit diagrams of the conventional example, and Figure 3 is! Fig. 2 is a plan view of essential parts when the conventional example is configured as an integrated circuit device, Fig. 4 is a diagram for explaining the drain current in the present invention-embodiment, and Fig. 5 is the present invention-embodiment. FIG. 6 is a plan view of a main part of the integrated circuit device according to the embodiment of FIG. 5. In the figure, Q is a driving transistor, and Q2 is
'A constant current source transistor, A is the input end, X is the output end, D is the drain, G is the gate, and S is the source.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 高電位側の電源と出力端との間に接続され且つ入力がゲ
ートに加えられるデ!プレッション形電界効果トランジ
スタと、該出力端と低電位側の電源との間に接続された
定電流源とを備え、前記ディプレッション齢電界効果ト
ランジスタにその飽和ドレイン電流より大なる電流を流
すような値に前記定電流源の電流値を設定したことを゛
特徴とするレベル−シフト回路。
A device that is connected between the high potential side power supply and the output terminal, and whose input is applied to the gate! a constant current source connected between the output terminal and a low-potential power source, the current being larger than the saturation drain current of the depletion-type field-effect transistor; A level shift circuit characterized in that the current value of the constant current source is set to .
JP17115283U 1983-11-04 1983-11-04 level shift circuit Expired JPS602681Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17115283U JPS602681Y2 (en) 1983-11-04 1983-11-04 level shift circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17115283U JPS602681Y2 (en) 1983-11-04 1983-11-04 level shift circuit

Publications (2)

Publication Number Publication Date
JPS5984933U true JPS5984933U (en) 1984-06-08
JPS602681Y2 JPS602681Y2 (en) 1985-01-25

Family

ID=30373427

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17115283U Expired JPS602681Y2 (en) 1983-11-04 1983-11-04 level shift circuit

Country Status (1)

Country Link
JP (1) JPS602681Y2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015019386A (en) * 2009-10-09 2015-01-29 株式会社半導体エネルギー研究所 Semiconductor device
JP2016140065A (en) * 2015-01-21 2016-08-04 パナソニック株式会社 Signal inversion device, power transmission device and negative voltage generating circuit

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015019386A (en) * 2009-10-09 2015-01-29 株式会社半導体エネルギー研究所 Semiconductor device
JP2016140065A (en) * 2015-01-21 2016-08-04 パナソニック株式会社 Signal inversion device, power transmission device and negative voltage generating circuit

Also Published As

Publication number Publication date
JPS602681Y2 (en) 1985-01-25

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