JPS59144914U - Impedance conversion circuit - Google Patents
Impedance conversion circuitInfo
- Publication number
- JPS59144914U JPS59144914U JP3830283U JP3830283U JPS59144914U JP S59144914 U JPS59144914 U JP S59144914U JP 3830283 U JP3830283 U JP 3830283U JP 3830283 U JP3830283 U JP 3830283U JP S59144914 U JPS59144914 U JP S59144914U
- Authority
- JP
- Japan
- Prior art keywords
- active element
- conversion circuit
- impedance conversion
- impedance
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Amplifiers (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図及び第２図は従来のインピーダンス変換回路を示
す回路図、第３図乃至第５図は本考案に係るインピーダ
ンス変換回路の実施例を示し、第３図は第１の実施例を
示す回路図、第４図及び第５図は夫々第２、第３の実施
例を示す回路図である。
１：第１の能動素子としてのＦＥＴ、 ２：第２の能動
素子としてのトランジスタ、３：第３の能動素子として
のＦＥＴ、 ４：制御用素子としてのトランジスタ。1 and 2 are circuit diagrams showing conventional impedance conversion circuits, FIGS. 3 to 5 show embodiments of the impedance conversion circuit according to the present invention, and FIG. 3 shows the first embodiment. The circuit diagrams shown in FIGS. 4 and 5 are circuit diagrams showing the second and third embodiments, respectively. 1: FET as a first active element, 2: Transistor as a second active element, 3: FET as a third active element, 4: Transistor as a control element.
Claims (1)
子と、該第１の能動素子からの出力を入力とし低インピ
ーダンスで出力できるようになっている第２の能動素子
と、上記第１の能動素子の電流源たる第３の能動素子と
、該第３の能動素子の電流量を制御するための制御用素
子とが含まれていることを特徴とするインピーダンス変
換回路。a first active element that can input an input voltage with high impedance; a second active element that receives the output from the first active element and can output it with low impedance; and the first active element. An impedance conversion circuit comprising: a third active element serving as a current source; and a control element for controlling the amount of current of the third active element.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3830283U JPS59144914U (en) | 1983-03-18 | 1983-03-18 | Impedance conversion circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3830283U JPS59144914U (en) | 1983-03-18 | 1983-03-18 | Impedance conversion circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59144914U true JPS59144914U (en) | 1984-09-27 |
| JPH0241927Y2 JPH0241927Y2 (en) | 1990-11-08 |
Family
ID=30168974
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3830283U Granted JPS59144914U (en) | 1983-03-18 | 1983-03-18 | Impedance conversion circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59144914U (en) |
-
1983
- 1983-03-18 JP JP3830283U patent/JPS59144914U/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0241927Y2 (en) | 1990-11-08 |
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