JPS5810115U - Stabilized power supply circuit - Google Patents
Stabilized power supply circuitInfo
- Publication number
- JPS5810115U JPS5810115U JP10253681U JP10253681U JPS5810115U JP S5810115 U JPS5810115 U JP S5810115U JP 10253681 U JP10253681 U JP 10253681U JP 10253681 U JP10253681 U JP 10253681U JP S5810115 U JPS5810115 U JP S5810115U
- Authority
- JP
- Japan
- Prior art keywords
- terminal
- control
- voltage
- high power
- supply circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Continuous-Control Power Sources That Use Transistors (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第1図は従来例による回路図、第2図は本考案による安
定化電源回路図、第3図、第4図は本考案の他の実施例
による回路図である。
図中5.15及び24は定電流源、8はスイッチングト
ランジスタ、9.16は出力トランジスタ、10は電源
レギュレータIC,12は入力端子、17は出力端子、
13. 14. 19. 18゜21は抵抗、20,2
2.23はトランジスタである。FIG. 1 is a circuit diagram of a conventional example, FIG. 2 is a stabilized power supply circuit diagram of the present invention, and FIGS. 3 and 4 are circuit diagrams of other embodiments of the present invention. In the figure, 5.15 and 24 are constant current sources, 8 is a switching transistor, 9.16 is an output transistor, 10 is a power regulator IC, 12 is an input terminal, 17 is an output terminal,
13. 14. 19. 18°21 is resistance, 20,2
2.23 is a transistor.
Claims (1)
上記小電力入力端子と上記小電力出力端子間に第1の制
御用トランジスタの主電流路が接続され、上記制御用ト
ランジスタの制御電極に上記制御端子の電圧を増幅して
加える様にした小電力安定化電源回路と、大電力入力端
子と大電力出力端子とを有し、上記大電力入力端子と上
記大電力出力端子間に第2の制御用トラジスタの主電流
通路が接続された大電力安定化電源回路と、上記大電力
入力端子の入力電圧を分圧して上記小電力入力端子に印
加する手段と、上記大電力出力端子の電圧を分圧して上
記制御端子に印加する手段と、上記小電力端子の電圧と
上記制御端子の電圧との差電圧を増幅して上記第2のト
ランジスタの制御電極に印加jることを特徴とする安定
化電源回路。It has a low power input terminal, a low power output terminal, and a control terminal,
A main current path of a first control transistor is connected between the low power input terminal and the low power output terminal, and the voltage at the control terminal is amplified and applied to the control electrode of the control transistor. A high power stabilizer comprising a stabilized power supply circuit, a high power input terminal and a high power output terminal, and a main current path of a second control transistor is connected between the high power input terminal and the high power output terminal. means for dividing the input voltage of the high power input terminal and applying it to the low power input terminal; means for dividing the voltage of the high power output terminal and applying it to the control terminal; A stabilized power supply circuit characterized in that a voltage difference between a voltage at a power terminal and a voltage at the control terminal is amplified and applied to a control electrode of the second transistor.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10253681U JPS5810115U (en) | 1981-07-10 | 1981-07-10 | Stabilized power supply circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP10253681U JPS5810115U (en) | 1981-07-10 | 1981-07-10 | Stabilized power supply circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS5810115U true JPS5810115U (en) | 1983-01-22 |
Family
ID=29897179
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP10253681U Pending JPS5810115U (en) | 1981-07-10 | 1981-07-10 | Stabilized power supply circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5810115U (en) |
-
1981
- 1981-07-10 JP JP10253681U patent/JPS5810115U/en active Pending
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