JPS6283299U - - Google Patents

Description

[Brief explanation of the drawing]

Fig. 1 is a connection diagram showing an embodiment of this invention, Fig. 2 is a waveform diagram of various parts of an embodiment of this invention, Fig. 3 is a block diagram showing an example of a sense amplifier enable signal generation circuit, and Fig. 4. 5 is a connection diagram showing a conventional example of a sense amplifier, and FIG. 5 is a schematic diagram showing signal levels of a conventional example of a sense amplifier. Explanation of main symbols in the drawings, 1, 2, 9:
N channel MOS transistor, 3, 4: P channel MOS transistor, 7: AND gate, 8: NOR gate, D,: data line,:
Sense amplifier enable signal.

Claims (1)

[Scope of utility model registration request] A pair of transistors forming a differential amplifier,
A sense amplifier including a constant current transistor inserted between the pair of transistors and one of the reference potential points, and a load circuit inserted between the pair of transistors and the other of the reference potential points, providing a logic circuit to which an output signal taken out from one of the pair of transistors and a sense amplifier enable signal are supplied;
A sense amplifier characterized in that the current path of the pair of transistors is cut off according to the level of the output signal by switching the constant current transistor based on the output of the logic circuit.