JPH0244598A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To reduce an operating current and to speed up a recovery time by stopping the operation of a sense amplifier and a memory array surrounding circuit and the like when the output signal of the sense amplifier is transferred to a rear stage output latch and starting the pre-charge or the preset operation of a complementary common data line, an internal output nord, etc. CONSTITUTION:Plural unit sense amplifiers USA0-USA31 are included in the sense amplifier SA of a semiconductor storage device with correspondence to the complementary common data lines CD0-CD31 and a pre-charge circuit PC, a level shift LS, sense amplifiers SCP and SCN and the like and an output latch OL are included in them. The storage device is made into a multiple constitution to simultaneously output the reading data of plural bits and plural reading amplifier circuits to be provided to correspond with each bit of the reading data and the output latch are constituted. The storage device is made into a clocked static type RAM of which basic constitution is a CMOS static type RAM.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor memory device, for example,
The present invention relates to a technique that is particularly effective when used in clocked static RAM (Random Access Memory) and the like.

[Conventional technology]

The memory array and peripheral circuits are CMO3 (complementary MO
There is a CMOS static RAM configured according to 3), which achieves high-speed operation and low power consumption. There is also a clocked static RAM which uses such a CMOS static RAM as its basic configuration and further reduces power consumption by converting the peripheral circuitry into a dyna.

For clocked static RAM, for example,
It is described in JP-A-61-134985 and the like.

[Problem to be solved by the invention]

FIG. 5 shows a clocked static RAM sense amplifier SA developed by the inventors prior to this invention.
A circuit diagram is shown. In the same figure, the clocked static RAM has a so-called multi-pint configuration that simultaneously inputs and outputs, for example, 32 bits of stored data, and its sense amplifier SA has a unit sense of 32 (lI) corresponding to each bit of read data. Amplifier USAO~USA
31 is provided. These unit sense amplifiers are
As represented by unit sense amplifiers USAO and LISA31 in the figure, each includes a precharge circuit PC, a level shift circuit LS, a sense circuit SC, and an output latch OL. Among these, the precharge circuit PC is selectively turned on according to the timing signal φsa.
P-channel MOS FETs Q7 and Q8, and when the clocked static type RAM is in the JF-selected state, the corresponding complementary common data lines CD0-CD3
1 (here, for example, the non-inverted common data line CDO and the inverted common data line CL) 0 are combined to form the complementary common data line C
(denoted as DO, hereinafter the same) is precharged to a high level such as the power supply voltage of the circuit. Level shift circuit L
S is selectively activated in accordance with the timing signal φsa, and shifts the DC level of the read signal output from the selected memory cell via the corresponding complementary common data edge Do-CD31. Similarly, the sense circuit SC is selectively activated according to the timing signal φsa, and amplifies the read signal transmitted via the corresponding level shift circuit LS. Further, the output latch OL takes in the read data output from the corresponding sense circuit SC, and the data output latch OL receives the read data output from the corresponding sense circuit SC.
Communicate to B. A P-channel preset MOSFET Q15, etc., which is selectively turned on according to the timing signal φsa, is provided between the inverted internal output nodes dnQ to dn31 of each sense circuit SC and the power supply voltage of the circuit. As a result, clocked static type RA
When M is in a non-selected state, the inverted internal output node dno-dn31 is preset to a high level, and the internal output signal rdo=rd31 is fixed to a low level.

However, it has become clear that the clocked static type RAM has the following problems. That is, each unit sense amplifier USAO of the sense amplifier SA~
The level shift circuit LS, sense circuit SC, etc. that constitute USA31 are selectively brought into operation according to the timing signal φsa, as described above. Furthermore, the levels of the complementary common data DO-CD31 and the inverted internal output node dnO"dn31, which affect the recovery time of the clocked static RAM, are as described above.
By setting the timing signal φSa to a low level, it is selectively precharged.

Here, the timing signal φaa is the timing signal φc supplied from the timing generation circuit TG when the clocked static RAM is in the read mode.
This timing signal φce is formed in accordance with the activation clock signal, that is, the chimbu enable signal CE, as shown in FIG. In other words, even though the amplification operation of the read signals has already been completed and these read signals have already been taken into the corresponding output latches OL, the chip enable signal CE is set to low level and the clocked static RAM is in the selected state. 32 provided in the sense amplifier SA while
The level shift circuits LS and sense circuits SC are continuously activated, and precharging or presetting operations of the complementary common data line and the inverted internal output node are prohibited.

For this reason, the operating current of the sense amplifier SA and memory array peripheral circuits cannot be reduced sufficiently, which limits the reduction in power consumption of clocked static RAM.
The recovery time of the clocked static RAM increases, and speeding up of its cycle time is limited.

An object of the present invention is to provide a semiconductor memory device such as a clocked static RAM that achieves low power consumption. Another object of the present invention is to shorten the recovery time of a semiconductor memory device such as a clocked static RAM and to speed up its cycle time.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

In other words, in a clocked static RAM having a multi-bit configuration, the sense amplifier and memory array It stops the operation of peripheral circuits, etc., and starts precharging or presetting operations of complementary common data lines, internal output nodes, etc.

[For production]

According to the above-mentioned means, the sense amplifier, memory array peripheral circuit, etc. can be kept in an operating state for only the minimum necessary period, and the operating current can be reduced, and the recovery time of the clocked static RAM can be increased. As a result, the clocked static type R, which has a multi-bit configuration,
It is possible to promote lower power consumption of AM, etc., and further speed up its cycle time.

〔Example〕

FIG. 2 shows a circuit block diagram of an embodiment of a clocked static RAM to which the present invention is applied. Further, FIG. 1 shows a circuit diagram of an embodiment of the sense amplifier SA of the clocked static RAM shown in FIG. An overview of the configuration and operation of the clocked static RAM of this embodiment, as well as its characteristics, will be described with reference to these figures. Note that each circuit element shown in FIGS. 1 and 2 and the circuit elements constituting each block may be made of a single semiconductor such as single crystal silicon, although not particularly limited, by known CMO3 integrated circuit manufacturing technology. Formed on a substrate. Also, in the figure below, MOSFETs with arrows added to the channel (bank gate) section
ET is a P-channel type and is shown to distinguish it from an N-channel MOSFET, which is not marked with an arrow.

The clocked static RAM of this embodiment is a so-called multi-bit RAM that simultaneously inputs and outputs 32-bit storage data, although it is not particularly limited. A clocked static RAM has a basic configuration of a memory array MARY that occupies most of the area of a semiconductor substrate. The memory array MARY includes, but is not particularly limited to, 32 sub-memory arrays SMO to SM3 provided corresponding to each bit of storage data input/output simultaneously.
Contains 1.

In FIG. 2, submemory arrays 5M0 to 3M31 constituting memory array MARY are arranged vertically with m+1 word lines WO to Wm arranged in parallel to the horizontal direction in FIG. f arranged in parallel
(m
+1) X (n+1) static type memory cells MC
and, respectively.

Each memory cell MC constituting sub-memory arrays SMO to SM31 includes, but is not particularly limited to, a P-channel MOSFET Q3, an N-channel MOSFET Q21, and a P-channel MOSFET Q21, as exemplarily shown in FIG.
It includes a 2 (vA) cMOS inverter circuit consisting of SFETQ4 and N-channel MOSFETQ22. These CMOS inverter circuits constitute a latch that serves as a storage element of a clocked static RAM by having their input terminals and output terminals cross-connected to each other. Further, the commonly coupled input terminal and output terminal of these CMOS inverter circuits are used as the human output node of each latch. m+ arranged in the same column of memory array MARY
The input/output node of the latch of the lf-captive memory cell MC is N
Channel type transmission game) MO5FBTQ23 and Q2
4 etc., the corresponding complementary data lines DO-Do-Dn
・1) Commonly connected to n. In addition, n + 1 fil arranged in the same row of the memory array MARY
The above transmission gate of memory cell MC) MOSFETQ23
Gates such as Q24 and Q24 are connected to the corresponding word line W O-W
are commonly connected to m.

Sub-memory arrays 5M0-3M of memory array MARY
Word lines WO to Wm constituting 31 are coupled to an X address decoder XAD and are selectively set. X
The address decoder XAD has an
Complementary internal address signal of i+l bits from B xO~a
xi (here, for example, the non-inverted internal address signal ax
Q and the inverted internal address signal 771 are collectively expressed as a complementary internal address signal axO. The same applies hereinafter) is supplied, and the timing signal φCe is supplied from the timing generation circuit TO. Although not particularly limited, the timing signal φce is set to a high level at a predetermined timing when the clocked static RAM is in a selected state. Further, as will be described later, when the amplification operation of the read signal by the sense amplifier SA is completed and the logic level of the output signal is determined, the output signal is returned to the low level.

The X address decoder XAD receives the timing signal φc
By setting e to a high level, it is selectively put into an operating state. In this operating state, the X address decoder
D decodes the complementary internal address signals axQ to axi and selectively selects the corresponding word line of the memory array MARY at a high level. As described above, when the amplification operation of the read signal by the sense amplifier SA is completed and the timing signal φce is set to low level,
The operation of address decoder XAD is stopped. As a result, the operating current of the X address decoder XAD is reduced, all word lines WO to Wm are set to a low level non-selected state, and the operating current for each memory cell MC of the memory array MARY is also reduced.

The X address buffer XAB is connected to the address input terminal AXO.
~i+l Bi supplied via AXi.

The X address signal AXO"AXi of the
Based on the above, the complementary internal address signals axQ to axi are formed and supplied to the X address decoder XAD.

On the other hand, sub memory array SMO of memory array MARY
Complementary data lines DO・■1~Dn that constitute ~5M31
-Dn is not particularly limited, but on the other hand, the corresponding P-channel precharge MOSFET QI
- Q2 to the supply voltage of the circuit, and on the other hand the corresponding switch M of the column switch C3W.
They are selectively connected to the corresponding offset common data lines CDO to -CD31 via OS FETs Q5 and Q25 and Q6 and Q26, respectively.

At the gate of MOSFET QI-Q2,
The above-mentioned timing signal φc is generated from the timing generation circuit TG.
e is commonly supplied. Precharge MOSFETQI
・Q2 is selectively turned on when the black 7 quad state clock type RAM is made unselected and the timing signal φC6 is set to low level, and the corresponding complementary data line DO is the ↓ inverted signal line of DO=Dn-Dn. and precharges the inverted signal line to a high level such as the power supply voltage of the circuit. When the clocked static type RAM is made into a selective tube and the timing signal φCe is set to high rail, these precharge MO3 are turned off.

Column switch C8W is, although not particularly limited, 32X (n+1) pairs of complementary switches MOSFE provided corresponding to complementary data lines DO-DO to Dn-DW of sub-memory arrays SMO to 5M31 of memory array MARY.
One of these switch MOS FETs, including Q5-Q25 and Q6 and Q26, is connected to the memory array MAR.
The corresponding complementary data lines Do-DO- to Dn-Dn of the corresponding sub-memory arrays SMO to 5M31 of Y are respectively coupled to the corresponding complementary common data lines -C.
They are commonly coupled to DO to CD31, respectively. The gates of the switch MOSFETs Q5, Q6 and Q25, Q26 in each column are commonly coupled, and the Y address decoder YAD
The corresponding data line selection signals YO to Yn or their inverted signals from the inverter circuit N1 are supplied from the respective data line selection signals YO to Yn.

Switch MOSFETQ in each column of column switch C5W
5, Q25 to Q6, and Q26 are turned on when the corresponding data line selection signals YO to Yn are alternatively set to the no level, and the sub memory array 3 MQ-3M
31 corresponding complementary data lines DO-Do to Dn-D
n and the corresponding complementary common data line CD0-Dan031 are selectively brought into a connected state. As a result, a total of 32 memory cells MC, one from each sub-memory array, are simultaneously selected and connected to the corresponding unit circuit of the sense amplifier SA or write amplifier WA.

The Y address decoder YAD has a Y address buffer Y.
Complementary internal address signal ayO- of j+l bits from AB
ayj is supplied, and the above-mentioned timing signal φce is also supplied from the timing generation circuit TG.

The Y address decoder YAD receives the timing signal φC.
By setting Q to a high level, it is selectively put into an operating state. In this operating state, the Y address decoder YA
D decodes the complementary internal address signals ayQ to ayj and selectively sets the corresponding data line selection signals YO to Yn to a no-y level. The clocked static RAM is in read mode and the sense amplifier SA
When the amplification operation of the read signal is completed and the timing signal φce is set to a low level, the operation of the Y address decoder YAD is stopped.

The complementary common data VMDO to -CD31 are respectively coupled to the output terminals of the corresponding unit circuits of the amplifier WA, and are respectively coupled to the input terminals of the corresponding unit circuits of the sense amplifier SA.

The input terminal of each unit circuit of the write amplifier WA is coupled to the output glass of the corresponding unit circuit of the data input buffer DIB. The input terminal of each unit circuit of the data person cover/nofa DIB is further connected to the corresponding data input/output terminal D.
are respectively coupled to O-D31. Similarly, the output terminal of each unit circuit of sense amplifier SA is coupled to the input terminal of the corresponding unit circuit of data output buffer DOB.

The output terminals of each unit circuit of the data output sofa DOB are as follows:
Additionally, there are corresponding data input/output terminals listed above.

~D31, respectively. light amplifier wa
, the timing signal ψ is sent from the timing generation circuit TO.
we are supplied. Further, timing signals φCe and φoe are supplied from the timing generation circuit TG to the sense amplifier SA and the data output buffer DOB, respectively. Here, the timing signal φwe is temporarily set to a high level at a predetermined timing when the clocked static type RAM is brought into a selected state in a write operation mode. Further, the timing signal φoe is set to a high level at a predetermined timing when the clocked static RAM is in a selected state in a read mode.

Each unit circuit of the data input buffer DrH, when the clocked static RAM is in write mode,
32-bit write data supplied from the outside via data input/output terminals Dθ~031 is taken in and transmitted to the corresponding unit circuit of the write amplifier WA.

In each unit circuit of the write amplifier WA, the clocked static type RAM is set to the signature mode and the above timing φ
By setting w6 to a high level, it is selectively put into an operating state. In this operating state, each unit circuit of the write amplifier WA uses the signed data transmitted via the data input buffer sofa DIB as a complementary write signal, and sends it to the submemory via the corresponding complementary common data lines CDO to CD31. It is supplied to selected memory cells MC of arrays 5M0-3M31. Although not particularly limited, when the timing signal φw6 is set to low level, the write amplifier ~VA
The output of each unit circuit is in a high impedance state.

As shown in FIG.
unit sense amplifiers USAO-USA31. Unit -4' 7 S'? 7pu USAO-USA31 is
Although not particularly limited, the unit sense amplifier IJ in FIG.
As represented by S A O and USA31,
Each includes a precharge circuit PC, a level shift circuit LS, sense circuits scP and SCN, and an output latch OL.

The precharge circuit PC of the unit sense amplifiers USAO to USA31 includes, but is not particularly limited to, a pair of Ps provided between the non-inverting signal line and the inverting signal line of the complementary common data edge DO-D31 and the power supply voltage of the circuit. Channel MOS
FETQ? and Q8, respectively. These Mo3F
The gates of ETQ7 and Q8 are all commonly coupled, and the above-mentioned timing signal φce is supplied from the timing generation circuit TO.

As a result, Mo5FETQ7 of the precharge circuit PC
and Q8 are selectively turned on when the L timing signal φce is set to a low level, that is, when the clocked static RAM is set to a non-selected state, and the corresponding complementary common data lines -CDQ to -〇D31 are turned on. The non-inverted signal line and the inverted signal line are precharged to a high level such as the power supply voltage of the circuit.

The level shift circuit LS of the unit sense amplifier tJSAO~USA31 includes, but is not particularly limited to, a pair of N-channel Mo3FETs Q27 and Q2 that are in a differential configuration.
B, and another pair of N-channel Mo3FETs Q29 and Q30 provided on the source side of these MOSFETs. The drains of Mo3FETs Q27 and Q28 are coupled to the circuit power supply voltage, and the drains of Mo3FETs Q29 and Q3
0 common coupled sources are N-channel MO5FE
It is coupled to the ground potential of the circuit via TQ31. M.O.S.
The gates of FETs Q27 and Q28 are coupled to the non-inverted signal line and inverted signal line of the corresponding complementary common data edges DO to D31, respectively. The gate of MOSFETQ29 is coupled to its drain and further connected to MOSFETQ3.
Commonly coupled to the 0 gate. This allows the MOSFE
TQ29 and Q30 are in a current mirror configuration. M.O.
Although not particularly limited, the gate of SFETQ31 is supplied with the output signal of AND gate circuit AG2, that is, timing signal φsa. MOS FETQ29 and Q
Is the source potential of 30 a phase? +li read signal sdO・
As 5do-sd31-sd31, sense circuit SCP
and SCN.

By the way, one input terminal of the AND gate circuit AG2 is supplied with the above-mentioned timing signal φce from the timing generation circuit TG, and the other input terminal is supplied with the internal control signal rm. Here, the internal control signal rm is
When the clocked static FOAM is selected in the read mode, it is selectively set to a high level.

As a result, the output signal of the ant gate circuit AG2, ie, the timing signal No. 4 φsa, is selectively set to a high level when the clocked static RAM is in a selected state in the read mode and the timing signal φco is set to a high level. Ru.

For these reasons, the level shift circuit LS of each unit sense amplifier assumes that the clocked static RAM is in the selected state in the read mode and at the above timing (ff signal φs
It is selectively brought into operation by being set to the a/f level. At this time, the level shift circuit and the S MOS
The gates of FET Q27 and Q28 are connected to the corresponding sub-memory array S I of memoria L/I MARY.
vi O=SM 31 selected memory cell MC
Complementary common data corresponding to 1JICDO~-9-03
1, a predetermined read signal is supplied. As mentioned above, clocked state.

When the double-type RAM is brought into a non-selected state, each sub-memory τ and complementary common data lines CDO to CD31 are precharged to a high level similar to the power supply voltage of the circuit. Therefore, the read signal has its center level at a relatively high level close to the power supply voltage of the circuit, and both MOS FETQ 27 and Q28 of the level shift circuit LS are turned on. This allows ivi
OS FET Q27 and Q28 source potential or phase? ! Read signal 5dO-sdO"-5a31-
sd31 is MOSFETQ27 and Q29 or MOSFET
It changes in phase with the readout signal, centered around a predetermined bias level determined by the conductance ratio of SFETs Q28 and Q30. In other words, the read signal transmitted via the offset common data lines CDO to -CD3i has its DC level shifted by the corresponding level shift circuit LS, so that the sense circuit SCP and -5C
It is assumed that the effective bias level is such that the sensitivity of N is maximized.

Unit sense amplifier USA O= USA 31
The sense circuit SCP includes a pair of N-channel MO8FHTQ32 (second
MOSFET) and Q33 (first MOSFET)
and a pair of P-channel MOS FETQ9 (fourth MOSFET) provided on the drain side of these MOSFETs.
SFET) and QIO (third MOSFET). The sources of MO5FETQ9 and QIO are coupled to the power supply voltage of the circuit, and an N-channel drive MO3F'ETQ34 (
A fifth MO3FE1') is provided. MOSFETQ
The gate of 10 is coupled to its drain and further connected to the MO
Coupled to the gate of SFETQ9. This allows M.O.
5)'F, TQ9 and Q10 are in a current mirror configuration. M OS r" E "I' Q 32 and Q33
For game 1-, the corresponding level shift circuit, S
output signal, that is, complementary readout signal 5dQ-sdO~
5d31-sd31 are supplied respectively. MOSFE
The timing signal φsa is supplied to the gate of TQ34.

The train of MOSFET Q32 is further coupled to the input terminal of CMOS inverter circuit N2.

Between the input terminal of this inverter circuit N2 and the power supply voltage of the circuit, there is a P-channel preset MO3FE'rQ1 whose gate receives the timing signal φsa.
3 is provided. The output signals of the inverter circuit N2 are non-inverted internal output signals dpo to dP31, respectively.

Similarly, the sense circuit SCN of the potential sense amplifiers USAO to USA31 includes a pair of N-channel MOSFETs Q35 (first MO8FE "f") and Q36 (second MOSFET), which are differentially shaped. A pair of P-channel MO5FETQII (third MOSFET) provided in the drain example of these MOSFETs
and Q i 2 Cm□1 MOS F ET), MOS F F, 'T' Q 1 i and Q1
The source of MOSFET 2 is coupled to the circuit power supply voltage, and the source of MOSFET
An N-channel drive MOSFET is connected between the commonly coupled sources of Q35 and Q36 and the circuit ground potential.
Q37C fifth MOSFET) is provided. M.O.
The gate of SFETQI 1 is coupled to its drain, which in turn is coupled to the gate of MOSFETQI 2.

As a result, MOS FETQll and Q12 are placed in a current mirror configuration.

The output signals of the corresponding level shift circuits LS, that is, the complementary read signals sdo.sdo to 5d31.5d31 are supplied to the gates of the MOSFETs Q35 and Q36, respectively. The timing signal φsa is supplied to the gate of MOSFETQ37.

The drain of MOSFET Q36 is further coupled to the input terminal of a 40S on-C inverter circuit N3.

A P-channel type preset MO5FETQ14 receiving the E timing signal φsa at its gate is provided between the input terminal of the impark circuit \3 and the power supply voltage of the circuit. The output signals of the inverter circuit N3 are each non-inverted internal output signal dno=dn31.

When the clocked static type RAM is in a non-selected state or a hot mode and the timing signal ψsa is set to a low level, the driving MOSFETs Q34 and Q37 of the sense circuits sep and SCH are in an off state, and the pre-sensing I-MOSFETs Qi3 and Q14 are in an on state. becomes. Therefore, both sense circuits SCP and SCN are rendered inactive, and MO5FETs Q32 and Q3 (i
1' potential, that is, the inverted internal output signal apo-d
Both p3 i and d rIQ ~ d n s I tend to become uncertain rails. However, as described above, since the presensor l-MOSFE'Q13 and Q14 are turned on, all of these inverted internal output signals are at a high level similar to the power supply voltage of the circuit. As a result, the output signals of inverter circuits N2 and N3, that is, non-inverted internal output signals dpO-dp31 and d
All of nQ to dn3j are determined to be low level.

This prevents lightning current from flowing through the CMOS inverter circuits N2 and N3.

On the other hand, when the clocked static RAM is selected in the read mode and the timing signal φ3d is set to high level, the drive MOSFETs Q34 and Q37 are turned on, and the preset MOSFETs Q13 and Q
14 is in the off state. Therefore, the sense circuit SCP
and SCN are both brought into operation, and a read signal amplification operation is performed. As a result, the inverted internal output signal ctp
.

~dp31 level is the corresponding complementary read signal sd
O・sdO~5d31-sd31 is changed in reverse phase, and the level of the inverted internal output signal dnQ~dn(lower) is the corresponding complementary readout signal sdO・sdQ~5d31-s
It is changed in phase according to d31. That is, the corresponding complementary read signals sdO・sdo”sd31・sd3
1 is set to logic "O", non-inverted signals sdQ~5d31 are set to inverted level, and corresponding inverted internal output signals dn0~
d n 31 is set to low level. As a result, the non-inverted internal output signals apo to dp31 are set to low level,
Non-inverted internal output signals dno to dn31 are set to high level. On the other hand, the corresponding phase? ! Read signal 5dO-Gd
O~sd31 ・sd31 is set to logic "1", and the non-inverted signals sdQ~sd3] are inverted It'! ! 3d O
-s d 31, the corresponding inverted internal output signal dpo-dp31 is set to low level, and the corresponding inverted internal output signal dnO~11 n 31 is set to high level. As a result, the non-reverse No. 1 internal output signal do
o to dp31 are set to high level 2, and non-inverted internal output signal d n Q -d n 31 is set to low level.

・In other words, the clocked static type RA of this embodiment
In M, the sense circuits SCP of the unit sense amplifiers USAO to USA31 have the corresponding read signals set to logic “1”.
”.As a result, on the condition that the corresponding readout node 3 is logic “1”, its inverted output node dp
o=dp31 is selectively discharged and set to low level. Similarly, the unit sense amplifier USAO-US
The sense circuit SCN of A31 functions as a second sense circuit for determining whether the corresponding read signal is logic "0". As a result, on the condition that the corresponding readout No. 8 is logic "θ", its inverted output node dnO.-dn31 is selectively discharged;
It is considered to be low level.

The output of the potential sense amplifier USAO=LISA31 is connected to two CMOS inverter circuits N4 and N.
Its basic structure is a latch in which 5 is cross-connected. Input terminal of inverter circuit N4 and inverter circuit N
If the common coupled node of the output terminals of 5 and 5 is the output latch O
It is an inverted input/output node of L, and N channels ~ 10SF
It is coupled to the power supply voltage and ground potential of the circuit via F, rQ3s and O40, respectively. Δ(O3FF, TQ38
The output of the inverter circuit N3 (No. 6, that is, non-inverted internal output signal dno-dn31) is supplied to the gate of MO5FETQ40, and the output of the inverter circuit N2 (No. 8, that is, non-inverted internal output signal dno-dn31) is supplied to the gate of =dp31 are respectively supplied.

Similarly, the commonly coupled node of the output terminal of the inverter circuit N4 and the input/naruko of the inverter circuit N5 is a non-inverting input/output node of the output latch OL, and the N-channel M
It is metallurgized to the power supply voltage and ground potential of the circuit through OSFETQ39 & O41, respectively. MOSFETQ39
The output signal of the inverter circuit N2, that is, the non-inverted internal output signals apo to dp31, is supplied to the gate of MOSFET Q41, and the output signal of the -f inverter circuit N3, that is, the non-inverted internal output signal d, is supplied to the gate of the MOSFET Q41.
Supply nQ to dn31, respectively. Output latch OL
The potential of the non-inverting input/output node of is the non-inverting internal output signal r
The signals dO to rd31 are supplied to the corresponding degree circuits of the data output cover and fa DOB.

Output latch O of unit sense amplifier USAO to USA31
L further includes OR gate circuits OGI to OG2, one input terminal of which is supplied with the corresponding non-inverted internal output signal dpO to dp31;
The corresponding non-inverted internal output signals dnQ to dn31 are supplied to the other input terminal. OR gate circuit Q
The output signals of GI to OG2 are internal signals dsO to ds31.
is supplied to the corresponding input terminal of the AND gate circuit AC,1. The output signal of the AND gate circuit AGL is
It is supplied to the timing generation circuit TG as an internal control signal ads.

When the black static type RAM is in the non-selected state or in the read mode, the output signal of the inverter circuit N2, that is, the non-inverted internal output signal dpo=dp31
The output signals of the -f inverter circuit N3, that is, the non-inverted internal output signals dnO to dn31, are all fixed at a low level as described above. Therefore, MOSF
ETQ38 to Q41 are all turned off, and the output latch OL maintains and governs the previous state. At this time, the output signals of the OR gate circuits OG1 to G2, that is, the internal signals dso to ds3L, are all set to a low level, so the output signal of Gl to the AND gate circuit, that is, the internal control signal ads, is set to a low level. On the other hand, when the clocked static RAM is selected in the read mode, as described above, the output signal of the inverter circuit N2, that is, the non-inverted internal output signals apo to dp31, indicates that the corresponding read signal is logic "1". The output signal of the inverter circuit N3, that is, the non-inverted internal output signal dn.

~dn31 is selectively set to high level on the condition that the corresponding read signal is logic "0". As a result, the corresponding output latch OL is forced into the set or reset state. At this time, the non-inverted internal output signal a
By selectively setting po~dp31 or dnO-dn31 to a high level, the OR gate circuits OGI~OG
2 output signal, i.e. internal signal d s O-d s 3
1 is considered to be a high level all at once. Therefore, the output signal of the AND gate circuit AGI, that is, the internal control signal adS
is considered to be at a high level.

In other words, the clocked static type RAM of this embodiment
In this case, the internal control signal ads is applied when the clocked static type RAM is selected in the read mode and when all the unit sense amplifiers U.S.A.O.
When the logic level of the output signal 31 is determined, it is selectively set to high level.

As will be described later, when the internal control signal ads is set to a high level, the timing generation circuit TG returns the timing signal φce, which was previously set to a high level, to a low level. As a result, the unit sense amplifier USAO of the sense amplifier SA
- The operations of the level shift circuit LS and sense circuits SCP and SCH of USA31 are stopped, and the operations of the X address decoder XAD and Y address decoder YAD are also stopped. In addition, the precharge circuit pc of the unit sense amplifiers USAO to USA31 of the sense amplifier SA
At the same time, the precharging operation of the complementary common data lines CD0 to CD31 is started, and the complementary data lines D of the sub-memory arrays SMO to 5M31 of the memory array MARY are started.
A precharge operation of O.DO-Dn-Dn is started.

Although not particularly limited, the data output buffer DOB is a unit sense amplifier USAO to USA3 of the sense amplifier SA.
It includes 32 unit circuits provided corresponding to 1. These unit circuits are selectively brought into operation by setting the timing signal φOe to a high level. In this operating state, each unit circuit of the data output buffer DOB has a corresponding unit sense amplifier U of the sense amplifier SA.
An output signal is formed according to the non-inverted internal output signals rdo-rd31 outputted from SAO-USA31, and is sent to the outside via the corresponding data input/output terminal Do-D31. Although not particularly limited, when the timing signal φOe is set to a low level, the output of each unit circuit of the data output buffer DOB is set to a high impedance state.

The timing generation circuit TG forms the various timing signals described above based on the chip enable signal CE and the write enable signal WE supplied as control signals from the outside, and supplies them to each circuit. Further, when the internal control signal ads supplied from the sense amplifier SA is set to a high level, the above-mentioned timing signal φc, which is set to a high level -
Return s to low level.

Figure 3 shows the clocked static RAM of Figure 2.
A timing diagram for one embodiment of a read mode is shown. According to FIG. 3 and FIGS. 1 and 2 above,
The outline and characteristics of the read mode of the clocked static RAM of this embodiment will be explained.

In FIG. 3, the black static type RAM is
Although not particularly limited, the selected state is achieved by changing the starting clock signal, that is, the chip enable signal CE, from a high level to a low level. Prior to this change of the chip enable signal CE to a low level, the write enable signal WE is set to a high level to designate a read mode. Address input terminals AXO-AXi and AYO
~AYj are supplied with an X address signal AX and a Y address signal AY.

When the chiabu enable signal GE is set to high level,
In the clocked static type RAM, the timing signal φce is set to low level. Therefore, precharge MOSFETs Q1-Q2 provided in each sub-memory array of memory array MARY are turned on, and complementary data lines DO/DO to Dn-Dn are precharged. In addition, the precharge MOSF provided in the precharge circuit PC of each sense amplifier of the sense amplifier SA
ETQ7 and Q8 are also turned on, and the complementary common data line -
Precharging of CDO to CD31 is performed. Furthermore, in the output latch OL of each of the 11 sense amplifiers, preset MOSFETs Q13 and Q14 are turned on,
Inverted internal output nodes dding-dp3L and dnO-
dn31 is set to 1 level. Accordingly, the non-inverted internal output signal dpO=dp31 and dnO~
dn31 becomes low level, and the internal signal dsO”d
All s31 become low level. As a result, the internal control signal ads is set to low level.

When the chip enable signal -CE is changed from the high level to the low level, the clocked static type RA
In M, first, the timing signal ψce is set to the 71-high level, and a little later, the timing signal (No. 8 φ0e is set to the high level).

By setting the timing signal φco to a high level, the precharge MOSFE':'Q1・Q
2 and Q7/Q8 and Brisset MOS FET
Q13 and Q14 are turned off all at once, and the precharging operation of the complementary data line, complementary common data line, and each internal output node is stopped. Further, the X address decoder XAD and the Y address decoder YAD are activated, and a total of 32 memory cells MC, 1118 each, are selected from each sub-memory array of the memory array MARY. As a result, the corresponding complementary data line DO/DO=
The level of the non-inverted signal line or the inverted signal line of Dn-L1 and complementary common data lines CDO to D31 is selectively lowered according to the data stored in the selected memory cell MC. These signal changes are transmitted to the corresponding unit sense amplifiers 1SAO to USA31 of the sense amplifier SA as read signals for each memory cell MC.

# of sense amplifier SA sense 7 amplifier USAO~USA
31, the timing signal φce is set to high level, so that the level shift circuit LS and the sense circuit SC
P and SCN are activated. Complementary common data line C
The read signal transmitted via D07CD31 is first shifted in its DC level by a corresponding level shift circuit LS, and then amplified by corresponding sense circuits SCP and SCH, respectively. As a result, when the read signal output from the corresponding memory cell MC is at logic "L", the inverted internal output signal apO-dp31 is selectively set to low level, as shown by the solid line in FIG. Inverted internal output (:i number ci p O-d p
31 is selectively set to high level. At this time, the inverted internal output signal d n Q z d n31 is
The non-inverting internal output (K '+ d n
O to d ri 31 are kept at low level. When the read signal output from the corresponding memory cell MC is logic "O", the inverted internal output signal dnO=dn31 is selectively set to low level, as shown by the dotted line in FIG. Internal output signal dnQ~cin31
is selectively set to λ level. At this time, the corresponding inverted internal output signals ap□-dp31 remain at high level, and the non-inverted internal output signal apo-dp31 remains at low level.

By selectively setting the non-inverted internal output signal dpQ''dp31 or dno to dn31 to a high level, the output signals of the corresponding OR gate circuits OG1 to OG2, that is, the internal signals dsQ-ds31, are set to a high level. Further, the output latch OL of each unit sense amplifier of the sense amplifier SA is selectively set or reset, and accordingly, the internal output signals rdO to rd31 are selectively set to the 71 level or low level.

All units of sense amplifier SA sense amplifier USAO
~In USA31, when the read signal increase @ operation is completed and all the non-inverted internal output signals dpO~dp31 or dnQ~dn31 are selectively set to high level, all of the sense amplifiers SA When the logic level of the output signal of the unit sense amplifier is determined, the output signal of the AND gate circuit AGI, that is, the internal control signal ad! I is set to high level. Therefore, the timing signal φce is set to low level by the timing generation circuit TG, and in each unit sense amplifier of the sense amplifier SA, the level shift circuit gBLS and the sense circuit SC
The operation of P and SCN is stopped. Also, complementary data lines DQ-DO-Dn-Dn and complementary common data line -CDO
~ and 1) The precharge operation of 31 is started, and internal output nodes dpo-dp31 and duO~da3
1 preset operation is started. At this time, the output latch OL of each unit center amplifier holds the read data corresponding to the data stored in the 32 selected memory cells MC until the next read mode is executed.

The read data held in the output latch OL of each unit sense amplifier is output as internal output nodes dO to rd31.
The data is transmitted to the corresponding unit circuit of the output sofa DOB. These read data are processed by the timing signal φo
When e is set to high level, the signal is sent to the outside via the corresponding data input/output terminal Do-D31.

As described above, the clocked static type RAM of this embodiment is a so-called multi-bit RAM that simultaneously inputs and outputs 32-bit storage data. Therefore, the clocked static RAM includes 32 sub-memory arrays SMO to 5M31 and complementary common data lines CDO to D31 provided corresponding to each bit of the stored data, and 32 unit circuits. A sense amplifier SA and a write amplifier WA are provided. The clocked static type RAM is brought into a selected state according to a starting clock signal, that is, a chip enable signal CB, supplied from the outside. Therefore, the X address decoder XAD,
Each unit circuit of Y address decoder YAD, sense amplifier SA, and write amplifier WA is selectively put into an operating state according to timing signal φce formed based on chip enable signal CE. In this embodiment, the unit sense amplifiers USAO~US of the sense amplifiers SA are
A31 is the corresponding complementary common data line CD0-CD31
The sensor circuit includes a sense circuit SCP that determines that the read signal outputted through the circuit is a logic "1", and a sense circuit SCN that determines that the read signal is a logic "0". Also, an OR gate circuit for determining that the output logic level of the sense circuit SCP or SCN is determined by selectively setting the output signal to a low level.

It includes Gl to OG2 and an AND gate circuit AGI.

As a result, every unit sense amplifier tJsAO~US
At A31, when the amplification operation of the read signal is completed and the logic level of the output signal is determined, the output signal of the AND gate circuit AGI, that is, the internal control signal ads
is considered to be at a high level. This internal control signal ads is supplied to the timing generation circuit TG, and the timing signal φCe is returned to the low level even though the clocked static type RAM is still in the selected state.

As a result, the operations of the X address decoder XAD and the Y address decoder Y end are stopped, and in each unit sense amplifier of the sense amplifier SA, the operations of the level shift circuit LS and sense circuits SCP and SCN are stopped. In addition, the precharging operation of each complementary data line and complementary common data line is started, and the sense amplifier S
A preset operation of a predetermined internal node of A is started.

For these reasons, in the locked static type RAM of this embodiment, each address decoder and sense amplifier S
Each sentry sense amplifier in A is kept in operation for the minimum necessary period, promoting low RG power consumption, and the recovery time of complementary data lines, complementary common data lines, and predetermined internal nodes is recursive. This will speed up the cycle time.

As shown in the above embodiments, when the present invention is applied to a semiconductor memory device such as a clocked static RAM having a multi-bit configuration, the following effects can be obtained.

In other words, (in a clocked statinoch RAM with an 11-bit configuration, each By stopping the operations of the address decoder, sense amplifier, etc., it is possible to keep these circuits in an operating state for only the minimum necessary period, resulting in the effect that the operating current can be significantly reduced.

(2) According to the above item (1), it is possible to achieve the effect of promoting lower power consumption of chromostatic RAM, etc.

(3) In the above item (1), the logic level of the output signal of the sense amplifier is determined or the output signal strength of the sense amplifier <t8! By starting the precharging or presetting operation of complementary data lines, complementary common data lines, predetermined internal output nodes, etc. when the signal is transmitted to the output latch of the stage, the recovery time of clocked static RAM, etc. can be shortened. Effects can be obtained.

(4) Item (3) above provides the effect that the cycle time of a clocked static RAM or the like can be further increased.

Although the invention made by the present inventor has been specifically explained above based on examples, it goes without saying that this invention is not limited to the above-mentioned examples, and can be modified in various ways without getting the gist of the invention. For example, in the embodiment shown in FIG. 1, a sense circuit SCP that determines that the read signal is logic "L" and a sense circuit SCN that determines that the read signal is logic "0" are provided separately. However, these sense circuits may be integrated, for example, as shown in the sense circuit SC of FIG. In FIG. 4, P-channel MOS FETQ15 and Q1
0 and N-channel MOSFETs Q42-Q45 are P-channel MOSFETs Q9 and Q12 and N-channel MOSFETs Q32. Q35. Q3
3. Each corresponds to Q36. Also, P channel M
OSFETQIG is the P-channel MO5FE in Figure 1.
TQIO and Qll are shared, and the N-channel MOSFET Q46 is the N-channel MOSFET in FIG.
SFET Q34 and Q37 are shared. 1 and 4, the internal control signal ads may be the internal signal ds (represented by any one or more of 1 to ds31; in this case, the unit with the slowest operating speed Select a sense amplifier as a representative, or
Alternatively, it is effective to arbitrarily slow down the operating speed of the unit sense amplifier that corresponds to the representative internal error. The internal signal dsO-ds31 may be formed by identifying that the read fa number has been taken into the output latch OL. Furthermore, if the clocked static RAM or the like is a memory with 18 logic capabilities, the output signal of each output latch OL may not be sent to the outside, but may be supplied as is to the subsequent logic circuit. Each sense circuit may be constructed by symmetrically combining a plurality of current mirror type augmentation circuits. In FIG. 2, the clocked static iRAM has a memory array MARY and a plurality of The clocked static RAM may include a memory array, and the memory cell MC may be a static memory cell with a high resistance load.
It may not include a column selection circuit, and it does not need to have a multi-focus configuration. The circuit whose operation is stopped when the internal control signal ads is set to high level and the internal node where the precharge or preset operation is started are not limited by this embodiment. Furthermore, the specific circuit configuration of the sense amplifier SA shown in FIGS. 1 and 4, the block configuration of the clocked static RAM shown in FIG. 2, the combination of control signals, etc. shown in FIG. 3, etc. , various embodiments may be adopted.

In the above explanation, the invention made by the present inventor was applied to a clocked static RAM, which is the field of application that formed the background of the invention, but the invention is not limited to this. It can also be applied to type RAM and other semiconductor memory devices.

The present invention is widely applicable to semiconductor memory devices having at least a read amplifier circuit and an output latch circuit, or to digital integrated circuit devices incorporating such semiconductor memory devices.

(Effects of the Invention) The effects obtained by typical inventions disclosed in this application are as follows.In other words, in a clocked static RAM having a multi-bit configuration, When the logic level of the output signal of the sense amplifier is determined or the output signal of the sense amplifier is transmitted to the subsequent output latch, the operation of the address decoder, sense amplifier, etc. is stopped, and the complementary data line and complementary common data line are In addition, by starting a precharge or preset operation of a predetermined internal output node, etc., it is possible to promote lower power consumption of a clocked static RAM, etc., and to speed up its cycle time.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an example of a clocked static RAM sense amplifier to which the present invention is applied, and FIG. 2 is an example of a clocked static RAM including the sense amplifier shown in FIG. A circuit block diagram showing an embodiment, FIG. 3 is a clocked static type RAM shown in FIG.
FIG. 4 is a timing diagram showing another embodiment of the sense amplifier of a clocked static RAM to which the present invention is applied; FIG. 6 is a circuit diagram showing an example of a sense amplifier of a clocked static type RAM previously developed by the inventors of 1N, and FIG. 6 is a timing diagram showing an example of a read mode of the clocked static type RAM of FIG. 5. . SA...Sense amplifier, USAO~(JSA31...
・Fluorescent level sense amplifier, PC...precharge circuit, L
S...Level shift circuit, 5C1SCP, SCN...
・Sense circuit, OL...output latch. MARY...Memory array, SMO~5M31...
Sub memory array, MC...memory cell, CSW...
・Column switch, XAD...X address decoder,
YAD...Y address decoder, XAB...X address decoder, YAB...Y address buffer, DI
B...Data manual buffer, WA...Write amplifier, D. B...Data output banofer, TO...timing generation circuit. Q1~Q17...P channel MOSFET1Q21
~Q46...N channel MOSFET, N1~N9
...CMOS inverter circuit, AG1~AG2...
AND gate circuit, OGl~OG2...OR gate circuit.

Claims (1)

[Claims] 1. A semiconductor memory comprising a read amplifier circuit whose operation is stopped after the logic level of its output signal is determined or its output signal is transmitted to a subsequent output latch. Device. 2. The semiconductor memory device has a so-called multi-bit configuration that simultaneously outputs multiple bits of read data, and is characterized by comprising a plurality of read amplifier circuits and output latches provided corresponding to each bit of the read data. A semiconductor memory device according to claim 1. 3. The above semiconductor memory device is a CMOS static type R
Clocked static RAM whose basic configuration is AM
3. The semiconductor memory device according to claim 1, wherein the read amplification circuit is a sense amplifier. 4. The sense amplifier includes a first sense circuit that determines that the read signal is a logic "0", a second sense circuit that determines that the read signal is a logic "1", and the first sense circuit that determines that the read signal is a logic "1". and a level shift circuit provided in the preceding stage of the second sense circuit, and the above-mentioned level shift circuit provided in the subsequent stage of the first and second sense circuits, and selectively set or reset according to the output signals of these sense circuits. 4. The semiconductor memory device according to claim 1, 2, or 3, further comprising an output latch. 5. The first and second sense circuits are both current mirror type amplifier circuits, and receive complementary read signals transmitted via the complementary common data line corresponding to their respective gates and the level shift circuit, and perform differential reading. N-channel type first and second MOSFETs having a current mirror configuration; A fifth MOSFET is provided between the third and fourth MOSFETs, the commonly coupled sources of the first and second MOSFETs, and the second power supply voltage, and is selectively turned on according to a predetermined timing signal. Claim 1 characterized in that each of the following MOSFETs is included:
4. A semiconductor memory device according to item 1, 2, 3, or 4. 6. Claims 1 and 2, wherein the first and second sense circuits are integrated by sharing the third and fifth MOSFETs.
3. The semiconductor memory device according to item 3, item 4, or item 5. 7. A memory array including a plurality of word lines and complementary data lines arranged orthogonally and a plurality of memory cells arranged in a grid at the intersections of the word lines and complementary data lines, and the word line or complementary data a row-related selection circuit and a column-related selection circuit that selectively select the respective lines; and a read amplifier circuit that amplifies a read signal transmitted from a selected memory cell of the memory array via a complementary common data line. , an output latch that holds the output signal of the read amplification circuit, and after the logic level of the output signal of the read amplification circuit is determined or the output signal of the read amplification circuit is taken into the output latch, the low A semiconductor memory device characterized in that operations of a system selection circuit, a column system selection circuit, and a read amplifier circuit are stopped. 8. The semiconductor memory device has a so-called multi-bit configuration that simultaneously outputs multiple bits of read data, and is characterized by comprising a plurality of read amplifier circuits and output latches provided corresponding to each bit of the read data. A semiconductor memory device according to claim 7.