JP2623462B2 - Semiconductor storage device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, for example, a CMOS (complementary MOS) static RAM (random access) having a current mirror type sense circuit.・ Technology related to technology that is effective for use in memories.

[Conventional technology]

There is a CMOS static RAM in which the memory array and peripheral circuits are configured by CMOS to achieve high-speed operation and low power consumption. Also, in such a CMOS static RAM, as an amplifier circuit for a read signal,
There is a current mirror type sensing circuit used alone or in combination.

The current mirror type sense circuit is described, for example, in Japanese Patent Application Laid-Open No. 62-046486.

[Problems to be solved by the invention]

FIG. 4 shows a circuit diagram of a sense amplifier SA of a CMOS static RAM developed by the present inventors prior to the present invention and a peripheral portion thereof. The sense amplifier SA includes the current mirror type sense circuit SC as described above.

In FIG. 4, a sense circuit SC includes a pair of N-channel MOSFETs Q27 and Q28 in a differential configuration,
A pair of P-channel MOSFETs Q1 and Q1 which are provided between the drain of the MOSFET and the power supply voltage of the circuit and are in the form of a current mirror;
Including Q2. The gates of the MOSFETs Q27 and Q28 have, for example, the corresponding complementary data lines D0 and ▲ ▼ and the complementary common data lines CD and ▲ from the selected memory cell MC of the memory array MARY.
▼ and the complementary read signal sd • ▲ transmitted through the level shift circuit LS are supplied. MOSFETQ2
A drive MOSFET Q13 receiving a timing signal .phi.sa at its gate is provided between the commonly coupled sources of 7 and Q28 and the ground potential of the circuit. This allows the sense circuit SC
Are selectively activated according to the timing signal φsa.

The commonly coupled drains of MOSFETs Q2 and Q28, ie, node n5, are further coupled to the input terminal of CMOS inverter circuit N1. The output signal of the inverter circuit N1 is the inverted output signal ▲ ▼ of the sense circuit SC and is transmitted to the data output buffer DOB.

By the way, between the input terminal of the CMOS inverter circuit N1 and the power supply voltage of the circuit, a P-channel MOSFET Q3 receiving the timing signal φsa at its gate is provided. MOSF
ETQ3 is turned on complementarily to drive MOSFET Q13, and functions as a preset MOSFET for node n5. As a result, when the timing signal φsa is at the low level and the sense circuit SC is in the non-operation state, the input of the node n5, that is, the input of the inverter circuit N1, is fixed at the high level, and the through current is prevented.

However, it has been clarified by the present inventors that the above-described current mirror type sense circuit SC has the following problems. That is, the sense circuit SC
, The corresponding N-channel MOSFETs Q27 and Q28 have a symmetrical structure, and are designed such that the respective constants s3 and s4, that is, the ratios of the respective channel widths to the channel lengths, are substantially the same. Also, the sense circuit
When the SC is deactivated, the level of the node n5 is set to the high level via the MOSFET Q3 as described above.
The level of the drain of the corresponding MOSFET Q27, i.e., node n4, is left indeterminate, e.g., from the supply voltage of the circuit.
This is an unstable level that is reduced by the threshold voltage of MOSFET Q1. For this reason, a level difference occurs between the nodes n4 and n5 at the beginning when the sense circuit SC is brought into the operating state, and particularly, the complementary read signal sd • ▲ is logic “0”.
When the output signal of the CMOS inverter circuit N1 is set to the high level, the sensitivity of the sense circuit SC is selectively reduced. This is due to the fact that the sense circuit SC is a current mirror type, and its amplification gain is smaller than that of a flip-flop type sense amplifier with a positive feedback path. It is one of the factors that hinders.

SUMMARY OF THE INVENTION An object of the present invention is to provide a current mirror type sense circuit which achieves high-speed operation. It is another object of the present invention to speed up a read operation of a CMOS static RAM or the like including a current mirror type sense circuit.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for solving the problem]

The outline of a typical invention disclosed in the present application will be briefly described as follows. That is,
N-channel first and second N-channel type receiving a non-inverted signal and an inverted signal forming a pair as complementary signals at their gates, respectively.
MOSFETs and P-channel third and fourth P-channel MOSFETs which are provided on the drain side of these MOSFETs and have a current mirror configuration.
A current mirror including a MOSFET, a CMOS inverter circuit having an input terminal coupled to the drain of the second MOSFET, and a preset MOSFET provided between an input terminal of the CMOS inverter circuit and a power supply voltage of the circuit. In the sense circuit of the type, the constant of the second or third MOSFET, that is, the ratio of the channel width to the channel length is designed to be larger than the constant of the first or fourth MOSFET. is there.

[Action]

According to the above-described means, the sensitivity of the sense circuit to the logic "0" input of the complementary signal can be made larger than the sensitivity to the logic "1" input, so that the amplification operation of the sense circuit can be speeded up overall. . This makes it possible to speed up the read operation of the CMOS static RAM including the current mirror type sense circuit.

〔Example〕

FIG. 2 is a circuit block diagram of one embodiment of a CMOS static RAM to which the present invention is applied. Each circuit element in FIG. 1 is not particularly limited by a known CMOS integrated circuit manufacturing technique, but may be made of a single-crystal silicon.
It is formed on individual semiconductor substrates. In the following figures, an arrow is added to the channel (back gate) part
The MOSFET is of the P-channel type, and is distinguished from the N-channel MOSFET without an arrow.

In FIG. 2, a CMOS static RA of this embodiment is shown.
M has a basic configuration of a memory array MARY arranged so as to occupy most of the area of the semiconductor substrate.

Although not particularly limited, the memory array MARY includes (m + 1) word lines W0 to W0 arranged in parallel in the horizontal direction in FIG.
Wm and (m + 1) × (n) arranged at the intersection of (n + 1) sets of complementary data lines D0 • ▲ to Dn • ▲ ▼ arranged in parallel in the vertical direction and these word lines and complementary data lines.
+1) static memory cells MC.

Although each memory cell MC constituting the memory array MARY is not particularly limited, as illustrated in FIG.
It includes two CMOS inverter circuits consisting of a channel MOSFET Q4 and an N-channel MOSFET Q19 and a P-channel MOSFET Q5 and an N-channel MOSFET Q20. These CMOS
The inverter circuit constitutes a latch serving as a storage element of a CMOS static RAM by having its input terminal and output terminal cross-connected to each other. In addition, the input terminal and the output terminal of these CMOS inverter circuits that are commonly coupled are:
These are input / output nodes of each latch. The input / output node of the latch of the (n + 1) memory cells MC arranged on the same row of the memory array MARY is an N-channel transmission gate MOSFET.
Via the corresponding complementary data lines D0 and ▲ via Q21 and Q22, etc.
Commonly connected to ▼ to Dn ・ ▲ ▼. Also,
The gates of the transmission gate MOSFETs Q21 and Q22 and the like of the (m + 1) memory cells MC arranged in the same column of the memory array MARY are commonly connected to the corresponding word lines W0 to Wm.

The word lines W0 to Wm forming the memory array MARY are coupled to the X address decoder XAD and are selectively selected. The X address decoder XAD supplies the (i + 1) -bit complementary internal address signal a x0 to
a xi (here, for example, the non-inverted internal address signal ax0 and the inverted internal address signal ▼ are collectively represented as a complementary internal address signal ax0; the same applies hereinafter).
Further, the timing signal φce
Is supplied. The timing signal φce is not particularly limited, but is set to a high level at a predetermined timing when the CMOS static RAM is selected.

The X address decoder XAD outputs the timing signal φce
Is set to the high level, thereby selectively operating. In this operation state, the X address decoder XAD
Decodes the complementary internal address signals a x0 to a xi and selectively sets the corresponding word line of the memory array MARY to a high level selection state.

The X address buffer XAB captures and holds i + 1-bit X address signals AX0 to AXi supplied via the external terminals AX0 to AXi. Also both these X address signal AX0～AXi, complementary internal address signals a x0~ a xi
And supplies it to the X address decoder XAD.

On the other hand, the complementary data lines D0
▲ ▼ to Dn ・ ▲ ▼ are not particularly limited, but on the other hand, the corresponding P-channel type precharge
Coupled to the supply voltage of the circuit via MOSFETs Q6, Q7 to Q8, Q9, and on the other hand, the corresponding switches MOSFETs Q23, Q24 to Q25, Q26 and Q31, Q32 to Q33 of the column switch CSW.
.Selective complementary data line CD via Q34.
Connected to. Between the non-inverted signal line and the inverted signal line of the complementary common data line CD • ▲ and the power supply voltage of the circuit, P
Channel type precharge MOSFETs Q35 and Q36 are provided. Here, the power supply voltage of the circuit is not particularly limited, but is a positive power supply voltage such as +5 V, for example.

Precharged MOSFETs Q6 / Q7 to Q8 / Q9 and Q3
The timing signal φce is commonly supplied from the timing generation circuit TG to the gates of 5 and Q36. These precharge MOSFETs are selectively turned on when the CMOS static RAM is deselected and the timing signal φce is set to low level, and the corresponding complementary data line is turned on.
D0 ・ ▲ ▼ ~ Dn ・ ▲ ▼ and complementary common data line
The non-inverting signal line and the inverting signal line of CD and ▼ are precharged to a high level such as the power supply voltage of the circuit. When the CMOS static RAM is set to the selected state and the timing signal φce is set to the high level, these precharges are turned off.

Although the column switch CSW is not particularly limited, the complementary data lines D0 ・ ▲ to Dn ・ ▲ ▼ of the memory array MARY are used.
N + 1 pairs of complementary switch MOSFETs 23 provided corresponding to
-Includes Q24-Q25-Q26 and Q31-Q32-Q33-Q34. The gates of each pair of switch MOSFETs are commonly coupled, and Y
The corresponding data line selection signal Y0 from the address decoder YAD
To Yn or inverted signals from the inverter circuits N6 to N7 are supplied. Each of the switch MOSFETs of the column switch CSW is turned on when the data line selection signals Y0 to Yn are alternatively set to a high level, and is complementary to the corresponding complementary data lines D0, ▲ ▼ to Dn, ▲ ▼. Selectively connect data lines CD and ▲ ▼.

The Y address decoder YAD has a Y address buffer YAB
To j + 1-bit complementary internal address signals a y0 to a yj, and the timing signal φce from the timing generation circuit TG. Y address decoder YAD
By setting the timing signal φce to a high level,
The operation state is selectively set. In this operating state, Y
The address decoder YAD outputs the complementary internal address signal a y
0 to a yj by decoding the corresponding said data line selection signal Y0~Yn and alternatively a high level.

The complementary common data lines CD • ▲ ▼ are coupled to the input terminal of the sense amplifier SA and to the output terminal of the write amplifier WA. Inverted output signal of sense amplifier SA
▼ is coupled to the input terminal of the data output buffer DOB. The output terminal of data output buffer DOB is further coupled to data input / output terminal DIO. In sense amplifier SA,
The timing signal φsa is supplied from the timing generation circuit TG. Further, the data output buffer DOB is supplied with the timing signal φoe and the timing signal φsa from the timing generation circuit TG. Here, the timing signal φ
Although sa is not particularly limited, sa is set to a high level at a predetermined timing when the CMOS static RAM is selected in the read operation mode. Similarly, the timing signal φoe is output enable signal ▲ when the static RAM is selected in the read operation mode.
In accordance with ▼, the signal is set to the high level after the timing signal φsa. On the other hand, the input terminal of the write amplifier WA is coupled to the output terminal of the data input buffer DIB. The input terminal of the data input buffer DIB is not particularly limited, but is further commonly connected to the data input / output terminal DIO. The write amplifier WA is supplied with a timing signal φwe from the timing generation circuit TG. Here, the timing signal φwe
Is temporarily set to a high level at a predetermined timing when the CMOS static RAM is selected in the write operation mode.

The sense amplifier SA includes a level shift circuit LS and a sense circuit SC, as described later. The input terminal of the level shift circuit LS is coupled to the complementary common data line CD. The output terminal thereof is coupled to the input terminal of the sense circuit SC. The output signal of the sense circuit SC is the inverted output signal ▼ of the sense amplifier SA. The level shift circuit LS and the sense circuit SC of the sense amplifier SA are selectively activated when the timing signal φsa is set to the high level. In this operating state, the level shift circuit
LS senses the level of the read signal output from the selected memory cell MC of the memory array MARY via the corresponding complementary data line D00-Dn ・ and the complementary common data line CD ・. The sensitivity of the circuit SC shifts to the highest level. The sense circuit SC amplifies the complementary read signal transmitted via the level shift circuit LS to form the inverted output signal 出力.

The data output buffer DOB includes an output latch and an output buffer for receiving the inverted output signal を 受 け る of the sense amplifier SA as described later. Of these, the output latch is
When the CMOS static RAM is set to the read operation mode and the timing signal φsa is set to the high level, the inverted output signal ▲ ▼ of the sense amplifier SA is taken in.
Hold this. Similarly, when the CMOS static RAM is in the read operation mode and the timing signal φoe is at the high level, the output buffer forms read data in accordance with the inverted output signal ▲ ▼, and the data input / output terminal DIO To the outside via. When the timing signal φoe is at a low level, the output of the output buffer of the data output buffer DOB is in a high impedance state.

Specific circuit configurations and operations of the sense amplifier SA and the data output buffer DOB will be described later in detail.

On the other hand, in the write operation mode of the CMOS static RAM, the data input buffer DIB stores write data supplied from the outside via the data input / output terminal DIO.
Transmit to the light amplifier WA.

The write amplifier WA is selectively activated by setting the CMOS static RAM to the write operation mode and setting the timing φwe to the high level. In this operation state, the write amplifier WA uses the write data transmitted via the data input buffer DIB as a complementary write signal, and via the complementary common data line CD
Supply to the selected memory cell MC. Although not particularly limited, when the timing signal φwe is at a low level, the output of the write amplifier WA is in a high impedance state.

The timing generation circuit TG forms the various timing signals described above based on a chip enable signal ▼, a write enable signal ▼, and an output enable signal ▲ which are supplied as control signals from the outside, and supplies the signals to each circuit. .

FIG. 1 is a circuit diagram showing one embodiment of the sense amplifier SA and the data output buffer DOB of the CMOS static RAM shown in FIG. Although FIG. 3 partially shows some circuits related to the memory array MARY, the description is omitted because it is the same as FIG.

In FIG. 1, the sense amplifier SA includes, but is not limited to, a level shift circuit LS and a sense circuit SC.

The level shift circuit LS of the sense amplifier SA is not particularly limited, but is a pair of N-channel MOSFETs in a differential form.
Q14 and Q15 and another pair of N-channel MOSFETs Q16 and Q17 provided on the source side of these MOSFETs. MO
The drains of SFETs Q14 and Q15 are coupled to the supply voltage of the circuit, and the commonly coupled sources of MOSFETs Q16 and Q17 are coupled to the circuit's ground potential via N-channel MOSFET Q18. The gates of the MOSFETs Q14 and Q15 are respectively coupled to the non-inverted signal line CD and the inverted signal line ▲ of the complementary common data line. The gate of MOSFET Q16 is coupled to its drain and is commonly coupled to the gate of MOSFET Q17.
Thus, MOSFETs Q16 and Q17 are in a current mirror form. The gate of the MOSFET Q18 has a timing generator TG
Supplies the above-mentioned timing signal φsa. MOSFET
The source potentials of Q14 and Q15 are determined by the complementary read signal sd
As ▼, it is supplied to the sense circuit SC.

When the CMOS static RAM is selected in the read operation mode and the timing signal φsa is set to the high level, the MOSFET Q18 is turned on and the level shift circuit L
S is set to the operating state. At this time, the level shift circuit LS
The gates of the MOSFETs Q14 and Q15 have complementary data lines D0 and ▲ ▼ from the selected memory cell MC of the memory array MARY.
A predetermined read signal is supplied via the complementary common data line CD. As described above, when the CMOS static RAM is deselected, the memory array MAR
The Y complementary data lines D0 ・ -Dn ・ are precharged to a high level such as the power supply voltage of the circuit. Therefore, the read signal has a relatively high level close to the power supply voltage of the circuit as its central level.

As described above, since the center level of the read signal transmitted via the complementary common data lines CD • ▲ is set to a relatively high level, both the MOSFETs Q14 and Q15 of the level shift circuit LS are turned on. Therefore, MOSFET Q14
And the source potential of Q15, that is, the complementary read signal sd
▼ changes in phase with the read signal around a predetermined bias level determined by the conductance ratio between the MOSFETs Q14 and Q16 or the MOSFETs Q15 and Q17. In this embodiment, the bias level is determined by the sense circuit SC.
Is set to the level at which the sensitivity is highest. That is, the read signal transmitted via the complementary common data line CD • ▲ ▼ is level-shifted by the level shift circuit LS, and the complementary read signal sd • having an effective bias level that maximizes the sensitivity of the sense circuit SC. It becomes ▲ ▼.

Although not particularly limited, the sense circuit SC of the sense amplifier SA has a pair of N-channel (first conductivity type) MOSFETs Q11 (first MOSFET) and Q12 (second MOSFET) in a differential form.
ET) and a pair of P-channel (second conductivity type) MOSFETs Q1 (third MO) provided on the drain side of these MOSFETs.
SFET) and Q2 (fourth MOSFET). MOSFET Q1 and
The source of Q2 is coupled to the circuit's power supply voltage (first power supply voltage), and an N-channel MOSFET Q13 is connected between the commonly coupled sources of MOSFETs Q11 and Q12 and the circuit's ground potential (second power supply voltage). (Fifth MOSFET) is provided. MOSFETQ
The gate of 1 is commonly coupled to its drain,
Coupled to the gate of FETQ2. As a result, the MOSFETs Q1 and Q2 are in a current mirror form. The output signal of the level shift circuit LS, that is, the complementary read signal sd ・ is supplied to the gates of the MOSFETs Q11 and Q12. Also,
The timing signal φsa is supplied to the gate of the MOSFET Q13.

In this embodiment, although the MOSFET Q12 is not particularly limited, its constant s2, that is, the ratio W2 / L2 of the channel width W2 to the channel length L2 is equal to the constant s1 of the MOSFET Q11.
That is, the channel width W1 is designed to be larger than the ratio W1 / L1 to the channel length L1, and the ratio is not particularly limited, but is set to be in the range of s2 / s1 = 1.1 to 1.4. .

The drain of MOSFET Q12, node n2, is also
It is coupled to the input terminal of S inverter circuit N1. Between the input terminal of the inverter circuit N1 and the power supply voltage of the circuit,
The gate thereof is provided with a P-channel type preset MOSFET Q3 (sixth MOSFET) for receiving the timing signal φsa. The output signal of the inverter circuit N1 is the sense amplifier SA
Is the inverted output signal ▲ ▼.

When the CMOS static RAM is deselected and the timing signal φsa is low, the sense circuit
The SC drive MOSFET Q13 is turned off and the preset MOSFET
TQ3 turns on. Therefore, the sense circuit SC is deactivated, and the drain potentials of the MOSFETs Q11 and Q12 are
Both try to reach an uncertain level. However, as described above, since the preset MOSFET Q3 is turned on, the MO
The drain of the SFET Q12, that is, the node n2, is set to a high level like the power supply voltage of the circuit. As a result, the output signal of the inverter circuit N1, that is, the inverted output signal ▼, is fixed at the low level. As a result, through current of the CMOS inverter circuit N1 is prevented, and low power consumption of the CMOS static RAM is achieved.

On the other hand, when the CMOS static RAM is selected in the read operation mode and the timing signal φsa is set to the high level, the drive MOSFET Q13 is turned on and the preset MOSFET Q3 is turned off. Therefore, the sense circuit SC is set to the operation state, and the complementary read signal sd
Is performed. As a result, the level of the node n2 is changed in the opposite phase according to the complementary read signal sd. That is, when the complementary read signal sd ・ is set to logic “0” and the non-inverted signal sd is made lower than the inverted signal ▼, the level of the node n2 is set to a low level lower than the center level, thereby The output signal ▲ ▼ is set to the high level. On the other hand, when the complementary read signal sd ・ is set to logic “1” and the non-inverted signal sd is made higher than the inverted signal ▼, the level of the node n2 is set to a high level higher than the center level, thereby The inverted output signal ▲ ▼ is at the low level.

By the way, in this embodiment, the MOSF of the sense circuit SC
ETQ12 is, as described above, its constant s2 is the constant of MOSFET Q11.
It is designed to be larger at a predetermined ratio than s1. Therefore, the substantial logic threshold level of the sense circuit SC as viewed from the inverted signal line ▲ ▼ is made higher than the substantial logic threshold level of the sense circuit SC as viewed from the non-inverted signal line sd. Therefore, the sensitivity when the input signal of the inverter circuit N1 of the sense circuit SC, that is, the potential of the node n2 is set to the low level, is lower than the sensitivity of the node n2.
Is higher than the sensitivity when the potential of the potential is set to the high level. As a result, the complementary read signal of the sense circuit SC
The sensitivity to the logic "0" input of sd • ▲ ▼ is selectively increased.

On the other hand, the complementary read signal sd
・ By selectively increasing the sensitivity to the logic “0” input of ▲ ▼, the complementary read signal sd
On the contrary, the sensitivity to the logic “1” input of ▲ ▼ is reduced. However, as described above, the level of the node n2 is CM
It is preset to a high level when the OS static RAM is in the non-selected state. Therefore, the complementary read signal
When sd • ▲ ▼ is set to logic “1”, the level of the node n2 is quickly set to the high level. Therefore, there is no problem that the sensitivity of the sense circuit SC to the logical "1" input of the complementary read signal sd • ▲ is reduced. From these facts, the operation of the sense circuit SC is speeded up overall, and the reading operation of the CMOS static RAM is speeded up.

Although the data output buffer DOB is not particularly limited, the CMO
It includes an output latch configured by cross-connecting input terminals and output terminals of S inverter circuits N3 and N4, and a tri-state output buffer OB1. The output terminal of the inverter circuit N3 which constitutes the output latch includes, but is not particularly limited to, a P-channel MOSFET Q1 in a parallel form.
The inverted output signal ▼ of the sense amplifier SA is supplied via a transmission gate composed of the 0 and N-channel MOSFET Q29. The inverted signal of the timing signal φsa by the CMOS inverter circuit N5 is supplied to the gate of the MOSFET Q10, and the timing signal φsa
Is supplied. The transmission gate has a timing signal φsa
Is set to a high level, thereby selectively entering a transmission state. At this time, the inverted output signal of the sense amplifier SA
Is taken into the output latch composed of the inverter circuits N3 and N4. As a result, the level of the inverted output signal ▼ in the data output buffer DOB is corrected.

The inverted output signal ▲ ▼ of the sense amplifier SA is not particularly limited, but after being inverted by the CMOS inverter circuit N2 of the data output buffer DOB, the output buffer OB1
Is supplied to one of the input terminals. The above-mentioned timing signal φoe is supplied from the timing generation circuit TG to the other input terminal of the output buffer OB1. The output buffer OB1 is
Although not particularly limited, the output buffer is a tri-state output buffer, and the output thereof is such that the timing signal φoe is at a high level and the output signal of the inverter circuit N2, that is, the non-inverted output signal do of the sense amplifier SA is at a high level. At this time, it is selectively set to the high level. When the timing signal φoe is at high level and the non-inverted output signal do is at low level at the same time, the output of the output buffer OB1 is selectively at low level. Timing signal φ
When oe is at a low level, the output of the output buffer OB1 is in a high impedance state.

FIG. 3 shows a timing chart of one embodiment of the read operation mode of the CMOS static RAM of FIG. In the figure, in order to clarify the difference in operation of the sense circuit SC when the complementary read signal sd • ・ is set to logic “0” and logic “1”, the read operation mode for two cycles is continuous. Are shown. The outline of the read operation mode of the CMOS static RAM according to this embodiment will be described with reference to FIG. 3 and FIGS. 1 and 2.

In FIG. 3, the CMOS static RAM is set to a selected state by changing the chip enable signal ▲ from a high level to a low level. Prior to the low level change of the chip enable signal ▼, the write enable signal ▼ is set to the high level, and the read operation mode is designated. The external terminals AX0 to AXi are connected to the X address signal AX0.
AXi are supplied in a combination that specifies a row address raa, and external terminals AY0 to AYj are supplied with a Y address signal AY0 to AYj in a combination that specifies a column address ca0. Further, after a predetermined time has elapsed since the chip enable signal 信号 was set to the low level, the output enable signal ▼ is temporarily set to the low level.

In the CMOS static RAM, the timing signal φce is first set to the high level by setting the chip enable signal ▲ ▼ to the low level, and the timing signal φsa is set to the high level with a slight delay. Further, when the output enable signal ▼ is temporarily set to the low level, the timing signal φoe is temporarily set to the high level.

By setting the timing signal φce to a high level, X
The address decoder XAD and the Y address decoder YAD are activated, and the row address signal raa of the memory array MARY is set.
Is alternatively set to the high level, and the data line selection signal Y0 corresponding to the column address ca0 is alternatively set to the high level. As a result, the (n + 1) memory cells MC coupled to the word line of the memory array MARY are set to the selected state, and a read signal corresponding to the stored data is supplied to the corresponding complementary data line D0 • ▲ ▼ to Dn • ▲ ▼. Is output. Of these, the complementary data line D0 • ▲ ▼ corresponding to the column address ca0 is connected to the column switch CS.
It is selected by W and connected to the complementary common data line CD • ▲ ▼. As a result, the read signal of one memory cell MC specified by the row address raa and the column address ca0 is transmitted to the sense amplifier SA via the complementary data lines D0 ・ and the common data lines CD ・. Is done. In the first read cycle of the embodiment shown in FIG. 3, the storage data held in one selected memory cell MC is set to logic "0".

In the sense amplifier SA, when the timing signal φsa is set to the high level, the level shift circuit LS and the sense circuit
The SC enters the operating state. Therefore, the complementary common data line CD
The read signal input via ▲ is first level-shifted by the level shift circuit LS to form a complementary read signal sd ・ having a predetermined bias level. This complementary read signal sd • ▲ is further amplified by the sense circuit SC. As a result, the node
n2 is set to the low level.

In the CMOS static RAM of this embodiment, the sensitivity when the node n2 of the sense circuit SC is at a low level is higher than the sensitivity when the node n2 is at a high level. For this reason, the amplification operation by the sense circuit SC is relatively accelerated, and the node n2 is rapidly set to the low level.

When the node n2 is set to the low level, the output signal of the CMOS inverter circuit N1, that is, the inverted output signal ▼ of the sense amplifier SA is set to the high level like the power supply voltage of the circuit. Since the timing signal φsa is already at the high level at this time, the inverted output signal ▲ ▼ is taken into the output latch of the data output buffer DOB, and the timing signal φoe is temporarily set to the high level. As a result, the data is sent to the outside as read data of logic “0” via the output buffer OB1 of the data output buffer DOB and the data input / output terminal DIO.

When the chip enable signal ▼ and the output enable signal ▼ are returned to the high level, the CMOS static RAM is set to a non-selected state, and each circuit is set to a non-operating state.

Next, the chip enable signal ▼ changes from the high level to the low level again. Prior to the low level change of the chip enable signal ▲ ▼, the external terminal AX
X address signals AX0 to AXi have row address ra
b is supplied in a combination that specifies b, and external terminals AY0 to
In AYj, the Y address signals AY0 to AYj correspond to the column address ca0.
Are supplied in a combination that specifies The write enable signal ▲ ▼ is still kept at the high level.

In the CMOS static RAM, the same operation as in the first read cycle is performed by setting the chip enable signal ▼ to a low level, and as a result, 1 specified by the row address rab and the column address ca0 is obtained.
Read signals from the memory cells MC are transmitted to the sense amplifier SA via the corresponding complementary data lines D00 and complementary common data lines CD ・. In the second read cycle of this embodiment, the storage data held in one selected memory cell MC is set to logic "1". Therefore, when the timing signal φsa is set to the high level, the node of the sense circuit SC of the sense amplifier SA is
Although the potential of n2 is slightly lowered, it is not lowered below the logic threshold level of CMOS inverter circuit N1.

In the CMOS static RAM of this embodiment, the sensitivity when the node n2 of the sense circuit SC is kept at a high level is smaller than the sensitivity when the node n2 is at a low level. For this reason, the amplification operation by the sense circuit SC is made relatively slow, but there is no problem because it is a read operation of logic "1" in which the level of the node n2 is kept at the high level.

Since the level of the node n2 is kept at the high level, the output signal of the CMOS inverter circuit N1, that is, the inverted output signal of the sense amplifier SA is kept at the low level such as the ground potential of the circuit. This inverted output signal ▲
Since the timing signal φsa is already at the high level at this time, the data output buffer DO
The output latch OB1 of the data output buffer DOB and the data input / output terminal DI
Via O, it is transmitted as read data of logic “1”.

As described above, the CMOS static RAM of this embodiment
Is a sense amplifier SA including a current mirror type sense circuit SC.
Is provided. The sense circuit SC includes a non-inverted signal sd and an inverted signal
N-channel MOSFETs each receiving ▼ and being in differential form
It includes Q11 and Q12, and P-channel MOSFETs Q1 and Q2 provided on the drain side of these MOSFETs and configured as a current mirror. The sense circuit SC further has an input terminal as described above.
CMOS inverter circuit N coupled to the drain of MOSFET Q12
1 and a preset MOSFET Q3 provided between the input terminal of the CMOS inverter circuit N1 and the power supply voltage of the circuit. In this embodiment, the constant s2 of the MOSFET Q12, that is, the ratio of the channel width W2 to the channel length L2
W2 / L2 is increased with respect to the constant s1 of the MOSFET Q11, that is, the ratio W1 / L1 of the channel width W1 to the channel length L1. For this reason, the sensitivity of the sense circuit SC to the logic "0" input of the complementary read signal sd.multidot..quadrature. Is increased compared to the sensitivity to the logic "1" input.
As a result, the operation of the sense circuit SC is generally accelerated, and the CMOS including the current mirror type sense circuit SC is used.
The reading operation of the static RAM is speeded up.

As shown in the above embodiments, when the present invention is applied to a semiconductor memory device such as a CMOS static RAM, the following effects can be obtained. That is, (1) N-channel type first and second MOSFETs which receive a pair of a non-inverted signal and an inverted signal as complementary signals at their gates, respectively, and a current mirror type provided on the drain side of these MOSFETs. P-channel third and fourth MOSFETs, a CMOS inverter circuit having an input terminal coupled to the drain of the second MOSFET, and a power supply voltage between the input terminal of the CMOS inverter circuit and the circuit. In the current mirror type sense circuit including a preset MOSFET provided, the constant of the second or third MOSFET, that is, the ratio of the channel width to the channel length is set to the constant of the first or fourth MOSFET. By designing it to be relatively large, the sensitivity of the sense circuit to the logical "0" input of the complementary signal is large compared to the sensitivity to the logical "1" input. The effect that it can be obtained is obtained.

(2) According to the above item (1), an effect is obtained that the operation of the current mirror type sense circuit can be speeded up comprehensively.

(3) According to the above items (1) and (2), an effect is obtained that the reading operation of a CMOS static RAM or the like including a current mirror type sensing circuit can be speeded up.

Although the invention made by the inventor has been specifically described based on the embodiments, the invention is not limited to the above-described embodiments, and various changes can be made without departing from the gist of the invention. Nor. For example, in the sense circuit SC of FIG. 1, the ratio between the constant s2 of the MOSFET Q12 and the constant s1 of the MOSFET Q11 can take any value. Also, the MOSFETs Q11 and Q12 have the same constant, and
The constant of ETQ1 may be increased compared to the constant of MOSFET Q2, or the constants of both MOSFETs Q12 and Q1 may be
It may be larger than the constants of 11 and Q2. MOSF
The gates of ETQ11 and Q12 have complementary read signals sd
▼ may be supplied inverted. In this case, the output signal of the CMOS inverter circuit N1 becomes the non-inverted output signal do. MOSFET Q3 for preset is N channel
It may be constituted by a MOSFET. Further, the sense circuit SC may be configured by symmetrically combining a plurality of current mirror type amplifier circuits. In FIG. 2, the memory array MARY may be composed of a plurality of memory mats, and the memory cell MC may be a high resistance load type static memory cell. cm
The OS static RAM may not include a column selection circuit, or may simultaneously input and output a plurality of bits of storage data. The output enable signal ▲ ▼ is not essential. Further, there are various circuit configurations such as a specific circuit configuration of the sense circuit SC, the level shift circuit LS, and the data output buffer DOB shown in FIG. 1, and a combination of a block configuration of the CMOS static RAM shown in FIG. Can be adopted.

In the above description, the case where the invention made by the present inventor is mainly applied to the CMOS static RAM, which is the application field in the background, has been described. However, the present invention is not limited to this. The present invention can also be applied to a semiconductor memory device of The present invention can be widely applied to a semiconductor memory device having at least a current mirror type sensing circuit or a digital integrated circuit device incorporating such a semiconductor memory device.

〔The invention's effect〕

The effects obtained by the representative inventions among the inventions disclosed in the present application will be briefly described as follows. That is, first and second N-channel MOSFETs each receiving a pair of a non-inverted signal and an inverted signal as complementary signals at their gates, and a P-channel mirror provided on the drain side of these MOSFETs in a current mirror form. Type third and fourth MOSFETs and their input terminals are
A CMOS inverter circuit coupled to the drain of the MOSFET,
In a current mirror type sense circuit including a preset MOSFET provided between an input terminal of the CMOS inverter circuit and a power supply voltage of the circuit, the second or third MOSFET
, That is, the ratio of the channel width to the channel length is made larger than the constant of the first or fourth MOSFET, whereby the operation of the sense circuit can be speeded up overall. As a result, the read operation of a CMOS static RAM or the like including a current mirror type sense circuit can be sped up.

[Brief description of the drawings]

FIG. 1 shows a CMOS static RA to which the present invention is applied.
FIG. 2 is a circuit diagram showing an embodiment of an M sense amplifier and a data output buffer; FIG. 2 is a circuit block diagram showing an embodiment of a CMOS static RAM including the sense amplifier and the data output buffer of FIG. 1; FIG. 2 is a timing chart showing an embodiment of a read operation mode of the CMOS static RAM shown in FIG. 2, and FIG. 4 is a circuit diagram showing an example of a sense amplifier of a conventional CMOS static RAM and peripheral parts thereof. . SA: Sense amplifier, LS: Level shift circuit, SC:
Sense circuit, DOB data output buffer, MARY memory array, MC memory cell, CSW column switch. XAD: X address decoder, YAD: Y address decoder, XAB: X address buffer, YAB: Y address buffer, DIB: Data input buffer, WA: Write amplifier, TG: Timing generation circuit. Q1-Q10, Q31-Q36 ... P-channel MOSFET, Q11-Q29 ...
… N-channel MOSFET, N1 to N7 …… Inverter circuit, OB
.... Output buffer.

Continuation of the front page (72) Inventor Hisaaki Kobayashi 1448, Kamizuhoncho, Kodaira-shi, Tokyo Inside Hitachi Super-LSI Engineering Co., Ltd. (56) References JP-A-59-119589 (JP, A) JP-A Sho JP-A-63-74196 (JP, A) JP-A-62-39299 (JP, U)

Claims (2)

(57) [Claims] A first conductive type first and second MOSFET having a gate supplied with a complementary signal read from a memory cell, and drains of the first and second MOSFETs; Third and fourth MOSFETs of a second conductivity type provided between the power supply voltage and a current mirror, and a common source of the first and second MOSFETs and a ground potential point of the circuit. And a fifth MOSFET of a first conductivity type, which is switch-controlled by an operation timing signal, and a MOSFET which is an output side of the third and fourth MOSFETs in the current mirror form. Sixth MOSFET of second conductivity type in parallel form and supplied with the operation timing signal
And a CM for receiving a differentially amplified signal by the first and second MOSFETs
A sense amplifier including an OS inverter circuit, wherein the drains of the first and third MOSFETs are shared, and the drains of the second and fourth MOSFETs are shared. The constant s, which is the ratio W / L of the channel length L to the channel width W in each of the four MOSFETs, is the ratio s2 / s1 of the constant s3 of the third MOSFET to the constant s1 of the first MOSFET. A semiconductor memory device characterized by being larger than a ratio s4 / s2 of a constant s4 of the third MOSFET to a constant s2 of the MOSFET. 2. The complementary signal is a read signal from a CMOS static memory cell, and is passed through a level shift circuit comprising a pair of source follower MOSFETs and an additional MOSFET of a current mirror type provided at the source of the source follower MOSFET. 2. The semiconductor memory device according to claim 1, wherein the information is transmitted.