JP2840068B2 - Dynamic RAM - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dynamic RAM, and more particularly to a technique effective for a dynamic RAM having a large storage capacity. 2. Description of the Related Art A 1-bit memory cell MC in a dynamic RAM comprises an information storage capacitor Cs and an address selection MOSFET Qm, and has logic "1", "1".
The information of "0" is stored in the form of whether or not there is a charge in the capacitor Cs.
This is performed by turning on TQm, connecting the capacitor Cs to the common data line D, and sensing how the potential of the data line D changes depending on the amount of charge stored in the capacitor Cs. In the case of a high-integration large-capacity memory array, small memory cells are formed, and many memory cells are connected to a common data line D. Accordingly, the ratio between the capacitor Cs and the stray capacitance Co of the common data line D, that is, Cs / Co becomes a very small value. In the development of a dynamic RAM having a storage capacity of about 1 Mbit, since the elements constituting the memory cell are miniaturized, the ratio of Cs / Co is further reduced, and a large storage capacity is required. It has become a bottleneck in doing. The inventors of the present invention have studied the stray capacitance of the data line, and have found that the capacitance value of the stray capacitance Co of the common data line D can be reduced by circuit means. That is, the data line is divided, and a common sense amplifier is arranged at the division point via the transmission gate MOSFET. As a result, the data line length and the number of memory cells connected to the data line can be halved, so that the stray capacitance Co can be halved. However, it is apparent that the following problem arises when a half precharge system is employed in which a data line is precharged to about 1/2 power supply voltage and is used as a read reference voltage. became. That is, a page mode in which a row (X) address is fixed and one word line is selected, and a column (Y) address is switched to perform continuous reading / writing in the column (Y) direction. In the static column mode, the data lines on the non-selected word lines hold the half precharge level in a floating state during this period. In this case, there is a possibility that the precharge level of the data line on the non-selection side may fluctuate due to coupling noise, a leak current at the PN junction of the address selection MOSFET coupled to the data line, or the like. Since this half precharge level is used as a read reference voltage of a memory cell, the level fluctuation causes a deterioration in an operation margin. [0006] As for the dynamic RAM,
For example, see JP-A-51-74535. For the dynamic RAM having the static column mode function, see, for example, pages 169 to 193 of “Nikkei Electronics” dated July 18, 1983 by Nikkei McGraw-Hill. SUMMARY OF THE INVENTION An object of the present invention is to provide a dynamic RAM in which the operation is stabilized. The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings. Means for Solving the Problems The following is a brief description of an outline of typical inventions disclosed in the present application. That is, a level compensating circuit is provided for each of the complementary data lines divided around the sense amplifier, and a current for compensating the precharge level is supplied to the complementary data lines whose word lines are not selected via the switch gate MOSFET. Is what you do. Embodiments of the present invention will be described below in detail with reference to the drawings. In all the drawings for describing the embodiments, components having the same functions are denoted by the same reference numerals, and repeated description thereof will be omitted. FIG. 1 is a schematic diagram showing a main part of an embodiment of a memory array section in a dynamic RAM according to the present invention. Although not particularly limited, a unit memory array is constituted by a pair of memory arrays MARY-L and MARY-R divided in the data line direction as shown by a broken line in FIG. That is, each of the above memory arrays MARY
−L and MARY-R are divided into two parts on the left and right in FIG. 3, and a common sense amplifier SA is provided at the center.
A pair of input / output nodes of the sense amplifier SA are connected to the complementary data line D and bar D on the left side and to the complementary data line D on the right side via transmission gate MOSFETs Q5 and Q6 (Q7 and Q8) and transmission gate MOSFETs Q9 and Q10 (Q11 and Q12). Each is coupled to a data line (not shown). As a result, the length of one data line and the number of memory cells to be coupled are halved, so that the stray capacitance Co (not shown) of the data line can be reduced. Thus, the level of a read signal from a memory cell appearing on the data line can be increased. Although not particularly limited, the sense amplifier SA is constituted by a CMOS latch circuit. That is,
The sense amplifier SA is configured by cross-coupled inputs and outputs of two CMOS inverter circuits.
P channel MOSF constituting the sense amplifier SA
The source of ET is shared with the source of a similar P-channel MOSFET of another sense amplifier SA, and the power supply voltage Vcc is supplied via a P-channel type switch MOSFET Q15. The source of the N-channel MOSFET constituting the sense amplifier SA is shared with the source of the similar N-channel MOSFET of the other sense amplifiers SA to form an N-channel switch MOS.
The ground potential of the circuit is supplied via the FET Q14. The sense amplifier SA is a switch MOSFET as described above.
When the power supply voltage Vcc and the ground potential of the circuit are supplied via Q15 and Q14, the operation state is set. A 1-bit memory cell is composed of an information storage capacitor Cs and an address selection MOSFET Qm as shown as a representative, and has a logic "1", "1".
The information of "0" is stored in the form of whether or not there is a charge in the capacitor Cs. To read the information, the MOSFET Qm is turned on, the capacitor Cs is connected to the common data line D or D, and the data line D ( Alternatively, the change is performed by sensing how the potential of D) changes depending on the amount of charge stored in the capacitor Cs. That is, when the word line of the left memory array MARY-L is selected. Since the left transmission gate MOSFETs Q5 to Q8 are turned on by the high level of the timing signal φL, the sense amplifier SA is coupled to the data line of the left memory array MARY-L, and the capacitor of the selected memory cell is This is to amplify a potential change in accordance with the amount of charge stored in Cs. To detect a minute signal, the complementary data lines D, bars D are precharged to approximately half the supply voltage Vcc / 2. In other words,
Between the pair of input / output nodes of the sense amplifier SA, there are provided precharge MOSFETs Q16 and Q17 for short-circuiting the pair. In order to perform the level compensation of the precharge level during the chip non-selection period, a pair of operating voltage supply lines of the sense amplifier SA are connected to the MOSFET Q18.
Vcc / formed by voltage dividing resistors R3 and R4 through
2 are supplied. When the MOSFET Q18 is turned on by the timing signal φp,
The operating voltage supply terminal of the sense amplifier SA is short-circuited MOSFE
Shorted by TQ13. According to this embodiment, in accessing a memory cell, the data lines of memory arrays MARY-L and MARY-R whose word lines are not selected are brought into a floating state, so that their precharge levels are coupled or The following level compensation circuit is provided in order to prevent the level from fluctuating due to the leak current. That is, the complementary data lines D and D of the left-hand memory array MARY-L shown as representatives are connected to the voltage dividing resistors via the switch gate MOSFETs Q1 to Q4 controlled by the timing signal φL '. R
1 to supply a divided voltage of Vcc / 2 formed by R2. The memory array MARY-R on the right side is also provided with a similar level compensation circuit (not shown). The memory arrays MSRY-L, MRY
An address decoder for selecting an ARY-R memory cell, an address buffer for receiving an address signal from an external terminal, supplying an internal address signal to the address decoder, and a control signal from an external terminal are necessary for the operation of the internal circuit. A timing control circuit that forms various timing signals is configured by a circuit similar to a known circuit.
Although not particularly limited, the address signal is supplied from a common external terminal by an address multi-system which is supplied in time series in synchronization with the address strobe signals / RAS and / CAS. In addition, static type circuits are employed for the column-based address buffer and the address decoder. An example of the operation of the circuit of this embodiment will be described below with reference to the timing chart shown in FIG. When the row address strobe signal / RAS and the column address strobe signal / CAS are at the high level and the chip is not selected, the precharge signal / φp is set to the high level. Further, the timing signal φL
And φR are both set to the high level, so that the sense amplifier SA is selectively divided into the memory arrays MA.
The transmission gate MOSFETs Q5 to Q8 and Q9 to Q12 connected to the complementary data lines of RY-L and MARY-R are both turned on. Selected memory array MAR
When YL or MARY-R is deselected, the operation timing signal φpa of the sense amplifier SA is at a low level and the timing signal φpa is at a high level, so that both the switch MOSFETs Q14 and Q15 are turned off. . As a result, the sense amplifier SA has its input / output node in a high impedance state. Then, the precharge MOSFETs Q16 and Q17 are turned on by the precharge signal .phi.p which is set to the high level. As a result, the high level and the low level of the complementary data lines D and / D in the selected memory array are short-circuited by the read / write operation, so that the precharge level is formed. Further, the complementary data lines of the non-selected memory array remain at the precharge level. If the chip is not selected for a relatively long time, the precharge level of the complementary data line is reduced by a leak current. To prevent this, Vc formed by the voltage dividing resistors R3 and R4 is used.
The divided voltage of c / 2 is supplied to the complementary data lines D and D via operating voltage supply lines (common source lines) for the MOSFETs Q13 and Q18 and the amplification MOSFETs constituting the sense amplifier SA. For example, in a read operation, a row address buffer fetches an address signal X1 supplied from an external terminal in synchronization with a fall of a row address strobe signal RAS and transmits it to an address decoder. For example, when a memory cell of the memory array MARY-R on the right side is selected according to the address specified by the address signal X1, the timing signal φL is set to low level. As a result, the transmission gate MOSFETs Q5 to Q8 connecting the sense amplifier SA and the complementary data lines of the left memory array MARY-L are turned off. Note that the timing signal φR is kept at a high level as shown by a dotted line in FIG. One word line W on the right side specified by the address signal X1 is set to a high level. As a result, of the complementary data lines D and / D, the MOSFET Qm for address selection of one of the memory cells is turned on, and the charge of the storage capacitor Cs is read out to the data line. Thereafter, when the signal φpa goes high and the timing signal bar φpa goes low, the power switch MOSFETs Q14 and Q15 are turned on, so that the sense amplifier SA amplifies the level difference between the right complementary data lines. . Next, when the column address strobe signal / CAS is set to the low level, the column address buffer and the address decoder are activated, and the address signal Y1 supplied from the external terminal is taken in. One of the amplified outputs is read from an external terminal Dout through a common input / output line (I / O), a main amplifier, and an output buffer (not shown), and read out as data D1
And send it out. In this embodiment, since the column circuit is constituted by a static circuit,
When the address signal is changed to Y2 to Y4, the circuit responds to this by switching the connection between the sense amplifier SA and the common input / output line (I / O), and sequentially outputting the output signals D2 to D4. Is sent. With such a static column mode, for example, in a dynamic RAM having a storage capacity of about 1 Mbit, data of up to 1024 bits can be continuously read. In such a static column mode, if the complementary data line of the left memory array MARY-L is left floating for a relatively long time, the half precharge level is reduced due to coupling or leakage current. Will fluctuate. In the circuit of this embodiment, when the timing signal φL is set to the low level by the row-related address instruction, the timing signal φL ′ is set to the high level. As a result, the switch gate MOSFETs Q1 to Q4 are turned on, and the voltage of Vcc / 2 formed by the voltage dividing resistors R1 and R2 is supplied to each data line. Note that the similar timing signal φR ′ in the selected memory array MARY-R is kept at the low level as shown by the dotted line,
It has no effect on the read operation of the memory cell. (1) Among the memory arrays divided in the data line direction,
Even if one memory array is accessed continuously like static column mode or page mode,
By continuously supplying the half precharge level to the complementary data line of the other non-selected memory array by the level compensation circuit, the half precharge level as the read reference voltage of the memory cell can be kept constant. The effect that the stabilization of can be realized is obtained. (2) According to the above (1), even if the power supply voltage fluctuates during operation, a precharge level as a reference voltage can be obtained in accordance with the fluctuation, so that stable operation is performed even with power supply voltage fluctuation. The effect that it can be obtained is obtained. Although the invention made by the present inventor has been described based on the embodiments, the invention is not limited to the above-described embodiments, and may be variously modified without departing from the gist thereof. Needless to say. For example,
The column circuit may be constituted by a dynamic circuit. In this case, the similar continuous access (page mode) can be performed by setting the column address strobe signal CAS once to the high level and then setting the column address strobe signal to the low level to sequentially take in the column address signals. The row address signal and the column address signal may be supplied from independent external terminals. In this case, selection / non-selection is controlled by a chip selection signal instead of the address strobe signal. Further, an internal synchronous system that detects a change in the address signal and forms a series of timing signals required for the internal circuit based on the change may be employed. According to the present invention, there is provided a dynamic type wherein a unit memory array is divided and a common sense amplifier is selectively connected to complementary data lines of both memory arrays, and a read reference voltage of a memory cell is formed by half precharge. It can be widely used for RAM.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic configuration diagram showing one embodiment of a memory array in a dynamic RAM according to the present invention. FIG. 2 is a timing chart for explaining an example of the operation. [Description of Signs] MARY-L, MARY-R: memory array, SA: sense amplifier.

──────────────────────────────────────────────────続 き Continued on front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G11C 11/407

Claims (1)

(57) [Claims] First and second memory cells each provided at an intersection of a complementary data line and a word line, each including a plurality of memory cells each including an address selection MOSFET and an information storage capacitor.
A memory array; a sense amplifier comprising two CMOS inverters provided for transmission lines MOSFETs for complementary data lines of the first and second memory arrays, respectively, and cross-coupled; and one of the two CMOS inverters A first potential supply line commonly connected to the sources of the two CMOS inverters and supplied with the first potential via the first switch; and a first potential supply line commonly connected to the other source of the two CMOS inverters and the second potential A second potential supply line to which two potentials are supplied; a level compensation circuit for supplying a precharge potential that is an intermediate potential between the first and second potentials to the first and second potential supply lines; Short-circuits are provided for the complementary data lines of the first and second memory arrays via transmission gate MOSFETs, respectively, for short-circuiting the complementary data lines. And when the first and second memory arrays are not selected, the first and second switches are turned off, and the complementary data line and the first and second potential supply lines are precharged. A dynamic RAM which is precharged to a potential. 2. The short circuit includes a source circuit between the complementary data lines.
2. The dynamic RAM according to claim 1, wherein the drain path is a MOS transistor connected. 3. The level compensating circuit may include a first transistor having a source / drain path connected between the first and second potential supply lines.
2. The semiconductor device according to claim 1, further comprising: an OS transistor; and a second MOS transistor having a source / drain path connected between a precharge potential and one of the first and second potential supply lines. Item 3. The dynamic RAM according to item 2 or 2.