JPH0766663B2 - Dynamic RAM - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a dynamic RAM (random access memory), and is used for a dynamic RAM having a static main amplifier controlled by a clock signal, for example. And effective technology.

[Background technology]

The applicant of the present application has considered using a clock-controlled differential amplifier circuit as a main amplifier for amplifying a signal of a common data line to which a data line of a memory array selected by a column switch circuit is coupled. This differential amplifier circuit has a drain of an N-channel type differential amplifier MOSFET and a P-channel type load MOSF in a current mirror form.
A MOSF that has an ET and supplies an operating current to the common source of the differential amplification MOSFET by a column timing signal.
An ET will be provided. In such a main amplifier, the operating current flows only when the timing signal is supplied, so that the power consumption can be reduced. However, since the operation is started after the timing signal is supplied, the operation becomes slower than that of a completely static main amplifier without clock control. Further, when a power supply pump is generated in which the current voltage is lowered from a high state, the potential of the common source of the differential MOSFET increased by the high current voltage is confined when the power source voltage is lowered. As a result, when the main amplifier is activated by the timing signal, it takes time to reduce the potential of the common source, and the operation is delayed accordingly. In particular, when a so-called pulse read operation is performed, in which a latch circuit is provided on the output side of the main amplifier so that the operation of the main amplifier is performed for a fixed and relatively short period of time, the power supply pump causes a substantial As a result of shortening the amplification operation period of the main amplifier, the amplification operation becomes unstable.

As an example of the patent application which describes the dynamic RAM in detail, there is JP-A-57-82282.

[Object of the Invention]

An object of the present invention is to provide a dynamic RAM including a main amplifier which operates at high speed and consumes less power.

The above and other objects and novel features of the present invention are as follows.
It will be apparent from the description of this specification and the accompanying drawings.

[Outline of Invention]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows. That is, a relatively small current is caused to flow by the timing signal formed based on the row address strobe signal to put the main amplifier in a half-operation state, and the timing signal formed based on the column address strobe signal is applied. The main amplifier is activated by passing a relatively large current.

〔Example〕

FIG. 1 shows a block diagram of a dynamic RAM according to the present invention. The circuit elements constituting each circuit block in the same figure are formed on a semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique, although not particularly limited thereto.

In this embodiment, although not particularly limited, the memory array is divided into two right and left like M-ARY1 and M-ARY2. In each of the memory arrays M-ARY1 and M-ARY2, the column system (data line) signal line is composed of a pair of complementary data lines arranged in parallel, and two pairs of complementary data lines form one set. In the figure, it is configured by a two-intersection system (folded bit line or digit line system) arranged so as to run in the lateral direction. The row-system address selection lines (word lines, dummy word lines) are used for the memory arrays M-AR.
Y1 and M-ARY2 are configured to run vertically, and are arranged to run vertically in FIG.

The column switches C-SW1 and C-SW2 receive a selection signal formed by a column address decoder C-DCR described later, and correspond to the above two sets of complementary data lines in the memory array M-ARY1 and the memory array M-ARY2. Connect to two sets of common complementary data lines (or input / output line I / O) CD0, CD1 and CD2, CD3, respectively. Above common complementary data lines CD0, CD1 and C
D2 and CD3 are arranged so as to run vertically to the left and right of the column decoder C-DCR.

The sense amplifiers SA1 and SA2 are selectively operated by the timing signal φpa during the write / read operation, and the minute read voltage from the memory cell coupled to one of the data lines is dummyed by the word line selection operation. One of the complementary data lines is amplified to the high level and the other is amplified to the low level by referring to the reference voltage from the dummy cell coupled to the other data line by the selection operation of the word line. Although not particularly limited, the unit circuit forming the sense amplifier is composed of a CMOS latch circuit.

Row address buffer R-ADB row address strobe signal ▲ ▼ receives the row address signal AX which is supplied in synchronization with, to form an internal complementary address signal a 0 to a m. Note that, for example, a non-inverted address signal a0, expressed as the complementary address signal a 0 in conjunction with this opposite phase inverted address signal 0. The same applies to the following description and drawings. Among the complementary address signal a 0 to a m, a specific bit, for example, complementary address signal a 0 to a m-1 excluding the most significant bit a m is the next row address decoder R-DCR1, R-DCR2 Sent out.

Row address decoder R-DCR1, R-DCR2 forms a selection signal of the complementary address signal a 0 to a m-1 respectively decodes one word line and the dummy word line. The row address decoders R-DCR1 and R-DCR2 are connected to the memory array M-AR in synchronization with the word line selection dimming signal φx.
The selection operation of one word line of Y1 and M-ARY2 and the dummy word line is performed.

The column address buffer C-ADB receives the address signal AY supplied in synchronization with the column address strobe signal CAS.
Receiving, form the internal complementary address signal a 0 to a n.
Of the complementary address signal a 0 to a n, a particular bit, e.g., complementary address signal excluding the most significant bit a n
a 0~ a n-1 are supplied to the column address decoder C-DCR. Column address decoder C-DCR decodes the complementary address signal a 0~ a n-1, 1 one column selection supplied to the column switch circuits C-SW1, C-SW2 in synchronization with the data line selection timing signal φy Form a signal.

Although not particularly limited, the address signal of the above most significant bit
a m and a n is supplied as an initial value in the address counter COUNT. In the figure, the address signal from the external terminal is shown to be transmitted to the address counter COUNT, but in reality, the address buffer R-ADB, C-ADB.
The internal signal at is transmitted. Address counter COUN
T consists of 2-bit binary counter forming the address signal a m 'and a n' is supplied to the decoder DEC which forms a selection signal of the main amplifier MA0 to MA3. This counter COUNT is a column address strobe signal ▲
The internal timing signal φ formed on the basis of ▼ is received, the counting operation is performed, and the four main amplifiers MA0 to M0
An address signal indicating A3 is formed.

The common complementary data lines CD0 to CD3 are coupled to the input terminals of the main amplifiers MA0 to MA3, respectively. These main amplifiers MA0 to MA3 include output selection circuits as described later. The decoder DEC receives the 'a n a' complementary address signal a m of the most significant bit, to form a series of selection signals when one of the one of the main amplifier MA0~MA3 of four. The output selection circuits of the main amplifiers MA0 to MA3 are arranged so that the selection signal formed by the decoder DEC in the read mode and the column address lobe signal ▲
The column address strobe signal ▲ ▼ is controlled by ▼ and, and is transmitted to the common data output circuit included in the input / output circuit I / O in time series in synchronization with the column address strobe signal ▲ ▼. This enables a read operation in the nibble mode in which a 4-bit signal is serially output.

The input / output circuit I / O includes a data output circuit for reading and a data input circuit for writing.
In the read operation in which the write enable signal ▲ ▼ is set to the high level, the data output circuit is activated at a predetermined timing, the output signals from the main amplifiers MA0 to MA3 are amplified and sent from the external terminal D. In the write operation in which the write enable signal ▲ ▼ is set to the low level, the data input circuit is activated at a predetermined timing, and the common complementary data is passed through a signal selection circuit (not shown in FIG. 1) as described later. Transmit write data to lines CD0-CD3.

Timing generation circuit TG has three external control signals ▲
Upon receiving ▼ (row address strobe signal), ▲ ▼ (column address strobe signal) and ▲ ▼ (write enable signal), the above various timing signals necessary for the memory operation are formed and transmitted.

FIG. 2 shows a circuit diagram of an embodiment of the data input and output system. Each circuit element in the figure is a well-known CMOS.
(Complementary MOS) It is formed on a semiconductor substrate such as single crystal silicon by a manufacturing technique of an integrated circuit. In the figure, the MOSFET in which a straight line is added between the source and drain is a P-channel type.

Although not particularly limited, the integrated circuit is formed on a semiconductor substrate made of single crystal P-type silicon. N-channel MOSFET
Is a gate electrode made of polysilicon formed through a thin gate insulating film on the surface of the semiconductor substrate between the source region and the drain region and between the source region and the drain region. Composed of. The P-channel MOSFET is formed in the N-type well region formed on the surface of the semiconductor substrate. As a result, the semiconductor substrate has a plurality of N channel MOs formed thereon.
Configure a common substrate gate for SFETs. The N-type well region constitutes the substrate gate of the P-channel MOSFET formed thereon. The substrate gate of the P-channel MOSFET, that is, the N-type well region, is coupled to the power supply terminal Vcc. Although not particularly limited, the built-in substrate back bias voltage generation circuit (not shown) responds to a positive power supply voltage such as + 5V applied between the power supply terminal Vcc that constitutes the external terminal of the integrated circuit and the reference potential terminal or the ground terminal. Then, a negative back bias voltage to be supplied to the semiconductor substrate is generated.
This applies a back bias voltage to the substrate gate of the N-channel MOSFET. As a result, the junction capacitance (parasitic capacitance) between the source and drain of the N-channel MOSFET and the semiconductor substrate is reduced, so that the operation speed is increased.

Common complementary data line CD0, ▲ ▼ 0 shown as a representative
Is coupled to the input terminal of the next Mayamp MA0. The main amplifier MA0 is composed of the following pair of first stage differential amplifier circuit, second stage differential amplifier circuit 2nd, latch circuit FF, and output selection circuit.

One of the pair of first-stage differential amplifier circuits is composed of N-channel differential amplifier MOSFETs Q7 and Q8 and P-channel load MOSFETs Q5 and Q6 provided between their drains and the power supply voltage Vcc. The load MOSFETs Q5 and Q6 form an active load circuit by forming a power supply mirror form. The other of the first-stage differential amplifier circuit has the same N-channel differential amplifier MOSFETs Q11, Q12 and P-channel load MOSFE as the above.
A common source of the differential amplification MOSFETs Q11 and Q12 is configured by TQ9 and Q10, and is shared with the common source of the one differential amplification MOSFETs Q7 and Q8.

The gate of the N-channel MOSFET Q7 as the inverting input terminal in the one differential amplifier circuit and the N-channel MOSFET Q1 as the non-recoil input terminal in the other differential amplifier circuit.
The gate of 1 is coupled to the common complementary data line {circle around (0)}. The gate of the N-channel MOSFET Q8 as the non-inverting input terminal in the one differential amplifier circuit and the gate of the N-channel MOSFET Q12 as the inverting input terminal in the other differential amplifier circuit are the common complementary data line CD0.
Be combined with.

Between the common source of the differential amplification MOSFETs Q7, Q8 and Q11, Q12 and the ground potential of the circuit in order to operate the first stage differential amplification circuit composed of the above two sets of differential amplification circuits in accordance with the timing signal. Is an N-channel MOSF that is activated by a column timing signal φma generated based on the column address strobe signal ▲ ▼.
ETQ13 is provided. That is, the dimming signal φma
Is generated at substantially the same timing as the data line selection timing signal φy. This MOSFET Q13 has its conductance set relatively large,
A relatively large current required for the amplification operation is passed. In this embodiment, in order to speed up the operation and stabilize the operation, a current switch circuit for bringing the differential amplifier circuit into a half operation state by using a row timing signal R is provided. The current switch circuit has an N-channel MOSFET Q1 whose conductance is reduced so that a relatively small current for causing the differential amplifier circuit to be in a half operation state is flown.
4 and an N-channel type switch MOSFET Q15 which receives a row timing signal R are connected in series. The power supply voltage Vcc is constantly applied to the gate of the MOSFET Q14.
Is supplied to cause the current having a relatively small value to flow. Although not particularly limited, the timing signal R is a row address strobe signal ▲
When ▼ is low level, in other words, it is set to high level when the chip is in the selected state, and the MOSFET Q15 is turned on.

As a result, the MOSFET Q15 is turned on in the row-system timing signal, in other words, in the row-system selection operation performed prior to the column-system selection operation. Depending on the current of the current value, the differential amplification MOSFET Q7, Q8 and Q11, Q
Current flows to 12. As a result, the differential amplifier circuit is brought into a half-operation state. In other words, the differential amplification MOSFET Q
The source potentials of 7, Q8 and Q11, Q12 are lowered to a relatively low potential by the above current. This allows the differential amplifier MOSFETs Q7, Q8 and Q11, Q12 to operate even if a power pump occurs.
It is possible to prevent that the source potential of is kept at a high level. Then, the column selection operation is performed, the read signal from the selected data line is transmitted to the common data lines ▲ ▼ 0, CD0, etc., and when the MOSFET Q13 is turned on by the column-related timing signal φma, each The differential amplification MOSFETs Q7, Q8 and Q11, Q12 perform high-speed amplification operation by flowing a current in response to the read signal supplied to their gates.

The pair of output signals of the pair of first-stage differential amplifier circuits is not particularly limited, but the second step formed by a circuit similar to the first-stage differential amplifier circuit, such as a circuit surrounded by a dotted line in FIG. It is supplied to a pair of input terminals of the dynamic amplification circuit 2nd. Since each circuit element in the second stage differential amplifier circuit is the same as that in the first stage amplifier circuit, the circuit symbol and its description are omitted.

The pair of output signals of the second stage differential amplifier circuit 2nd is transmitted to the input of the common data output circuit DOB through the next output selection circuit. One output selection circuit for receiving one output signal of the differential amplifier circuit path 2nd is a P-channel MOSFET Q17.
Is supplied to the input of the CMOS inverter circuit constituted by the N-channel MOSFET Q18. This CMOS inverter circuit is put into operation by the power supply voltage Vcc and the ground potential of the circuit being supplied by the P-channel MOSFET Q16 and the N-channel MOSFET Q19. Therefore, the above MOSF
When ETQ16 and Q19 are turned off, the output of the CMOS inverter circuit is set to a high impedance state. The other output selection circuit that receives the other output signal of the differential amplifier circuit 2nd is a P-channel MOSFET Q21, N-channel MOSFET Q22 and a P-channel MOSFET Q20, N-channel MOSFET Q23 that supplies an operating voltage, which constitutes a CMOS inverter circuit similar to the above.
When the MOSFETs Q20 and Q23 are turned off, the output of the CMOS inverter circuit is brought to a high impedance state.

The output selection circuit configured as described above is the next selection circuit (decoder).
Form an operation timing signal. The NAND gate circuit G4 constitutes a unit circuit of the decoder DEC. That is, the address signal address signals m'and n'formed by the address counter COUNT are supplied to the inputs of the NAND gate circuit G4. For example, when the address signals m'and n'are both high level, a low level selection signal is formed. This selection signal is supplied to one input of a NOR gate circuit G7 forming an operation timing signal of the output selection circuit. This NOR gate circuit G7
The other input of the column address strobe signal ▲
The output {circle around (5)} of the NAND gate circuit G5 that receives the internal control signal C1 formed in synchronization with {circle around (1)} and the row-related timing signal RG2 formed based on the operation timing signal φpa of the sense amplifier is supplied. Above NOR gate circuit
The output of G7 is inverted by the CMOS inverter circuit IV3 and supplied to the gates of P-channel MOSFETs Q16 and Q20 of the output selection circuit. The output of the NOR gate circuit G7 is supplied to the gates of the N-channel MOSFETs Q19 and Q23 of the output selection circuit. A signal DS obtained by inverting the output ▲ ▼ of the NAND gate circuit G5 by a CMOS inverter circuit (not shown) is
It is supplied to the gates of P-channel MOSFETs Q24 and Q25 provided at the input terminal of the data output circuit DOB.

The data output circuit DOB is provided with a latch circuit FF composed of NAND gate circuits G8 and G9. This latch circuit FF
As a result, the output signals from the main amplifier MA0 and the like can be held, so that a so-called pulse read operation can be performed in which the main amplifier NA0 and the like are operated for a relatively short period. As a result, the main amplifier MA0 or the like, after transmitting its output signal to the latch circuit FF, sets its timing signal φma (and R) to a low level to bring it into a semi-operational state or a non-operational state, resulting in low power consumption. . Furthermore, although not particularly limited, the output of the output selection circuit is also in a high impedance state. Between the pair of input terminals of the latch circuit FF and the power supply voltage Vcc, a P-channel MOSF controlled by the signal DS is provided.
ETQ24 and Q25 are provided. When the output selection circuit is set to high impedance, that is, after the output signal of the main amplifier is sent to the output buffer DOB, one input of the NAND gate circuits G8 and G9 of the latch circuit FF is kept at high level by the MOSFETs Q24 and Q25. Be drunk

The output signals of the latch circuit FF are NAND gate circuit G10, CMOS inverter circuit IV5 and NAND gate circuit, respectively.
Push-pull type N-channel output MOSFET Q26 and N-channel output MOS via G11 and CMOS inverter circuit IV6
It is transmitted to the gate of FETQ27. The NAND gate circuit G1
The operation timing signal DOE formed based on the column system signal is supplied to the other inputs of 0 and G11. When this signal DOE is at a high level (logic “1”), the NAND gate circuits G10 and G11 open the gates accordingly, and the input signal is output via the CMOS inverter circuits IV5 and IV6 and the output MOSFETs Q26 and Q27 to the external terminal Dout. To send to. If the timing signal DOE is low level like the ground potential of the circuit,
The outputs of the NAND gate circuits G10 and G11 both become high level, and the outputs of the inverter circuits IV5 and IV6 both become low level. As a result, both output MOSFETs Q26 and Q27 are turned off, and their outputs are put in a high impedance state. The external output terminal Dout is used as an external input terminal Din to which an input terminal of a data input circuit DIB, which will be described later, is combined so that the common external terminal Dout shown in FIG.
May be

The external input terminal Din is connected to the input terminal of the data input circuit DIE. This data input circuit DIB has an external input terminal Din
To form a write signal having the same phase as the write data signal supplied to the write signal and the opposite write signal. The complementary write data signals are N-channel transmission gate MOSFETs Q1 and Q2.
Is supplied to the common complementary data line ▲ ▼ 0, CD0 via the. Common complementary data line ▲ ▼ 0, CD0 and power supply voltage V
N-channel load MOSFETs Q3 and Q4 having a relatively small conductance are provided between them and cc.

Transmission gate M for transmitting the output signal of the data input circuit DIB
The output selection signal of the selection circuit including the following NOR gate circuit G1 and NAND gate circuit G2 is supplied to the gates of the OSFETs Q1 and Q2. The same address signals m'and n'as described above and the write control signal WYP based on the write enable signal () are supplied to the inputs of the NAND gate circuit G2. The output of the NAND gate circuit G2 is supplied to one input of the NOR gate circuit G1. This NOR gate circuit
An inverted internal column address strobe signal ▲ ▼ is supplied to the other input of G1. As a result, since the control signal WYP is set to the high level in the write operation mode, when the address signals m'and n'instructing the common complementary data lines ▲ ▼ 0, CD0 are both at the high level, the NAND gate circuit G2 Output is set to low level. Therefore, the column address strobe signal ▲
Internal column system timing signal that changes in phase with ▼
When ▼ is set to low level, the output of NOR gate circuit G1 becomes high level and transmission gate MOSFETs Q1 and Q2 are turned on, and the write signal supplied from external input terminal Din is sent to common complementary data lines ▲ ▼ 0 and CD0. Tell. In addition,
The output of the data input circuit DIB is similar to the transmission gate MOS.
It is selectively transmitted to other common complementary data lines CD1 to CD3 via the FET. In the read operation, the control signal
Since WYP is set to low level, the output of the NAND gate circuit G2 is set to high level. As a result, the output of the NOR gate circuit G1 is set to low level.
The MOSFETs Q1 and Q2 are turned off. The output of the NOR gate circuit G1 is inverted by the CMOS inverter circuit IV1 and transmitted to the gates of the N-channel MOSFETs Q3 and Q4. Therefore, these MOSFETs Q3 and Q4 are turned on at the time other than the above write operation, and the common complementary data line
▼ 0, CD0 is given a substantially constant bias level. Since the signal amplitudes of the common complementary data lines ▲ ▼ 0 and CD0 are substantially limited during the read operation, etc., due to the ON state of the MOSFETs Q3 and Q4, it is necessary to respond to the read signal from the memory cell at high speed. You can

[Effect]

(1) A relatively large current value that causes the main amplifier to be in a half-operation state with a current having a small current value using a row system timing signal and to substantially perform an amplification operation with a column system timing signal. By performing the amplification operation with the determined operating current, it is possible to obtain an effect that an amplified output signal that responds to the input signal at high speed can be obtained.

(2) An undesired high level due to power supply bumps may be trapped in the main amplifier by keeping the main amplifier in a half-operation state with a current having a small current value by using a row timing signal. It can be prevented. As a result, it is possible to obtain an effect that a stable high-speed amplification operation can be performed even for a power pump.

(3) By increasing the speed of the amplification operation, the operation period of the pulse read can be shortened, so that the effect of reducing power consumption can be obtained.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above-mentioned embodiments and can be variously modified without departing from the scope of the invention. Nor. For example, the static column mode or the page mode other than the nibble mode may be used. At this time, the signal φma may be a pulse signal generated from the address signal change detection circuit (ATD) or based on a column system signal. The memory array is divided into the above two memory arrays and 4
An input / output circuit that divides and realizes the write / read operation as described above may be provided for each mat. Also, one may amplifier may be used to access memory in 1-bit units, or multiple may amplifiers and input / output circuits may be provided to perform parallel memory access in multiple-bit units. It is effective for the memory ICs that have.

In addition, the first and second address strobe signals corresponding to the first and second address signal groups are formed based on the first and second address strobe signals.
The first and second signals may cause the main amplifier to be in one of two states, a half operating state and an operating state. Instead of the row-related signal R, a signal formed by the chip selection signal CE may be used. Further, the specific circuit of each circuit can take various embodiments.

[Field of application]

INDUSTRIAL APPLICABILITY The present invention can be widely used for a dynamic RAM in which an address strobe signal is multiplexed from a common external terminal to supply an address signal.

[Brief description of drawings]

FIG. 1 is an internal configuration block diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing an embodiment of a main amplifier, a data output circuit and a data input circuit. M-ARY1, M-ARY2 ... Memory array, SA1, SA2 ... Sense amplifier, R-ADB ... Row address buffer, C-SW
1, C-SW2 ... Column switch, C-ADB ... Column address buffer, R-DCR1, R-DCR2 ... Row decoder, C
-DCR ... Column decoder, DEC ... Decoder, COUNT ...
... Address counter, MA0 to MA3 ... Main amplifier, TG ...
... Timing generator, I / O ... Input / output circuit, DOB ... Data output circuit, DIB ... Data input circuit

Claims (2)

[Claims] 1. A memory array in which dynamic memory cells are arranged in a matrix at intersections of a plurality of word lines and data lines, and a row address signal and a column address for selecting addresses of the word lines and data lines of the memory array. An address buffer whose signal is input from the same address terminal in time series in synchronization with the row address strobe signal and the column address strobe signal, respectively, and selectively coupled through the data line of the memory array and the column switch circuit. Common data line and a signal of the common data line are supplied to the input terminal, and are brought into a half-operation state by a current having a relatively small current value in accordance with a first timing signal formed based on the row address stove signal. , A second formed based on the column address strobe signal It is in the operating state by a current of relatively large current value in accordance with the timing signal, dynamic RAM, which comprises a main amplifier for the input terminal and the output terminal is composed of a differential amplifier circuit which is separated. 2. The main amplifier is made to be in a semi-operating state or a non-operating state by at least a first or second timing signal after holding the amplified signal in a latch circuit. A dynamic RAM according to claim 1.