JP2514329B2 - Semiconductor integrated circuit device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, for example, a semiconductor integrated circuit device such as a dynamic RAM having an ATD (address signal change detection) circuit. And effective technology.

[Conventional technology]

One of the operation modes in the dynamic RAM is a so-called static column mode in which the word line is selected and the storage information of the memory cells coupled to the word line is serially output by switching the column address. There is. In such a static column mode, it is necessary to generate a timing signal for a data line switching operation each time a column address changes. Therefore, a change detection circuit for address signals is provided. As such an address signal change detection circuit, for example, one in which an address signal and its delay signal are supplied to an exclusive OR circuit to form one shot address signal change detection signal for each change of the address signal is known. Is. A semiconductor memory incorporating such an address signal change detection circuit is disclosed in, for example, Japanese Patent Laid-Open No. 59-45685.
No., published in Japanese Unexamined Patent Publication No.

[Problems to be solved by the invention]

In the address signal change detection circuit as described above,
Since an exclusive OR circuit including a delay circuit and a plurality of gate circuits is required, there is a problem that the number of circuit elements increases.

An object of the present invention is to provide a semiconductor integrated circuit device provided with a signal change detection circuit having a simple circuit configuration.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for solving problems]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows. That is,
For each of a plurality of bits of the internal complementary address signal, first and second MOSFETs in series are arranged between the output terminal and the first power supply voltage having a relatively low level, and the corresponding internal complementary address signal is provided. Is coupled to the gate of the first MOSFET, and the output of inverting delay means for receiving the corresponding internal complementary address signal and outputting its inverting delay signal is coupled to the gate of the second MOSFET. Further, a load means is provided between the signal wiring to which the respective output terminals are commonly connected and the second power supply voltage having a relatively high level,
What is claimed is: 1. A semiconductor integrated circuit device comprising an address change detection circuit for outputting an address change detection signal from an output node at a predetermined position of the signal wiring, the semiconductor integrated circuit device comprising a semiconductor substrate, the level of the output node in an address change detection direction. Positive feedback means for detecting a change and amplifying the output node by positive feedback is provided, and the positive feedback means is provided with an inverter circuit having an input terminal coupled in the vicinity of the output node and having a relatively high logical threshold voltage. Third and fourth MOSFETs in series are arranged between the input terminal of the inverter circuit and the first power supply voltage, and the output signal of the inverter circuit is supplied to the gate of the third MOSFET, And the fourth MO above
The output of the inverting delay means for receiving the output signal of the inverter circuit and outputting its inverting delay signal is coupled to the gate of the SFET.

[Action]

According to the above-mentioned means, when the internal complementary address signal is changed, the first and second series-connected MOSFETs corresponding to the changed internal complementary address signal are turned on for a certain period of time, and in response thereto. Then, the address transition detection signal output from the output node tends to change from a relatively high level to a relatively low level. At this time, the inverter circuit having a relatively high logic threshold voltage included in the positive feedback means immediately detects the above change of the output node, and the third and fourth series connection modes included in the positive feedback means. of
The MOSFET is forced to be in the ON state, and the node is amplified by positive feedback in the address change detection direction near the output node.

〔Example〕

FIG. 2 shows a dynamic RA to which the present invention is applied.
A block diagram of one embodiment of M is shown. Each circuit element in the figure is formed on one semiconductor substrate such as single crystal silicon by a known CMOS (complementary MOS) integrated circuit manufacturing technique. In the following description, the MOSFET (insulated gate field effect transistor) is an N-channel MOSFET unless otherwise specified. Also, in the figure, an arrow is added to the channel (back gate) part.
The MOSFET is a P-channel type, and N without an arrow is added.
Distinct from channel MOSFETs.

Although not particularly limited, the integrated circuit is formed on a semiconductor substrate made of single crystal P-type silicon. N channel MO
The SFET is composed of a source region, a drain region, and polysilicon formed on the surface of the semiconductor substrate between the source region and the drain region through a thin gate insulating film between the source region and the drain region. Composed of various gate electrodes. The P-channel MOSFET is formed in the N-type well region formed on the surface of the semiconductor substrate. Thereby, the semiconductor substrate constitutes a common substrate gate of the plurality of N-channel MOSFETs formed thereon. The N-type well region constitutes the substrate gate of the P-channel MOSFET formed thereon. The substrate gate of the P-channel MOSFET, that is, the N-type well region, is coupled to the power supply voltage Vcc. The substrate gate of the N-channel MOSFET or semiconductor substrate is coupled to a negative substrate bias potential generated inside the chip or the ground potential of the circuit.

In the dynamic RAM of this embodiment, the X address signal and the Y address signal are supplied via the same external terminal by the multiplex method. In addition to having an automatic refresh function, it has a function of performing continuous read or write operation by changing an address signal within one memory access period. Therefore, in the automatic refresh operation mode, the refresh address counter for specifying the word line to be refreshed
REFC, a multiplexer MPX for switching and selecting a row address signal formed by this refresh address counter REFC and a row address signal externally supplied, and for detecting a level change of an externally supplied address signal The ATD circuit of is provided.

The memory array M-ARY has a two-intersection system, and n sets of complementary data lines D0, ▲ ▼ ~ arranged horizontally in FIG.
Dn∇, m word lines arranged in the vertical direction, and m × n memory cells coupled to the intersections of these complementary data lines and word lines. As represented by complementary data lines D0 and ▲ ▼, m memory cells each including an address selection MOSFET Qm and an information storage capacitor Cs are coupled to each data line with a predetermined regularity. It

A precharge circuit PC including switch MOSFETs typified by MOSFETs Q7 and Q8 is provided between the complementary data lines D0, ▲ ▼ to Dn, ▲ ▼. Gates of these switch MOSFETs are commonly connected, and a timing control circuit TC described later supplies a timing signal φpc which is set to a high level when the dynamic RAM is in a non-operating state and is set to a low level in the operating state. As a result, the timing type φpc is a high level dynamic type
In the non-operation state of the RAM, the switch MOSFETs Q7 to Q8 are turned on, and both signal lines of the complementary data lines are short-circuited to have the same intermediate level. Therefore, the read operation is speeded up.

The sense amplifier SA is a P channel shown as a representative.
Consists of MOSFETs Q3, Q4 and N-channel MOSFETs Q5, Q6
It is composed of a CMOS latch circuit, and its pair of input / output nodes is coupled to the complementary data line D0. Although not particularly limited, the latch circuit is supplied with the power supply voltage Vcc through parallel P-channel MOSFETs Q1 and Q2 and the ground voltage of the circuit through parallel N-channel MOSFETs Q13 and Q14. These power switch MOSFETs Q1 and Q2 and MOSFETs Q13 and Q14 are commonly used for latch circuits provided in other similar rows in the same memory mat. In other words, the sources of the P-channel MOSFET and the N-channel MOSFET in the latch circuits in the same memory mat are commonly connected.

The gates of the MOSFETs Q1 and Q13 have complementary timing signals ▲ ▼ and φ for activating the sense amplifier SA.
pa1 is applied, and complementary timing signals ▲ ▼ and φpa2 formed slightly later than the timing signals ▲ ▼ and φpa1 are applied to the gates of the MOSFETs Q2 and Q14. Thus, the operation of the sense amplifier SA is performed in two stages. That is, the timing signals ▲ ▼, φpa
In the first stage in which 1 is formed, the minute read voltage given between the pair of data lines from the memory cell undergoes an undesired level fluctuation due to the current limiting action of the MOSFETs Q1 and Q13 having a relatively small conductance. Amplified without. After the potential difference between the complementary data lines is increased by the amplifying operation of the sense amplifier SA, when the second stage in which the timing signals ▲ ▼ and φpa2 are formed, the MOSFETs Q2 and Q14 having a relatively large conductance are obtained.
Is turned on. The amplification operation of the sense amplifier SA is MO
It is speeded up by turning on SFETQ2 and Q14. As described above, by performing the amplification operation of the sense amplifier SA in two stages, high-speed data reading can be performed while preventing an undesired level change of the complementary data line.

The complementary data line is coupled to a switch MOSFET forming a column switch CSW on the opposite side of the sense amplifier SA. The column switch CSW is a representative M
N sets of switch MOSF like OSFET Q9, Q10 and Q11, Q12
It is composed of ET and selectively couples the designated complementary data line and the common complementary data line CD. The gates of these switch MOSFETs Q9, Q10 to Q11, Q12 have data line selection signals Y0 to
Yn is supplied.

On the other hand, the gates of the address selecting MOSFETs Qm of the memory cells arranged in the same column of the memory array M-ARY are coupled to the corresponding word lines W0 to Wn. These word lines are selected and designated by the row address decoder.

Row address buffer RADB is an address signal input terminal
Row address strobe signal via A0-Ai
X address signal AX0 supplied in synchronization with the falling edge of
~ AXi received, internal address signals a0 to ai in phase with these external address signals and internal address signals in opposite phase ▲ ▼
~ ▲ ▼ complementary internal address signals consisting of (hereinafter, these together representing a a 0 to a i) to form a. These internal complementary address signals are supplied as one input signal to the multiplexer MPX.

A refresh address signal is supplied from the refresh address counter REFC to the multiplexer MPX as the other input signal in order to specify a word line to be refreshed in the automatic refresh operation mode. Further, the timing signal φref, which is set to the high level in the automatic refresh operation mode, is supplied to the multiplexer MPX as the switching signal.
Supplied from C. The multiplexer MPX operates in the normal read or write operation mode in which the timing signal φref is at low level, and thus the row address buffer RA
The internal complementary address signals a 0 to a i supplied from DB are selected and transmitted to the row address decoder as internal address signals a x0 to a xi. Further, in the automatic refresh operation mode in which the timing signal φref is at the high level,
The refresh address signal supplied from the refresh address counter REFC is selected and similarly transmitted to the row address decoder.

Although not particularly limited, the row address decoder has a two-stage structure and is composed of a combination of a predecoder RDCR1 and a secondary decoder RDCR2. Predecoder RDCR1
Are complementary internal address signals a x0 and a x1 of the lower 2 bits.
Are decoded to form four types of word line selection timing signals φx00 to φx11 (not shown) synchronized with the word line selection timing signal φx. These word line selection timing signals are combined with the common selection signal formed by the secondary decoder DCR2 that decodes the internal X address signals a x2 to a xi excluding the lower 2 bits, to form the X address signals AX0 to AXi. It is used as a word line selection signal (W0 to Wm) for selecting one designated word line. As described above, the row address decoder has the two-stage structure of the predecoder RDCR1 and the secondary decoder RDCR2, so that the pitch of the row decoder RDCR2 and the pitch of the word lines can be matched, and the space on the semiconductor substrate can be adjusted. Can be effectively utilized.

The column address buffer YADB receives the column address strobe signal CAS via the address signal input terminals A0 to Ai.
Y address signal AY0 supplied in synchronization with the falling edge of
~ AYj, internal address signals ay0 to ayj in phase with these external address signals and address signals ay0 to ayj in antiphase
(Hereinafter, these are collectively expressed as a y0 to a yj) to form complementary internal address signals a y0 to a yj. The complementary internal address signals a y0 to a yj are the column address decoder CD.
Address signal change detection circuit AT
Supplied to D.

The column address decoder CDCR has a complementary internal address signal a y0 supplied from the column address buffer CADB.
Decodes ~ a yi, to form the data line selection signal Y0~Yn synchronized with the data line selection timing signal φy supplied from the timing control circuit TC, and supplies to the column switch CSW.

A precharge MOSFET Q15 similar to the precharge circuit PC is provided between the common complementary data lines CD and ▲ ▼. Further, a pair of input / output nodes of a main amplifier MA having a circuit configuration similar to that of the sense amplifier SA and a output terminal of a data input buffer DIB are connected to the common complementary data line CD. . The output terminal of the main amplifier MA is coupled to the input terminal of the data output buffer DOB.

If the dynamic RAM is in read mode,
The data output buffer DOB is activated by the timing signal φr, amplifies the output signal of the main amplifier MA and sends it out from the data input / output terminal DO. When the dynamic RAM is in the non-operating state or the write operating mode, the output of the data output buffer DOB is in the high impedance state.

When the dynamic RAM is in the write operation mode, the data input buffer DIB is activated by the timing signal φw to form a complementary write signal according to the write data supplied from the input terminal Di, and the common complementary data line Supplied to CD / ▲ ▼. When the dynamic RAM is in the non-operating state or the read operating mode, the output of the data input buffer DIB is in the high impedance state.

The address signal change detection circuit ATD receives the complementary internal address signals a y0 to a yj and detects the signal change. When at least one of these address signals causes a level inversion from a low level to a high level or from a high level to a low level, the address signal change detection signal ▲ ▼ is set to the low level and is transmitted to the timing control circuit TC.

The refresh address counter REFC operates in the automatic refresh operation mode of the dynamic RAM,
Timing signal φ supplied from timing control circuit TC
c is counted and a refresh address signal for designating a word line to be refreshed is formed and supplied to the multiplexer MPX.

The timing control circuit TC has a row address strobe signal ▲ ▼, a column address strobe signal ▲ ▼ and a write enable signal ▲ that are supplied from the outside.
▼ and the address signal change detection signal ▲ ▼ formed by the address signal change detection circuit ATD,
The above various timing signals are formed and supplied to each circuit.

FIG. 1 shows a circuit diagram of an embodiment of the address signal change detection circuit ATD. In this embodiment, in order to reduce the number of circuit elements, a unit circuit is composed of two MOSFETs provided corresponding to each address signal and its inversion signal and one inversion delay circuit. That is, the unit circuits UATD0 to UA of the address signal change detection circuit ATD.
TDj is a series type N-channel MOSFET QA4, QA5 and QA6 provided between the output node no and the ground potential of the circuit, as represented by the unit circuit UATD0 provided for the complementary internal address signals ay0 and ▲ ▼. , QA7 and inverting delay circuits DN2 and DN3. The drains of the MOSFETs QA4 and QA6 are commonly connected and coupled to the output node no as the output terminal ▲ ▼ of the unit circuit UATD0.
The gate of MOSFET QA4 and the input terminal of inverting delay circuit DN2 are supplied with the non-inverting internal address signal ay0, and MOSFET QA5
The output signal of the inverting delay circuit DN2 is
Is supplied. Similarly, the gate of the MOSFET QA6 and the input terminal of the inverting delay circuit DN3 are connected to the inverting internal address signal ▲
▼ is supplied, and the output signal of the inverting delay circuit DN3 is supplied to the gate of the MOSFET QA7. MOSFET QA5 and QA
The source of 7 is coupled to the ground potential of the circuit. In the figure, the output terminals of the other unit circuits UATDj-1, UADTj and the like having the same configuration as described above are commonly connected to this output node no. Between the output node no and the power supply voltage Vcc, a P-channel type load MOSFET QA whose gate is coupled to the ground potential of the circuit
1 is provided.

FIG. 3 shows a timing chart for explaining the operation of the unit circuit UATD0. The operation of this unit circuit will be described by taking the case of the non-inverted internal address signal ay0 as an example.

Since the non-inverted internal address signal ay0 is inverted and delayed by the inversion delay circuit DN2, the potentials of the gates of the two MOSFETs QA4 and QA5 are complementary to each other when the address signal is not inverted. Therefore, the MOSFETs QA4 and QA5 are not turned on at the same time, and the potential of the output node no becomes high level like the power supply voltage Vcc unless the other unit circuits are in the signal change detection state. When the non-inverted internal address signal ay0 is inverted from high level to low level, the output signal of the inversion delay circuit is delayed after this inversion.
▼ becomes high level, but before that, the gate of MOSFET QA4 is made low level.
The potential of is not extracted to the ground potential.

On the other hand, as shown in FIG. 3, a non-inverted internal address signal
When ay0 is inverted from the low level (that is, the address signal AY0 is a logical “0”) to the high level (that is, the address signal AY0 is a logical “1”), the MOSFET QA4 is turned on. Also, the output signal of the inverting delay circuit ▲
Since ▼ changes from the high level to the low level with a delay of that delay time, the MOSFETs QA4 and QA5 are simultaneously turned on for the delay time of the inverting delay circuit. As a result, the potential of the output node no is pulled out to the ground potential for the delay time,
From high level to low level.

Similarly, QA that receives the inverted internal address signal ▲ ▼
6 and MOSFET QA7 that receives the output signal of the inverting delay circuit DN3
Is turned on simultaneously only when the inverted internal address signal ▲ ▼ is inverted from low level (that is, the address signal AY0 is logic “1”) to high level (that is, the address signal AY0 is logic “0”), and the output node The no potential is set to low level.

As described above, since the output terminals of each unit circuit are all commonly connected to the output node no, when at least one address signal is inverted, the potential of the output node no is pulled down to the ground potential and becomes low level.

By the way, the pads connected to the external terminals of the dynamic RAM shown in FIG. 1 are arranged side by side on two opposing sides of the semiconductor chip. Therefore, 18
The semiconductor chips mounted in the pin package will be arranged in groups of nine. Dynamic type RA above
When M has a storage capacity of about 1 Mbit, 10 address pads are needed. As a result, of the 10 address pads, for example, the most significant bit address signal
The pad corresponding to ay9 (ayj) is arranged with a relatively large distance from other address signals. Address buffer and address signal change detection circuit
ATD unit circuits will also be provided separately on both sides of the semiconductor substrate. FIG. 1 shows complementary internal address signals a y0 to a
It shows a case where the unit circuits UATD0 to UATDj-1 corresponding to yj-1 are arranged on one side of the semiconductor substrate, and the unit circuit UATDj corresponding to the complementary internal address signal a yj is arranged on the opposite side of the semiconductor substrate.

In this embodiment, the address signal change detection circuit ATD in which the unit circuits are separately provided on both sides of the semiconductor substrate in this way.
In order to improve the operation margin of the
Appended to no. That is, the potential of the output node no is an inverter circuit whose logic threshold voltage is relatively high.
An inversion detection circuit similar to the unit circuit of the address signal change detection circuit ATD input to N1 and receiving its output signal and its inversion signal is provided. That is, the output signal of the inverter circuit N1 is input to the inverting delay circuit DN1. Between the output node no and the ground potential of the circuit, a MOSFET QA2 for receiving the output signal of the inverter circuit N1 at its gate and a MOSF for receiving the output signal of the inverting delay circuit at its gate.
ETQA3 is provided. As a result, the change in the potential of the output node no from the high level to the low level is judged by the inverter circuit N1 with a relatively high logic threshold voltage,
Positive feedback is given to the output node no. Therefore, since there is a wiring resistance Rs that cannot be ignored between the output terminal of the unit circuit UATDj arranged on the opposite side of the other unit circuits and the load MOSFET on the semiconductor substrate, the address signal ay
If only j and its inverted signal ▲ ▼ change,
The time constant circuit composed of the wiring resistance Rs and the parasitic capacitance in the wiring may prevent the potential of the output node no from reaching a sufficiently low level. Even in such a case, it is determined by the relatively high logic threshold voltage of the inverter circuit N1. When the output potential of the inverter circuit N1 changes from the low level to the high level, the MOSFET QA2 is turned on and the MOSFE is delayed by the delay time of the inverting delay circuit DN1.
TQA3 also turns on at the same time. This allows the output node
The no potential is pulled out to a lower low level to improve the operation margin of the address signal change detection circuit ATD.

As shown in the above embodiment, the following effects can be obtained by applying the present invention to a semiconductor integrated circuit device such as a dynamic RAM having an ATD circuit. (1) Serial MO that receives the input signal and its inverted delayed signal
A simple circuit composed of SFETs has an effect that both MOSFETs can be turned on during the delay time to form a signal change detection signal when the input signal is changed from low level to high level, for example. .

(2) The circuit of (1) above is provided for each of a plurality of complementary input signals, and a simple configuration in which a common load means is connected allows any one of a plurality of bit signals to be provided. When changing from the high level to the low level or from the low level to the high level, it is possible to obtain the effect that the detection signal synchronized with the change can be obtained.

(3) The common output node is provided with an inverter circuit having a relatively high threshold voltage for receiving the potential and a unit circuit for positively feeding back a change in the output signal of the inverter circuit to the common output node. Therefore, the potential change of the common output node is determined by the inverter circuit having a relatively high threshold voltage, and by positive feedback, the detection signal of the unit circuit arranged at a distant position on the semiconductor substrate is also detected. Since the signal is reliably transmitted, it is possible to obtain an effect that a signal change detection circuit having a large operation margin can be realized.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above-mentioned embodiments and can be variously modified without departing from the scope of the invention. Nor. For example, in Figure 1
The MOSFET QA1 may be composed of an N-channel MOSFET, and the load MOSFET corresponding to the MOSFET QA1 is one in which a unit circuit is divided into several groups and a plurality of them are provided for each group. Good. In this case, the output signals of the plurality of output nodes must be converted into one address signal change detection signal by an OR circuit. The level reproduction circuit including the inverter circuit N1 and the unit circuit shown in FIG. 1 may be provided only in the unit circuit arranged at a distant position on the semiconductor substrate. Further, the two MOSFETs forming the unit circuit may be P-channel MOSFETs, so that a signal change opposite to that of this embodiment, that is, a signal inversion from a high level to a low level may be detected. Further, various embodiments can be adopted as the specific circuit configuration of other peripheral circuits constituting the dynamic RAM, the combination of control signals, and the like.

In the above description, the case where the invention made by the inventors of the present application is mainly applied to the ATD circuit of the dynamic RAM which is the field of application which is the background has been described, but the present invention is not limited thereto, and for example, various types of It can also be applied to ATD circuits in semiconductor memory devices. The present invention can be applied to a semiconductor integrated circuit device having at least a signal change detection circuit for detecting a signal change.

[Effects of the Invention] The effects obtained by the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, in response to the pair of series MOSFETs corresponding to the changed internal complementary address signal being turned on for a certain period, the address change detection signal output from the output node is changed from a relatively high level to a relatively low level. When it is going to change to a level, an inverter circuit included in the positive feedback means and having a relatively high logic threshold voltage,
Immediately detecting the change in the output node, forcing the third and fourth MOSFETs connected in series included in the positive feedback means to the ON state, and moving the node in the vicinity of the output node in the address change detection direction. Since the positive feedback amplification is performed, even when the first and second series-connected MOSFETs arranged on the semiconductor substrate at positions apart from the output node are turned on, the change at the output node is accelerated. Can
As a result, an address change detection circuit with a large operation margin can be realized.

[Brief description of drawings]

FIG. 1 shows a dynamic RAM A to which the present invention is applied.
FIG. 2 is a circuit diagram showing an embodiment of a TD circuit, FIG. 2 is a block diagram showing an embodiment of a dynamic RAM including the ATD circuit of FIG. 1, and FIG. 3 is a unit circuit of the ATD circuit of FIG. 5 is a timing chart for explaining the operation of FIG. ATD …… Address signal change detection circuit, UATD0 to UATDj ……
Unit circuit, QA1 …… P-channel MOSFET, QA2 to QA11 ……
N-channel MOSFET, N1 ... Inverter circuit, DN1 to DN5
…… Inversion delay circuit, Rs …… Wiring resistance. M-ARY …… Memory array, PC …… Precharge circuit, SA
…… Sense amplifier, USA …… Sense amplifier unit circuit, CSW
...... Column switch, RDCR1, RDCR2 ...... Row address decoder, CDCR ...... Column address decoder, RADB ...... Row address buffer, CADB ...... Column address buffer, MPX ...... Multiplexer, MA ...... Main amplifier, DOB
...... Data output buffer, DIB ...... Data input buffer, REFC ...... Refresh counter, TC ...... Timing control circuit. Q1-Q4 ... P-channel MOSFET, Q5-Q15 ... N-channel MOSFET.

Claims (2)

(57) [Claims] 1. A plurality of internal complementary address signals of each bit,
The first and second MOSFETs in series are arranged between the output terminal and the first power supply voltage having a relatively low level, and
The corresponding internal complementary address signal is supplied to the gate of the first MOSFET, and the gate of the second MOSFET receives the corresponding internal complementary address signal and outputs its inverted delay signal. The outputs of the means are combined,
Further, a load means is provided between the signal wiring to which the respective output terminals are commonly connected and the second power supply voltage having a relatively high level, and an address change detection signal is output from an output node at a predetermined position of the signal wiring. A positive feedback means for detecting the level change of the output node in the address change detection direction and amplifying the output node in a positive feedback manner. The positive feedback means provides an inverter circuit having an input terminal coupled to the output node in the vicinity of the output node and having a relatively high logic threshold voltage, and between the input terminal of the inverter circuit and the first power supply voltage. A third and a fourth MOSFET in series with each other, an output signal of the inverter circuit is supplied to the gate of the third MOSFET, and the fourth MO is provided.
A semiconductor integrated circuit device characterized in that an output of an inverting delay means for receiving an output signal of the inverter circuit and outputting an inverting delay signal thereof is coupled to a gate of the SFET. 2. The address signal of a plurality of bits is an internal complementary address signal for accessing a memory, and a signal obtained from an output node of the address transition detection circuit is input to the internal timing for memory access. The semiconductor integrated circuit device according to claim 1, which is a semiconductor memory device having a timing control circuit for forming a signal.