JPH06243685A - Semiconductor device - Google Patents

Abstract

PURPOSE:To suppress a power supply noise of a dynamic RAM and the like provided with plural output buffers by suppressing variation of an operating current caused by that an output buffer having comparatively simple circuit constitution is made a operating state. CONSTITUTION:Control MOSFETs consisting of depletion type NFET N7 and P5, for example, are respectively added to a driving path for making one pair of output MOSFET N4 and N5 of an unit output buffer UOB0 an ON state selectively, a gate of the MOSFET is connected to a data input/output terminal D0. Gate potential of the control MOSFET TN7 and P5 is varied in accordance with potential variation of an output signal at D0, conductance of the TN7 and P5 is made small at the beginning of an ON state of the TN4 and the N5, and conductance of theses FET are sufficiently made large.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, for example, a dynamic RAM (random access memory) having a multi-bit structure and a technique particularly effective when used for a data output buffer thereof.

[0002]

2. Description of the Related Art There is a multi-bit dynamic RAM that simultaneously inputs or outputs a plurality of bits of stored data. These dynamic RAMs have a plurality of data output terminals or data input / output terminals provided corresponding to respective bits of read data output simultaneously and a plurality of data output terminals or data input / output terminals provided corresponding to these data output terminals. And a data output buffer including a unit output buffer.

A dynamic RAM having a multi-bit structure having a data output buffer is disclosed in, for example, Japanese Patent Laid-Open No.
It is described in Japanese Patent No. 214669.

[0004]

In a conventional dynamic RAM having a multi-bit structure, a unit output buffer which constitutes a data output buffer is, for example, as shown in FIG. 8, a power supply voltage VCC and a data input / output terminal. D0
An N-channel type output MOSFET (metal oxide semiconductor type field effect transistor; generically referred to as an insulated gate type field effect transistor in this specification) N4 provided between, a data input / output terminal D0 and a circuit. N-channel type output M provided between the ground potentials of
And OSFET N5. Of these, the output MOSFET
An inverted signal of the output signal of the NAND gate NA1 is supplied to the gate of N4 via an inverter composed of a P-channel MOSFET P1 and an N-channel MOSFET N1, and the gate of the output MOSFET N5 is supplied via an inverter composed of a P-channel MOSFET P2 and an N-channel MOSFET N2. An inverted signal of the output signal of the NAND gate NA2 is supplied. The non-inverted output signal MO0T of the main amplifier MA0 is input to one input terminal of the NAND gate NA1 (here, a so-called non-inverted signal which is set to a high level when it is enabled has a T at the end thereof). The same applies hereinafter) is supplied to one input terminal of the NAND gate NA2 to the main amplifier MA.
An inverted output signal MO0B of 0 (here, a so-called inverted signal or the like which is brought to a low level when it is enabled is represented by adding B to the end of the name. The same applies hereinafter). The other input terminals of the NAND gates NA1 and NA2 have internal control signals DO for output control.
C is commonly supplied.

As a result, in the output MOSFET N4, the internal control signal DOC is set to the high level and the non-inverted output signal MO0T of the main amplifier MA0 is set to the high level, that is, the storage data read from the selected memory cell is logical "1". Is selectively turned on, and the data input / output terminal D0 is set to a predetermined high level which is lower than the power supply voltage VCC by the threshold voltage. Also, output MOSF
The ETN5 is selectively operated when the internal control signal DOC is at a high level and the non-inverted output signal MO0B of the main amplifier MA0 is at a high level, that is, when the storage data read from the selected memory cell is a logic "0". The data input / output terminal D0 is set to a low level almost like the ground potential of the circuit. When the internal control signal DOC is at low level, both output MOSFETs N4 and N5 are turned off, and the data input / output terminal D0 is set to a so-called high impedance state.

However, it has been made clear by the inventors of the present application that the following problems will occur in the above-mentioned conventional dynamic RAM as the number of bits and speed of the dynamic RAM increase. That is, in the above dynamic RAM, the output MOSFETs N4 and N constituting each unit output buffer of the data output buffer
5 is designed to have a sufficiently large conductance so that a relatively large load capacitance coupled to the data input / output terminal D0 can be driven at high speed, and MOSFETs P1 and P5 are provided.
2 and N1 and N2 are so-called enhancement type MOSFETs. Therefore, the output MOSFE
Gate potential d0T of TN4 and output MOSFET N
As shown by the dotted line in FIG. 4, the gate potential d0B of No. 5 rapidly changes to the high level in response to changes in the output signals of the corresponding NAND gates NA1 and NA2, and in response to this, the output MOSFETs N4 and N5 are rapidly turned on. Becomes As a result, the potential of the output signal at the data input / output terminal D0 changes at high speed due to the large driving capability of the output MOSFET N4 or N5, which causes a relatively large change in the operating current of the dynamic RAM or the like.
This change in the operating current induces a relatively large power supply noise in the power supply voltage VCC and the ground potential of the circuit, and causes the output characteristics of the dynamic RAM or the like to deteriorate.

To cope with this, in the conventional dynamic RAM or the like, the power supply wiring for the data output buffer is dedicated to increase the line width or the output MOS.
These output MOSFETs by replacing the FETs N4 and N5 with a plurality of output MOSFETs that are respectively coupled in parallel
However, in any case, the wiring design and timing design of the dynamic RAM are complicated and the cost reduction is restricted. .

An object of the present invention is to realize a semiconductor device such as a dynamic RAM which has a relatively simple circuit structure and can suppress a change in operating current due to the operation of an output buffer. Another object of the present invention is to suppress power supply noise caused by operating a plurality of output buffers without interfering with cost reduction of a dynamic RAM having a multi-bit configuration and having a plurality of output buffers, It is to improve the output characteristics of a dynamic RAM or the like.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0010]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows. That is, in a dynamic RAM having a multi-bit configuration and including a plurality of output buffers, for example, a depletion type N channel and a P channel are provided in a drive path for selectively turning on a pair of output MOSFETs of each output buffer. Control MOSFETs made up of MOSFETs are respectively added, and their gates are commonly connected to, for example, the output terminal of the circuit.

[0011]

According to the above means, the gate potential of the control MOSFET is changed according to the change in the output signal at the output terminal of the circuit, and the conductance of the control MOSFET is made relatively small at the beginning when the output MOSFET is turned on. After the change in the potential of the output signal is suppressed and after the change in the potential of the output signal reaches a certain level, the conductance of the control MOSFET can be increased to set the high level and the low level of the output signal to the prescribed levels. As a result, the potential change of the output signal can be made gradual, and the change of the operating current due to the operation of the output buffer can be suppressed. As a result, with a relatively simple circuit configuration, it is possible to suppress the power supply noise of the dynamic RAM or the like that accompanies the operation of a plurality of output buffers at the same time, and improve the output characteristics.

[0012]

1 is a block diagram of an embodiment of a dynamic RAM to which the present invention is applied. 2 shows a block diagram of an embodiment of the data output buffer DOB included in the dynamic RAM of FIG. Based on these figures, first, an outline of the configuration and operation of the dynamic RAM of this embodiment and the data output buffer thereof will be described. The circuit elements forming each block in FIGS. 1 and 2 are known CMOs.
It is formed on one semiconductor substrate such as single crystal silicon by an S (complementary MOS) integrated circuit manufacturing technique.

In FIG. 1, the dynamic RAM of this embodiment has a memory array MARY, which occupies most of the surface of a semiconductor substrate, as its basic constituent element. The memory array MARY includes a plurality of word lines arranged in parallel in the vertical direction in the figure, and a plurality of sets of complementary bit lines arranged in parallel in the horizontal direction. At the intersections of these word lines and complementary bit lines, a large number of dynamic memory cells each composed of an information storage capacitor and an address selection MOSFET are arranged in a grid pattern.

A plurality of word lines forming the memory array MARY are coupled to the X address decoder XD and are alternatively set to the selected state. X address decoder XD has X
The address buffer XB supplies the i + 1-bit internal address signals X0 to Xi, and the timing generation circuit TG supplies the internal control signal XDG. Further, the X address buffer XB is supplied with the i + 1-bit X address signals AX0 to AXi in a time division manner through the address input terminals A0 to Ai, and the timing control circuit TG supplies the internal control signal XL.

The X address buffer XB is supplied with X address signal AX via address input terminals A0 to Ai.
0 to AXi are fetched and held according to the internal control signal XL, and internal address signals X0 to Xi are formed based on these X address signals, and the X address decoder X
Supply to D. The X address decoder XD receives the high level of the internal control signal XDG and is selectively brought into an operating state, decodes the internal address signals X0 to Xi supplied from the X address buffer XB, and outputs the memory array MAR.
The word line corresponding to Y is selectively set to the high level selected state.

Next, the plurality of sets of complementary bit lines forming the memory array MARY are coupled to the corresponding unit circuits of the sense amplifier SA. The internal control signal PA is supplied to the sense amplifier SA from the timing generation circuit TG.

The sense amplifier SA is a memory array MAR.
It includes a plurality of unit circuits provided corresponding to the respective complementary bit lines of Y, and each of these unit circuits includes a pair of CMs.
It includes a unit amplifier circuit in which OS inverters are cross-coupled and a pair of switch MOSFETs. Of these, each unit amplifier circuit is selectively supplied with a power supply voltage and a ground potential of the circuit via a drive MOSFET that is selectively turned on according to an internal control signal PA. Also, switch M
The gates of the OSFETs are sequentially connected in common by 8 pairs, and the corresponding bit line selection signal is supplied from the Y address decoder YD.

As a result, the unit amplifier circuits forming each unit circuit of the sense amplifier SA are selectively and simultaneously operated according to the internal control signal PA, and the memory array M is operated.
A minute read signal output from a plurality of memory cells coupled to the selected word line of ARY via the corresponding complementary bit line is amplified to be a high level or low level binary read signal. On the other hand, the switch MOSFETs constituting each unit circuit of the sense amplifier SA are selectively turned on by 8 pairs when the corresponding bit line selection signal is set to the high level, and the corresponding 8 pairs of the memory array MARY are turned on. Complementary bit line and complementary common data line CD0 * to
CD7 * (Here, for example, the non-inverting common data line CD0T
, And the inverted common data line CD0B are collectively indicated by asterisk like a complementary common data line CD0 *. The same shall apply hereinafter) and are selectively connected.

The Y address decoder YD has an i + 1 bit internal address signal Y0 from the Y address buffer YB.
~ Yi are supplied, and the internal control signal YDG is supplied from the timing generation circuit TG. The Y address buffer YB is supplied with the Y address signals AY0 to AYi in a time division manner via the address input terminals A0 to Ai, and the timing control circuit TG supplies the internal control signal YL.

The Y address buffer YB is supplied with Y address signal AY via address input terminals A0 to Ai.
0 to AYi are fetched and held according to the internal control signal YL, and internal address signals Y0 to Yi are formed based on these Y address signals, and the Y address decoder Y
Supply to D. The Y address decoder YD is selectively activated by receiving the high level of the internal control signal YDG, decodes the internal address signals Y0 to Yi supplied from the Y address buffer YB, and outputs the corresponding bit line selection signal. Alternately set to high level. As described above, these bit line selection signals are respectively supplied to the corresponding eight pairs of switch MOSFETs of the sense amplifier SA and used for the complementary bit line selection operation.

Complementary common data line C to which eight designated complementary bit lines of the memory array MARY are alternatively connected.
D0 * to CD7 * are coupled to the output terminals of the corresponding unit circuits of the write amplifier WA, and the main amplifier M
A is coupled to the input terminal of the corresponding unit circuit. The input terminal of each unit circuit of the write amplifier WA is coupled to the output terminal of the corresponding unit circuit of the data input buffer DIB,
Complementary output signal MO0 * of each unit circuit of main amplifier MA
2 to MO7 * are corresponding unit output buffers UOB0 to UO of the data output buffer DOB, as shown in FIG.
It is coupled to the input terminal of B7. Data input buffer DI
The input terminal of each unit circuit of B is a data output buffer DO
After being coupled to the output terminals of the corresponding unit output buffers UOB0 to UOB7 of B, the corresponding data input / output terminal D0
˜D7. The write amplifier WA is supplied with the internal control signal WP from the timing generation circuit TG, and the data output buffer DOB is supplied with the internal control signal DOC. As shown in FIG. 2, the internal control signal DOC is commonly supplied to the eight unit output buffers UOB0 to UOB7 forming the data output buffer DOB.

Each unit circuit of the data input buffer DIB outputs the write data supplied via the data input / output terminals D0 to D7 to the corresponding unit of the write amplifier WA when the dynamic RAM is selected in the write mode. Signal to the circuit. In the write mode, each unit circuit of the write amplifier WA is selectively activated by receiving the high level of the internal control signal WP, and based on the write data transmitted from the corresponding unit circuit of the data input buffer DIB. A predetermined complementary write signal is formed at the same time and is simultaneously written to the selected eight memory cells of the memory array MARY via the complementary common data lines CD0 * to CD7 *.

On the other hand, each unit circuit of the main amplifier MA is
When the dynamic RAM is selected in the read mode, the read signal output from the selected eight memory cells of the memory array MARY via the complementary common data lines CD0 * to CD7 * is further amplified, The complementary output signals MO0 * to MO7 * are selectively set to logic "0" or logic "1" (here, for example, the non-inverted output signal MO0T of the complementary output signal MO0 * is set to low level and the inverted output signal MO0B is set to high level. The state to be performed is referred to as logic "0", and the opposite state is referred to as logic "1". Unit output buffer U of data output buffer DOB
OB0 to UOB7 are selectively and simultaneously activated in response to the high level of the internal control signal DOC, and the complementary output signals MO0 * to MO7 * output from the corresponding unit circuits of the main amplifier MA are associated with corresponding data. Input / output terminal D0
~ Send to the outside via D7. Data output buffer D
The specific configuration and operation of the OB will be described in detail later.

The timing generation circuit TG selectively forms the various internal control signals on the basis of the row address strobe signal RASB, the column address strobe signal CASB, and the write enable signal WEB which are externally supplied as start control signals. And dynamic RA
Supply to each circuit of M.

FIG. 3 shows the data output buffer DO of FIG.
A circuit diagram of a first embodiment of the unit output buffer UOB0 included in B is shown, and FIG. 4 shows a signal waveform diagram of the one embodiment. Further, FIG. 5 shows a circuit diagram of a second embodiment of the unit output buffer UOB0 included in the data output buffer DOB of FIG. 2, and FIGS. 6 and 7 show its third and fourth implementations. Example schematics are shown respectively. Based on these drawings, the specific configurations and operations of the unit output buffers UOB0 to UOB7 that form the data output buffer DOB and their characteristics will be described. In the following circuit diagrams, a MOSFET having an arrow on its channel (back gate) portion is a P-channel type (second conductivity type) and is shown separately from an N-channel MOSFET without an arrow. Also, the MOSFET whose dotted line is shown in the channel portion is a depletion type, and is an enhancement type M without the dotted line.
It is shown separately from the OSFET. Further, although the following description will proceed with the unit output buffer UOB0 as an example, the other unit output buffers UOB1 to UOB7 have basically the same configuration as the unit output buffer UOB0, and therefore, it should be analogized.

In FIG. 3, the unit output buffer UOB0
Is an N-channel (first conductivity type) output MOSFET N4 (first MOSFET) provided between the power supply voltage VCC (first power supply voltage) and the data input / output terminal D0 (output terminal of the circuit), and data input. N-channel type output MOSF provided between the output terminal D0 and the ground potential of the circuit
And ETN5 (second MOSFET). this house,
The gate of the output MOSFET N4 has a series configuration P
Channel MOSFET P1 and N channel MOSF
Power supply voltage VC via ETN7 (third MOSFET)
It is coupled to C and further to the ground potential (second power supply voltage) of the circuit through the N-channel MOSFET N1. Similarly, the gate of the output MOSFET N5 has two P-channel MOSFETs P2 and P2 arranged in series.
5 (fourth MOSFET) to the power supply voltage VCC, and further to the ground potential of the circuit through the N-channel MOSFET N2. As will be described later, MOS
FETs N7 and P5 form a drive path for the output MOSFET N4, and MOSFET P5 is the output MOSFET.
It becomes a control MOSFET for N4. Similarly, MOS
FETs P2 and P5 form a drive path for the output MOSFET N5, and MOSFET P5 is the output MOSFET.
It becomes a control MOSFET for N5. Control MOSFE
The gates of TN7 and P5 are commonly coupled to the data input / output terminal D0.

In this embodiment, the power supply voltage VCC is
Although not particularly limited, a positive power supply voltage such as + 3V is used. The control MOSFETs N7 and P5 are depletion type N-channel or P-channel MOSFETs.
Even if the gate-source voltage is zero, it is in a weekly ON state.

The unit output buffer UOB0 further includes a pair of NAND gates NA1 and NA2. Of these, the non-inverted output signal MO0T of the corresponding main amplifier MA0 is supplied to one input terminal of the NAND gate NA1.
The inverted output signal MO0B is supplied to one input terminal of the NAND gate NA2. These NAND gates N
The internal control signal DOC is commonly supplied to the other input terminals of A1 and NA2. The output signal of the NAND gate NA1 is supplied to the commonly coupled gates of the MOSFETs P1 and N1, and the output signal of the NAND gate NA2 is supplied to the commonly coupled gates of the MOSFETs P2 and N2.

From these facts, the output signal of the NAND gate NA1 is the non-inverted output signal MO0 of the corresponding main amplifier MA0 when the internal control signal DOC is at the high level.
When T is high level, that is, when the complementary output signal MO0 * of the main amplifier MA0 is logic "1", it is selectively set to low level, and the output signal of the NAND gate NA2 is the high level of the internal control signal DOC and the corresponding main signal. The inverted output signal MO0B of the amplifier MA0 is at high level, that is, the complementary output signal MO0 * of the main amplifier MA0 is logic "0".
Is set to a low level selectively.

When the output signal of the NAND gate NA1 is at a low level, the unit output buffer UOB0 has a MOS
The FET P1 is turned on and the MOSFET N1 is turned off. At this time, as described above, the control MOSFET N7 is turned on with a weekly or relatively small conductance as the gate-source voltage becomes zero, that is, the potential of the output signal at the data input / output terminal D0 becomes closer to the ground potential of the circuit, that is, the low level. To be done. Therefore, the gate potential d of the output MOSFET N4
0T is the control MOSFET as shown by the solid line in FIG.
It gradually rises according to the conductance of TN7, and accordingly, the conductance of the output MOSFET N4 is gradually increased. As a result, the potential of the output signal at the data input / output terminal D0 rises relatively gently, and the potential change of the output signal, that is, the change of the operating current due to the operation of the unit output buffer UOB0 is suppressed. Then, when the potential of the output signal at the data input / output terminal D0 becomes high to some extent, the conductance of the control MOSFET N7 becomes sufficiently large and the output MOSFET N4.
The gate potential of D becomes high enough, and data input / output terminal D
The potential of the output signal at 0 reaches the specified high level.

When the output signal of the NAND gate NA1 is at low level, the output signal of the NAND gate NA2 is at high level. Therefore, MOSFETP2
Is turned off and the MOSFET N2 is turned on. As a result, the gate of the output MOSFET N5 is MO.
The ground potential of the circuit is set to a low level via the SFET N2, and the MOSFET N5 is turned off.

On the other hand, when the output signal of the NAND gate NA2 is at low level, the MOSFET P2 is turned on in the unit output buffer UOB0, and the MOSFET N2 is turned on.
Is turned off. At this time, the control MOSFET P5
As described above, when the gate-source voltage is zero, that is, the potential of the output signal at the data input / output terminal D0 is closer to the power supply voltage VCC, that is, the high level, it is turned on with a weekly or relatively small conductance. Therefore, the gate potential d0B of the output MOSFET N5 is controlled by the control MOS as shown by the solid line in FIG.
It gradually rises according to the conductance of the FET P5, and accordingly, the conductance of the output MOSFET N5 is gradually increased. As a result, the potential of the output signal at the data input / output terminal D0 falls relatively gently, and the potential change of the output signal, that is, the variation of the operating current due to the operation of the unit output buffer UOB0 is suppressed. Then, when the potential of the output signal at the data input / output terminal D0 becomes low to some extent, the control MOSFET P5
The conductance of the
The gate potential of TN5 becomes sufficiently high, and the potential of the output signal at the data input / output terminal D0 reaches a prescribed low level.

When the output signal of the NAND gate NA2 is at low level, the output signal of the NAND gate NA1 is at high level. Therefore, MOSFET P1
Is turned off and the MOSFET N1 is turned on. This causes the gate of the output MOSFET N4 to be MO.
The ground potential of the circuit is set to a low level via the SFET N1, and the MOSFET N4 is turned off.

As described above, the dynamic RAM of this embodiment is made multi-bit by simultaneously inputting or outputting 8-bit storage data, and the data output buffer D thereof is provided.
Each of the unit output buffers UOB0 to UOB7 forming the OB is selectively provided according to the potentials of the output signals at the data input / output terminals D0 to D7 which are substantially provided in the drive paths of the output MOSFETs N4 and N5 and have corresponding conductances. Control MOSFET N changed
7 and P5. The control MOSFETs N7 and P5 are
The gate potentials of the corresponding output control MOSFETs N4 and N5 are gradually raised according to their conductances, and the potentials of the corresponding output signals are gently changed. As a result, with a relatively simple circuit configuration, it is possible to suppress changes in the operating current that accompany the eight unit output buffers UOB0 to UOB7 being in the operating state at the same time, and to suppress the power supply noise associated therewith, thereby enabling multi-bit operation. The output characteristics of the dynamic RAM having the configuration can be improved.

In the unit output buffer UOB0 of FIG. 3, the control MOSFET N7 is added to output the output MO.
The high level of the gate potential of SFETN4 is the control MOSF.
Although it decreases by the threshold voltage of ETN7, as shown in FIG. 5, the power supply voltage VC is applied to the source of the MOSFET P1.
Power supply voltage VC higher than C by, for example, twice the threshold voltage Vthn of the N-channel MOSFET, that is, 2Vthn.
By supplying H, this can be avoided. Further, in the unit output buffer UOB0 of FIG. 3, the gates of the control MOSFETs N7 and P5 are directly coupled to the data input / output terminal D0 and are always affected by the potential of the output signal at the data input / output terminal D0, as shown in FIG. And a dynamic type R between the data input / output terminal D0 and the commonly connected gates of the control MOSFETs N7 and P5.
This can be avoided by providing switch MOSFETs P3 and N3 which are selectively turned on according to the internal control signal CS when AM is selected.

On the other hand, the control MOSFETs N7 and P5 are
So-called low threshold voltage MOSFET having a relatively small threshold voltage in place of the depletion type MOSFET
Can be used. Further, the control MOSFETs N7 and P5 have normal threshold voltages provided that a predetermined level conversion circuit LC is provided between their gates and the data input / output terminal D0, as illustrated in FIG. It can also be replaced by the enhancement type MOSFETs N6 and P4. In this case, the potentials of the internal signals VN and VP formed by the level conversion circuit LC cause the control MOSFETs N6 and P4 to be in a weekly ON state at the beginning of the operation of the unit output buffer UOB0, and output at the data input / output terminal D0. When the signal potential rises or falls to some extent, the control MOSFE
It needs to be set to a predetermined level so that TN6 and P4 can be sufficiently turned on.

As shown in the above-described embodiments, the present invention is applied to a semiconductor device such as a dynamic RAM having a multi-bit structure having a plurality of output buffers.
The following effects can be obtained. That is, (1) In a dynamic RAM or the like having a multi-bit configuration and having a plurality of output buffers, for example, a depletion type N channel is provided in a drive path for selectively turning on a pair of output MOSFETs of each output buffer. And control MOSFET consisting of P-channel MOSFET
Respectively, and by commonly connecting the gates to the output terminal of the circuit, for example, the gate potential of the control MOSFET is changed according to the potential change of the output signal at the output terminal of the circuit, and the output MOSFET is initially turned on. , The conductance of the control MOSFET is made relatively small to suppress the potential change of the output signal, and after the potential change of the output signal reaches a certain level, the conductance of the control MOSFET is increased to define the high level and the low level of the output signal. The effect that it can be set to the level is obtained.

(2) According to the above item (1), the potential change of the output signal of each output buffer is made gradual, and the change of the operating current due to the simultaneous operation of a plurality of output buffers is suppressed. The effect of being able to do is obtained. (3) According to the above items (1) and (2), with a relatively simple circuit configuration, power supply noise due to simultaneous operation of a plurality of output buffers is suppressed, and output characteristics of a dynamic RAM or the like are suppressed. The effect of being able to improve is obtained.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in FIGS. 1 and 2, the number of data input / output terminals provided in the dynamic RAM can be set arbitrarily, and external terminals for data input and external terminals for data output can be provided separately. it can. Dynamic type R
The AM can adopt a so-called array division method in which the memory array MARY is divided into a plurality of sub-memory arrays, and a so-called address non-multi type in which an X address signal and a Y address signal are input from separate address input terminals. The plex system can also be adopted.
The block configuration of the dynamic RAM and the names and combinations of the activation control signal and the address signal are not restricted by this embodiment.

3 to 7, the output MOSFE
TN4 and N5 can be replaced by a plurality of N-channel MOSFETs that are coupled in parallel. Further, the unit output buffers UOB0 to UOB7 can include a latch circuit for holding read data, and can also include various protection elements. The output terminal of each unit output buffer may be coupled to, for example, an internal bus instead of an external terminal, and the signals transmitted by these unit output buffers do not necessarily have to be read data. Furthermore, unit output buffers UOB0-U
Various embodiments may be adopted for the specific circuit configuration of the OB 7, the polarity and absolute value of the power supply voltage, the conductivity type of the MOSFET, and the like.

In the above description, the case where the invention made by the present inventor is mainly applied to the dynamic type RAM which is the field of application which is the background of the invention has been described.
The present invention is not limited to this, and can also be applied to various memory integrated circuit devices such as static RAMs having similar output buffers and logic integrated circuit devices such as gate array integrated circuits. The present invention can be widely applied to semiconductor devices including at least an output buffer mainly composed of MOSFETs.

[0042]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, in a dynamic RAM having a multi-bit configuration and including a plurality of output buffers, for example, a depletion type N channel and a P channel are provided in a drive path for selectively turning on a pair of output MOSFETs of each output buffer. By adding control MOSFETs each including a MOSFET and commonly connecting the gates to the output terminals of the circuit, for example, a control MO according to the potential change of the output signal at the output terminal of the circuit can be obtained.
When the gate potential of the SFET is changed and the output MOSFET is turned on, the conductance of the control MOSFET is made relatively small to suppress the potential change of the output signal, and after the potential change of the output signal reaches a certain level. By increasing the conductance of the control MOSFET, the high level and the low level of the output signal can be set to the specified levels. As a result, the potential change of the output signal can be made gradual, and the change of the operating current that accompanies the operation of the output buffer can be suppressed. It is possible to suppress the power supply noise associated with the above, and improve the output characteristics of the dynamic RAM or the like.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a dynamic RAM to which the present invention is applied.

2 is a block diagram showing an embodiment of a data output buffer included in the dynamic RAM of FIG.

FIG. 3 is a circuit diagram showing a first embodiment of a unit output buffer included in the data output buffer of FIG.

FIG. 4 is a signal waveform diagram showing an embodiment of the unit output buffer of FIG.

5 is a circuit diagram showing a second embodiment of a unit output buffer included in the data output buffer of FIG.

FIG. 6 is a circuit diagram showing a third embodiment of a unit output buffer included in the data output buffer of FIG.

FIG. 7 is a circuit diagram showing a fourth embodiment of a unit output buffer included in the data output buffer of FIG.

FIG. 8 is a circuit diagram showing an example of a unit output buffer included in a conventional data output buffer.

[Explanation of symbols]

MARY ... memory array, XD ... X address decoder, XB ... X address buffer, SA ... sense amplifier, YD ... Y address decoder, YB ...
・ Y address buffer, WA ・ ・ Write amplifier, MA ・
..Main amplifier, DIB ... Data input buffer,
DOB ... Data output buffer, TG ... Timing generation circuit. UOB0 to UOB7 ... Unit output buffer. LC: Level conversion circuit. P1 to P4 ... Enhancement type P channel MOSFET, P5 ...
Depletion type P-channel MOSFET, N1 to N
6 ... Enhancement type N-channel MOSFE
T, N7 ... Depletion type N-channel MOSF
ET, NA1-NA2 ... NAND gate, V1 ...
Inverter.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Internal reference number FI Technical indication location H03K 17/687 19/0175 7436-5J H03K 17/687 F 8941-5J 19/00 101 F

Claims (6)

[Claims] 1. An output MOSFET whose drain or source is coupled to a predetermined output node, and a gate potential which is provided substantially in the drive path of the output MOSFET and whose gate potential is selectively changed according to the potential of the output node. A semiconductor device comprising a control MOSFET. 2. The output MOSFET and control MOSF
ET constitutes a tri-state type output buffer, the output node is an output terminal of the output buffer, and the output MOSFET is between a first power supply voltage and an output terminal of the output buffer. A first MOSFET of the first conductivity type provided between the first MOSFET and a second MOSFET of the first conductivity type provided between the output terminal of the output buffer and the second power supply voltage; The control MOSFET includes a third MOSFET of the first conductivity type provided substantially between the first power supply voltage and the gate of the first MOSFET, substantially the first power supply voltage and the second MOSFET. The semiconductor device according to claim 1, further comprising a fourth MOSFET of a second conductivity type provided between the gate of the MOSFET and the fourth MOSFET. 3. The semiconductor device according to claim 2, wherein the third and fourth MOSFETs are depletion type MOSFETs whose gates are coupled to the output terminal of the output buffer. 4. The third and fourth MOSFETs are enhancement type low threshold voltage MOSFETs whose gates are coupled to the output terminals of the output buffers. Semiconductor device. 5. The semiconductor device according to claim 2, wherein the third and fourth MOSFETs are enhancement type MOSFETs whose gates receive an output signal of a predetermined level conversion circuit. 6. The semiconductor device is a dynamic RAM having a multi-bit structure, and a plurality of output buffers are provided corresponding to each bit of read data of the dynamic RAM. The semiconductor device according to claim 1, claim 2, claim 3, claim 4, or claim 5.