JPH06132747A - Semiconductor device - Google Patents

Abstract

PURPOSE:To shorten access time by preventing the occurrence of noise in an output signal since large output current transitionally flows when power voltage is high and making the rise and fall of the output signal to be steep when power voltage is low in the output circuit of a semiconductor storage device. CONSTITUTION:A voltage detection circuit 1 detects whether power voltage VCC is more than setting voltage or not. An output control circuit 2 delays a first signal D1 inputted from an external part when power voltage VCC is more than setting voltage by previously decided time so as to output it and outputs the first signal D1 inputted from the external part without delaying it when power voltage VCC is lower than setting voltage. A first output circuit 3 inputs the first signal D1 outputted from the output control circuit 2 and outputs it. A second output circuit 4 directly inputs a signal D2 inputted from the external part with the first signal D1 without the output control circuit 2 and outputs it.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to an output circuit of a semiconductor memory device.

In recent years, in semiconductor memory devices, it has been required to increase the number of outputs. In order to increase the number of bits of the output, an output circuit is provided for each bit. In that case, if the output signals of the same level are simultaneously output from the output circuits, noise is likely to occur in the output signal.

That is, when the output signals of the same level are simultaneously output from the respective output circuits, a large current including the output currents of the respective output circuits transiently flows, and due to a mismatch of characteristic impedances of the output lines, etc. Noise such as ringing easily occurs in the output signal.

Further, in recent years, in order to realize higher integration of semiconductor memory devices, the line width of the power supply line is suppressed to a necessary minimum, and the power supply capacity seen from each output circuit cannot be said to be large. ing. Therefore, when the output signals of the same level are simultaneously output from the output circuits, a large current is drawn from the power supply at a time, and the fluctuation of the power supply level causes a malfunction in the semiconductor memory device.

In particular, when the semiconductor memory device is used at a high power supply voltage with the diversification of the operating voltage of the semiconductor memory device (5V system, 3V system, etc.), the noise level of the output signal also increases. Its reduction is an important issue.

On the other hand, when the semiconductor memory device is used with a low power supply voltage, the noise level of the output signal is reduced and the current drawn from the power source is also reduced, so that the access time to the semiconductor memory device is shortened more. It becomes an important issue.

That is, by shortening the time until the level of the output signal is determined to be the H level or the L level, that is, the time required for the rising and falling of the output signal, data is read (outputted) from the semiconductor memory device. ) Is required to shorten the access time.

[0008]

2. Description of the Related Art In a conventional semiconductor memory device, as shown in FIG. 7, data Dn, Dn + 1, Dm, Dm + 1 output from a data output buffer 61 are output from an output circuit 62 having the same circuit configuration. It is designed to be output to the outside via.

FIG. 8 shows a circuit diagram of the output circuit 62. The sources of the PMOS transistors forming the CMOS inverters 63 and 64 are connected to the high potential side power supply Vcc, and the sources of the NMOS transistors forming the CMOS inverters 63 and 64 are connected to the ground.

The output terminals of both the CMOS inverters 63 and 64 are commonly connected, and the data Dn, Dn + 1, Dm and Dm + 1 are output from the common output terminals, respectively. The data Dn, Dn + 1, Dm, output from the data output buffer 61 is input to the input terminal of the CMOS inverter 63.
One of Dm + 1 is input. On the other hand, the same data Dn, Dn + 1, Dm, Dm + 1 input to the CMOS inverter 63 is input to the input terminal of the CMOS inverter 64 via the four inverters 65 connected in series. .

Therefore, the CMOS inverter 64 is a CMO.
Compared to the S inverter 63, the delay time of each inverter 65 is delayed by the total value of the delay times. That is, the data Dn, which is output from the data output buffer 61,
When Dn + 1, Dm, Dm + 1 rises from the L level to the H level, the output signal of the CMOS inverter 63 immediately becomes H level.
Switch from level to L level. On the other hand, CM
The output signal of the OS inverter 64 switches from the H level to the L level with a delay of the total delay time of each inverter 65.

Similarly, when the data Dn, Dn + 1, Dm, Dm + 1 from the data output buffer 61 rises from H level to L level, the output signal of the CMOS inverter 63 promptly changes from L level to H level. Switch. On the other hand, the output signal of the CMOS inverter 64 is delayed by the total value of the delay times of the respective inverters 65 from the L level to H level.
Switch to level.

As described above, the CMOS inverter 64 has the C
Since it operates later than the MOS inverter 63, the rising and falling edges of the data Dn, Dn + 1, Dm, Dm + 1 output from the common output terminals of both the CMOS inverters 63 and 64 become gentle. .

That is, each CMOS inverter 63, 6
4 is operated in a time division manner (that is, staggered operation), the output signal of the output circuit 62 (data Dn, Dn + 1, Dm,
That is, the rising and falling edges of Dm + 1) are moderated.

Therefore, even when data Dn, Dn + 1, Dm, Dm + 1 of the same level are simultaneously output from each output circuit 62, a transiently large output current does not flow from each output circuit 62. Even if there is a mismatch in the characteristic impedance of the output lines, noise such as ringing will not occur in each data Dn, Dn + 1, Dm, Dm + 1.

Further, when the power supply line has a narrow line width and the power supply capacity seen from each output circuit 62 is small, each output circuit 6
Even if the data Dn, Dn + 1, Dm, Dm + 1 of the same level are simultaneously output from 2, the large current is not drawn from the power source at once. Therefore, the fluctuation of the power supply level (the fluctuation of the voltage VCC of the high-potential-side power supply VCC and the ground level) does not occur, and the fluctuation of the power supply level does not cause a malfunction inside the semiconductor memory device.

Here, the rising and falling edges of the data Dn, Dn + 1, Dm, Dm + 1 output from the output circuits 62 correspond to the transistor sizes of the P and NMOS transistors constituting the CMOS inverters 63, 64. It can be adjusted by changing.

That is, each M of the CMOS inverter 63
By making the transistor size of the OS transistor smaller than that of the CMOS inverter 64, the data Dn, Dn + 1, Dm, Dm + output from each output circuit 62 can be obtained.
The rising and falling edges of 1 can be made more gradual.

[0019]

By the way, in recent years, the operating voltage of semiconductor memory devices has been diversified, and the use of 3V system has been increasing in addition to the 5V system which has been generally used in the past.

In the 3V system, H of the data Dn, Dn + 1, Dm, Dm + 1 output from each output circuit 62 is higher than that in the 5V system.
The difference between the level and the L level is reduced to 3/5, and the noise level is correspondingly reduced.

Therefore, in the 3V system, shortening the access time to the semiconductor memory device becomes more important than noise of the data Dn, Dn + 1, Dm, Dm + 1 output from the output circuits 62. .

That is, the time until the data Dn, Dn + 1, Dm, Dm + 1 output from each output circuit 62 is set to the H level or the L level, that is, the data Dn output from each output circuit 62. , Dn + 1, Dm, Dm + 1, the rising and falling times must be shortened.

However, the time required for the rising and falling of the data Dn, Dn + 1, Dm, Dm + 1 output from the output circuit 62 is the voltage VCC of the high potential side power supply VCC (hereinafter,
If the power supply voltage Vcc) decreases, it becomes longer.

That is, as shown in FIG. 9, the output circuit 6
When the data Dn, Dn + 1, Dm, Dm + 1 output from 2 rises from the L level (= 0V) to the H level (= VCC),
When the power supply voltage Vcc is low ("Vcc1" shown in FIG. 9), it rises with a delay compared to when it is high ("Vcc2" shown in FIG. 9) (time t shown in FIG. 9).

This is because the threshold voltage of the CMOS inverter 63 corresponds to the power supply voltage Vcc, and when the power supply voltage Vcc is low, the threshold voltage of the CMOS inverter 63 also decreases accordingly. This is because the operation of the CMOS inverter 63 is delayed.

Similarly, the threshold voltage of the CMOS inverter 64 also corresponds to the power supply voltage Vcc, and when the power supply voltage Vcc is low, the threshold voltage of the CMOS inverter 64 is correspondingly lowered, and the CMOS inverter 64 is also reduced. Operation is delayed.

Therefore, as shown in FIG. 9, the power supply voltage Vcc
When (Vcc1) is low, the data Dn, Dn + 1, D output from each output circuit 62 is higher than when (Vcc2) is high.
The time required for rising m, Dm + 1 becomes long.

Similarly, when the power supply voltage Vcc is low, the time required for the falling of the data Dn, Dn + 1, Dm, Dm + 1 output from each output circuit 62 is longer than when it is high.

As described above, in the conventional output circuit 62, 2
By providing two CMOS inverters 63 and 64 and performing stagger operation, the rising and falling edges of the output signal of the output circuit 62 are moderated to prevent a transiently large output current from flowing.

Therefore, when the power supply voltage V CC is high (5 V
System, it is possible to effectively reduce the noise of the output signal of the output circuit 62 and the fluctuation of the power supply level. However, a transiently large output current does not flow, and the output circuit 6
Even when the power supply voltage Vcc at which the noise of the output signal of No. 2 and the fluctuation of the power supply level are not a problem (3V system), the rising and falling edges of the output signal of the output circuit 62 are made gentle. Therefore, when the power supply voltage Vcc is low, there is a problem that the access time to the semiconductor memory device becomes long.

The present invention has been made in order to solve the above problems, and its object is to prevent a noise from occurring in the output signal due to a transiently large output current flowing when the power supply voltage is high. It is an object of the present invention to provide an output circuit of a semiconductor memory device which can prevent and shorten the access time by making the rise and fall of the output signal steep when the power supply voltage is low.

[0032]

FIG. 1 is a diagram for explaining the principle of the present invention. The voltage detection circuit 1 detects whether the power supply voltage Vcc is equal to or higher than a set voltage.

The output control circuit 2 delays the first signal D1 input from the outside by a predetermined time when the power supply voltage Vcc is equal to or higher than the set voltage, and outputs the delayed first signal D1.
Is lower than the set voltage, the first signal D1 input from the outside is output without delay.

The first output circuit 3 inputs and outputs the first signal D1 output from the output control circuit 2. The second output circuit 4 directly inputs and outputs the signal D2 input from the outside together with the first signal D1 without passing through the output control circuit 2.

[0035]

Therefore, according to the present invention, when the power supply voltage Vcc is equal to or higher than the set voltage, the output control circuit 2 delays the signal D1 input from the outside by a predetermined time and outputs the delayed signal D1 to the first output circuit 3. To do. When the power supply voltage Vcc is lower than the set voltage, the output control circuit 2 outputs the first signal D1 input from the outside to the first output circuit 3 without delaying.

On the other hand, the second output circuit 4 directly inputs the second signal D2 input from the outside without passing through the output control circuit 2. Therefore, when the signals D1 and D2 are simultaneously input from the outside when the power supply voltage Vcc is equal to or higher than the set voltage, the first signal D1 output from the first output circuit 3 is output.
Is delayed by the delay time of the output control circuit 2 with respect to the second signal D2 output from the second output circuit 4.

If the signals D1 and D2 are simultaneously input from the outside when the power supply voltage Vcc is lower than the set voltage,
The first signal D1 and the second signal output from the first output circuit 3
And the second signal D2 outputted from the output circuit 4 of FIG.

[0038]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in a dynamic RAM (DRA
An embodiment embodied in the output circuit M) will be described with reference to the drawings.

FIG. 2 shows the structure of the DRAM of this embodiment. The memory cell array 21 is composed of memory cells (not shown) arranged two-dimensionally, and each memory cell stores 1-bit data.

The external addresses A0 to A9 are divided into row addresses and column addresses via the address buffer 22, and the row address is input to the row decoder 23 and the column address is input to the column decoder 24, respectively.

By the row decoder 23 and the column decoder 24, the external addresses A0 to A9 are X and Y.
Are converted into one combination of the respective select signals. That X
One combination of X and Y select lines (not shown) is selected by each of the Y and Y select signals, and the memory cell at the intersection of the selected X and Y select lines is determined. The determined memory cell is the target of read and write operations. The column decoder 2
The Y select signal generated by 4 is output to the memory cell array 21 via the sense amplifier and the input / output (I / O) gate 25.

The clock generator 26 controls the mode control 27, the row decoder 23 and the sense amplifier I based on the row address strobe signal RAS.
Controls the / O gate 25. In addition, mode control 2
7 and the clock generator 26 are mutually controlled.

The column address / strobe signal bar CAS is input to the L active input terminal of the AND circuit 28, and H
A control signal of the clock generator 26 is input to the active input terminal.

The clock generator 29 is an AND circuit 2
8 based on the level of the output signal of 8
2, the column decoder 24, the write clock generator 30, and the data output buffer 31 are controlled.

The mode control 27 is refreshed.
The address counter 32 is controlled so that the refresh address signal generated by the refresh address counter 32 is output to the predecoder 33 in the address buffer 22.

That is, the mode control 27 controls the refresh address counter 32 so as to execute the CAS-before-laser (CBR) refresh based on the row address strobe signal bar RAS and the column address strobe signal bar CAS. To do.

The write clock generator 30 receives the data input buffer 34 based on the control signal of the clock generator 29 and the write enable signal bar WE.
To control.

That is, the data input buffer 34, based on the control signal of the write clock generator 30,
Data Dn, Dn + 1, Dm, Dm + 1 ...
Output to the sense amplifier / I / O gate 25 or the data output buffer 31.

The data output buffer 31 outputs
Based on the enable signal bar OE, the data read from the memory cell array 21 or the data output from the data input buffer 34 is output as 4-bit data Dn, Dn + 1, Dm, Dm + 1. .

Of the data Dn, Dn + 1, Dm, Dm + 1 output from the data output buffer 31, the data Dn, Dn + 1.
Are output to the outside via the output control circuit 35 and the output circuit 36, respectively. In addition, the data output buffer 31
Data Dm, Dm + 1 out of the data Dn, Dn + 1, Dm, Dm + 1 output from are output to the outside only through the output circuit 36, respectively.

That is, the data stored in the appropriate memory cell in the memory cell array 21 selected by the external addresses A0 to A9 is read out, and the data is output via the sense amplifier / I / O gate 25. Three
It is output to 1. The data read from the memory cell is output from the data output buffer 31 to each output circuit 36 directly or via the output control circuit 35, and each output circuit 36 outputs data Dn, Dn + 1, Dm, Dm. It is output as +1.

Further, when performing a verify check, etc., the data Dn, input to the data input buffer 34,
Dn + 1, Dm, Dm + 1 ... are directly output to the data output buffer 3
It is also possible to output from 1.

All the output control circuits 35 have the same structure, and the control signals φ output from the voltage detection circuit 37,
Controlled by bar φ. Further, all the output circuits 36 have the same configuration.

A substrate bias generator 38 is provided in the DRAM so that an appropriate substrate bias is applied to the semiconductor substrate on which the DRAM is formed.

FIG. 3 shows a circuit diagram of the voltage detection circuit 37. The voltage detection circuit 37 is an enhancement type NMOS.
Transistor 41, resistor R and CMOS inverter 42-
And 44.

The gate and drain of the NMOS transistor 41 are connected to the high potential side power supply VCC, and the source is connected to the ground via the resistor R and the input terminal of the CMOS inverter 42.

The CMOS inverters 42 to 44 are connected in series, and the control signal φ is taken out from the output terminal of the CMOS inverter 43 and the control signal bar φ is taken out from the output terminal of the CMOS inverter 44.

Therefore, the drain voltage and the gate voltage of the NMOS transistor 41 become equal to the voltage VCC of the high-potential-side power supply VCC (hereinafter referred to as the power supply voltage VCC). Therefore, when the power supply voltage VCC is lower than the threshold voltage Vth41 of the NMOS transistor 41, the NMOS transistor 4
The source-gate voltage VGS41 of 1 is the threshold voltage Vth41.
It becomes lower (VGS41 <Vth41). Then, the NMOS transistor 41 becomes the off region, and the source voltage VS of the NMOS transistor 41 (that is, the input voltage of the inverter 42) becomes the ground level (that is, the L level).

As a result, the control signal φ which is the output signal of the CMOS inverter 43 becomes L level and the control signal φ which is the output signal of the CMOS inverter 44 becomes H level (that is, the power supply voltage VCC).

On the other hand, when the power supply voltage VCC is higher than the threshold voltage Vth41 of the NMOS transistor 41, the source-gate voltage VGS41 of the NMOS transistor 41 becomes higher than the threshold voltage Vth41 (VGS41 ≧ Vth41). Then,
The NMOS transistor 41 becomes the ON region, and the NMOS
The source voltage VS of the transistor 41 becomes a value obtained by subtracting the threshold voltage Vth41 from the power supply voltage VCC (VS = V
CC-Vth41).

When the source-drain voltage VDS41 of the NMOS transistor 41 is lower than the value obtained by subtracting the threshold voltage Vth41 from the source-gate voltage VGS41 (VDS41 <VGS41-Vth41), the NMOS transistor 41 becomes It becomes a linear region.

When the NMOS transistor 41 is in the linear region, the source voltage VS of the NMOS transistor 41 becomes lower than the threshold voltage of the CMOS inverter 42,
The output signal of the CMOS inverter 42 becomes H level.

As a result, the control signal φ which is the output signal of the CMOS inverter 43 becomes L level and the control signal bar φ which is the output signal of the CMOS inverter 44 becomes H level.

When the source-drain voltage VDS41 is higher than the value obtained by subtracting the threshold voltage Vth41 from the source-gate voltage VGS41 (VDS41≥VGS41-Vth41),
The NMOS transistor 41 is in the saturation region.

When the NMOS transistor 41 is in the saturation region, the source voltage VS of the NMOS transistor 41 becomes higher than the threshold voltage of the CMOS inverter 42,
The output signal of the CMOS inverter 42 becomes L level.

As a result, the control signal φ which is the output signal of the CMOS inverter 43 becomes H level and the control signal φ which is the output signal of the CMOS inverter 44 becomes L level.

Thus, the source-gate voltage VGS41
When the source-drain voltage VDS41 of the NMOS transistor 41 is lower than the value obtained by subtracting the threshold voltage Vth41 from (that is, when the NMOS transistor 41 is in the linear region in the off region or the on region), the control signal φ is The L level and the control signal bar φ become the H level.

When the source-drain voltage VDS41 of the NMOS transistor 41 is higher than the value obtained by subtracting the threshold voltage Vth41 from the source-gate voltage VGS41 (that is, the NMOS transistor 41 is in the saturation region in the ON region). At some time), the control signal φ becomes H level and the control signal bar φ becomes L level.

That is, when the power supply voltage Vcc is lower than the voltage determined corresponding to the threshold voltage Vth41 of the NMOS transistor 41 (hereinafter referred to as the set voltage A), the control signal φ is L level and the control signal bar φ is It becomes H level. On the other hand, when the power supply voltage Vcc is equal to or higher than the set voltage A, the control signal φ
Becomes H level, and the control signal bar φ becomes L level.

By the way, the threshold voltage Vth41 of the NMOS transistor 41 can be appropriately adjusted by changing the transistor size of the NMOS transistor 41.

Therefore, the set voltage A can be appropriately determined by changing the transistor size of the NMOS transistor 41. By setting the resistance value of the resistor R sufficiently large, when the NMOS transistor 41 is in the ON region, the high potential side power supply VCC
Therefore, it is possible to reduce the through current flowing to the ground through the NMOS transistor 41 and the resistor R. Therefore, even if the NMOS transistor 41 is in the ON region, the power consumption does not increase.

FIG. 4 shows a circuit diagram of the output control circuit 35. Data Dn output from the data output buffer 31,
Dn + 1 is each CMOS transmission gate 51,
It is input to one terminal of 52.

The other terminal of the CMOS transmission gate 51 is directly connected to the output circuit 36, and C
The other terminal of the MOS transmission gate 52 is connected to the output circuit 36 via the four inverters 53 to 56 connected in series.

CMOS transmission gate 51
Is composed of an NMOS transistor 51a and a PMOS transistor 51b. The CMOS transmission gate 52 is composed of an NMOS transistor 52a and a PMOS transistor 52b.

The control signal bar φ of the voltage detection circuit 37 is input to the gates of the NMOS transistor 51a and the PMOS transistor 52b. Also, NM
OS transistor 51b and PMOS transistor 5
The control signal φ of the voltage detection circuit 37 is input to each gate of 2a.

Therefore, when the control signal φ is at L level and the control signal bar φ is at H level, the CMOS transmission gate 51 is opened and the CMOS transmission gate 52 is closed. On the contrary, when the control signal φ is at H level and the control signal bar φ is at L level, the CMOS transmission gate 52 is opened and the CMOS transmission gate 51 is closed.

When the CMOS transmission gate 52 is opened and the CMOS transmission gate 51 is closed, the data Dn, Dn + 1 output from the data output buffer 31 is output to the output circuit 36 via the four inverters 53 to 56. To be done.

On the other hand, the CMOS transmission gate 51 is opened and the CMOS transmission gate 52 is opened.
When is closed, the data Dn and Dn + 1 output from the data output buffer 31 are directly output to the output circuit 36.

That is, when the control signal φ is at the H level and the control signal bar φ is at the L level, the output from the data output buffer 31 is greater than when the control signal φ is at the L level and the control signal bar φ is at the H level. The data Dn and Dn + 1 are output to each output circuit 36 with a delay of the total value of the delay times of the inverters 53 to 56.

By the way, as described above, the control signal φ becomes L level and the control signal bar φ becomes H level when the power supply voltage VCC is lower than the set voltage A. Further, the control signal φ becomes H level and the control signal bar φ becomes L level when the power supply voltage Vcc is equal to or higher than the set voltage A.

Therefore, when the power supply voltage Vcc is equal to or higher than the set voltage A, the data Dn, output from the data output buffer 31 is higher than when the power supply voltage Vcc is lower than the set voltage A.
Dn + 1 is output to each output circuit 36 with a delay of the total value of the delay times of the respective inverters 53 to 56.

FIG. 5 shows a circuit diagram of the output circuit 36. The output circuit 36 is a CMOS inverter, and the data Dm, Dm + 1 directly sent from the data output buffer 31
Alternatively, the data Dn, Dn + 1 sent via the output control circuit 35 is input.

Then, the output circuit 36 outputs the inputted data Dn, Dn + 1, Dm, Dm + 1 to the outside. Next, the operation of this embodiment configured as described above will be described with reference to FIG. Since the operation of the DRAM is known and is not directly related to the gist of the present invention, here,
The description is omitted.

When the power supply voltage Vcc is equal to or higher than the set voltage A, the gate 52 of each output control circuit 35 is opened and the gate 51 is closed. Therefore, among the data Dn, Dn + 1, Dm, Dm + 1 output from the data output buffer 31, the data Dn, Dn + 1 is the inverter of each output control circuit 35 for the data Dm, Dm + 1. It is output to each output circuit 36 with a delay of the total value of the delay times 53 to 56.

Therefore, as shown in FIG. 7, the data Dn, Dn + 1, Dm, Dm + output from the data output buffer 31 is output.
When 1 falls from the H level to the L level, the data Dn, Dn + 1 among the data Dn, Dn + 1, Dm, Dm + 1 output from each output circuit 36 becomes the data Dm, Dm + 1. On the other hand, the L level is switched to the H level with a delay.

Similarly, when the data Dn, Dn + 1, Dm, Dm + 1 output from the data output buffer 31 rises from the L level to the H level, the data Dn, Dn + output from each output circuit 36. Data Dn, Dn + 1 out of 1, Dm, Dm + 1
Switches from the H level to the L level with a delay with respect to the data Dm and Dm + 1.

As described above, when the power supply voltage Vcc is equal to or higher than the set voltage A, the data D output from each output circuit 36.
Data n, Dn + 1, Dm, Dm + 1 are data Dn, Dn + 1
The rising and falling edges are delayed with respect to m and Dm + 1.

Therefore, even if the data Dn, Dn + 1, Dm, Dm + 1 of the same level are simultaneously output from the data output buffer 31, the total value of the output currents of the output circuits 36 becomes transiently large. Even if there is a mismatch in the characteristic impedance of the output line, each data Dn, Dn + 1, D
Noise such as ringing does not occur in m and Dm + 1.

When the power supply line has a narrow line width and the power supply capacity seen from each output circuit 36 is small, the data Dn, Dn + 1, Dm, Dm + of the same level is output from the data output buffer 31.
Even if 1s are output at the same time, a large amount of current is not drawn from the power supply at once. Therefore, the fluctuation of the power supply level (the fluctuation of the power supply voltage Vcc and the ground level) does not occur, and the fluctuation of the power supply level does not cause a malfunction in the semiconductor memory device.

On the other hand, when the power supply voltage Vcc is lower than the set voltage A, the gate 51 of each output control circuit 35 is opened and the gate 52 is closed. Therefore, the data Dn, Dn + 1, Dm, Dm + 1 output from the data output buffer 31 are all output to the output circuits 36 at the same time.

Therefore, the data Dn, Dn + 1, Dm, Dm + 1 output from the data output buffer 31 changes from H level to L level.
When falling to the level, the data Dn, Dn + 1, Dm, Dm + 1 output from the output circuits 36 all switch from the L level to the H level at the same time.

Similarly, when the data Dn, Dn + 1, Dm, Dm + 1 output from the data output buffer 31 rises from the L level to the H level, the data Dn, Dn + output from each output circuit 36. 1, Dm and Dm + 1 all switch from the H level to the L level at the same time.

As described above, when the power supply voltage Vcc is lower than the set voltage A, the rising and falling edges of the data Dn, Dn + 1, Dm, Dm + 1 output from the output circuits 36 are all equal.

At this time, the rising and falling edges of the data Dn, Dn + 1, Dm, Dm + 1 output from each output circuit 36 are defined only by the operating speed of the output circuit 36 which is a CMOS inverter. It doesn't become loose.

Therefore, when the power supply voltage Vcc is lower than the set voltage A, the data Dn, output from each output circuit 36,
The time required for rising and falling of Dn + 1, Dm, Dm + 1 is shortened, and the access time to the DRAM can be shortened.

The present invention is not limited to the above-described embodiment. For example, among the data Dn, Dn + 1, Dm, Dm + 1 output from the data output buffer 31, the data Dm, Dm + 1 can be used. Alternatively, the output control circuit 35 may be provided.
The output control circuit 35 may be provided only for one data Dn, Dn + 1, Dm, Dm + 1.

The data output from the data output buffer 31 is not limited to 4 bits. Further, the output circuit 36 is not limited to the CMOS inverter, and may be an output circuit of another type such as an open drain type or a three-state type.

In addition, a plurality of voltage detection circuits 37 having different set voltages A may be provided and the voltage detection circuits 37 may control the plurality of output control circuits 35. Also,
Not only the output circuit of the semiconductor memory device, but also any output circuit such as an output circuit of an operational amplifier may be used.

[0099]

As described in detail above, according to the present invention, in the output circuit of the semiconductor memory device, when the power supply voltage is high, a transiently large output current flows and noise is generated in the output signal. When the power supply voltage is low, there is an excellent effect that the rise and fall of the output signal can be made steep and the access time can be shortened.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a block circuit diagram of a DRAM according to an embodiment of the present invention.

FIG. 3 is a circuit diagram of a voltage detection circuit 37 according to an embodiment.

FIG. 4 is a circuit diagram of an output control circuit 35 according to an embodiment.

FIG. 5 is a circuit diagram of an output circuit 36 according to an embodiment.

FIG. 6 is a characteristic diagram showing rising edges of data Dn, Dn + 1, Dm, Dm + 1 output from the output circuit 36 of the embodiment.

FIG. 7 is a block circuit diagram showing a configuration of a conventional data output buffer and an output circuit.

FIG. 8 is a circuit diagram of an output circuit 62 of a conventional example.

FIG. 9 is data D output from the output circuit 62 of the conventional example.
It is a characteristic view which shows the rising of n, Dn + 1, Dm, and Dm + 1.

[Explanation of symbols]

 1 voltage detection circuit 2 output control circuit 3 first output circuit 4 second output circuit Vcc power supply voltage D1 first signal D2 second signal

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H03K 17/16 H 9184-5J

Claims (1)

[Claims] 1. A voltage detection circuit (1) for detecting whether or not a power supply voltage (VCC) is higher than a set voltage, and a first signal (D1) inputted from the outside when the power supply voltage (VCC) is higher than the set voltage. ) Is output with a delay of a predetermined time, and when the power supply voltage (VCC) is lower than the set voltage, the first signal (D1) input from the outside is output without delay and an output control circuit (2). , The first signal (D1) output from the output control circuit (2)
And a second signal (D2) input from the outside together with the first output circuit (3) for inputting and outputting
A second output circuit (4) for directly inputting and outputting (4) without passing through the output control circuit (2).