JPH10241367A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To contrive reduction of size and low cost of a chip of a direct sense system dynamic type RAM, etc., by equipping a 1st switch MOSFET pair for selectively becoming the on-state immediately before an operation of a unit amplifier circuit and a 2nd switch MOSFET pair for becoming the on-state or the effective state immediately after the aforesaid operation. SOLUTION: A switch MOSFET pair N5 and N6 constituting a write data transmitting circuit is turned on immediately after the unit amplifier circuit of a sense amplifier SA becomes the operation state, and is finally brought under the complete on-state at the point of time when a write signal is outputted from a write amplifier WA to a complementary common data line CD*. Consequently, the write operation of the write amplifier WA is quickened at high speed. Since the complementary common data line CD* us used on common for transmitting a read signal and a write signal of a read amplifier RA and the write amplifier WA respectively, the number of complementary common data lines CD*s, each requiring a large writing width is reduced, in other write, an area required for the layout of the sense simplifier SA can be reduced, and the size of the dynamic type RAM can be reduced accordingly.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a dynamic RAM (random access memory) employing a direct sense system and a technique particularly effective for use in increasing the speed and reducing the chip size. is there.

[0002]

2. Description of the Related Art A memory array including a word line and a complementary bit line arranged orthogonally and a dynamic memory cell arranged in a lattice at the intersection of the word line and the complementary bit line, and each complementary memory array There is a dynamic RAM including a sense amplifier including a unit amplifier circuit provided corresponding to a bit line. Further, in such a dynamic RAM, between a designated complementary bit line of a memory array, that is, a complementary input / output node of a designated unit amplifier circuit of a sense amplifier and a complementary common data line (common I / O line). Are connected indirectly via the gate of a sense MOSFET (metal oxide semiconductor type field effect transistor; in this specification, a MOSFET is a generic name of an insulated gate type field effect transistor), thereby forming a complementary bit line. There is known a so-called direct sense method capable of accelerating the selection operation and shortening the access time of the dynamic RAM.

[0003]

In a conventional dynamic RAM employing a direct sensing method, as shown in FIG. 11, a sense amplifier SA includes a P-channel MOSFET P1 and an N-channel MOSFET N1, and a P-channel MOSFET P2 and an N-channel MOSFET N2. , A complementary input / output node of the designated unit amplifier circuit and a complementary complementary data line CDW * for writing (here, for example, a non-inverting common data line CDWT and an inverting common data line A common data line CDW * is represented by an asterisk (*), and a so-called non-inverted signal line or the like which is selectively set to a high level when it is enabled is indicated by adding a T to the end of its name. A so-called inverted signal line that is selectively low level Are represented by suffixing B to the end of the name. The same applies to the following.) Switches N3 and N4 for selectively connecting between switches MOSFET N3 and N4 and switches for selectively connecting between complementary complementary data lines CDR * for reading. MO
Includes SFETs N7 and N8.

The switch MOSFETs N3 and N4 and N7 and N8 are selectively and simultaneously turned on by setting the corresponding bits of the bit line select signals YS0 to YSn to a high level. However, switch MOSF
ETN3 and N4 and write complementary common data line CDW
*, A switch M which is selectively turned on in response to a high level of the internal control signal WP during a write operation.
Since OSFET NE and NF are provided, the switch M
OSFETs N3 and N4 are connected to these switch MOSFs.
It is selectively enabled on condition that ETNE and NF are turned on. Needless to say, the internal control signal WP
When the dynamic RAM is set to the write mode, it is selectively set to the high level in response to the low level of the write enable signal WEB which is the activation control signal.

That is, in the conventional dynamic RAM employing the direct sense method, the complementary common data line CDW * for writing and the complementary common data line CDR for reading are used.
Are dedicated and provided separately, and these complementary common data lines extend over a relatively long distance so as to substantially intersect all the complementary bit lines B0 * to Bn * constituting the memory array MARY. It is arranged and formed with a relatively wide metal wiring layer to reduce its wiring resistance. As a result, the required layout area of the sense amplifier SA is increased, and the chip size of the dynamic RAM is increased, which hinders cost reduction. At the time of a write operation, it is necessary to selectively set the internal control signal WP to a high level to turn on the MOSFETs NE and NF. The internal control signal WP includes switch MOSFETs for all unit circuits of the sense amplifier SA.
The gate capacitances of NE and NF are combined. For this reason, the signal path for the internal control signal WP becomes a critical path, and the speed-up of the write operation of the dynamic RAM is restricted.

On the other hand, in the direct sense system, as described above, the switch MOSFETs N7 and N8 are turned on in parallel with the amplification operation of each unit amplifier circuit of the sense amplifier SA, and are connected to the selected word line of the memory array MARY. From a corresponding memory cell to a corresponding complementary bit line B0.
* To Bn * from the beginning of amplification by the unit amplifier circuit to sense MOSFETs N9 and N
By transmitting the data to the read complementary common data line CDR *, that is, the read amplifier RA via A, the read operation is speeded up. However, when a continuous read operation is performed on a selected word line of the memory array MARY, for example, in the page mode, the effect of the direct sense method is not obtained for the second and subsequent bits.
Conversely, the read signal is indirectly transmitted through the gates of the sense MOSFETs N9 and NA, and the level of the read complementary common data line CDR * is lowered, thereby delaying the cycle time of the continuous read operation.

A first object of the present invention is to reduce the chip size of a dynamic RAM or the like that employs a direct sensing system, thereby reducing the cost. A second object of the present invention is to speed up a write operation and a continuous read operation of a dynamic RAM or the like employing a direct sensing method.

[0008] The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0009]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, in a dynamic RAM or the like employing a direct sense method, the complementary common data line is shared for writing and reading, and
For example, between this complementary common data line and the ground potential VSS, a sense MOSFET pair whose gate is coupled to a non-inverting or inverting input / output node of a corresponding unit amplifier circuit of the sense amplifier, respectively, and a unit amplifier of the sense amplifier. A first switch MOSFET pair, which is selectively turned on in response to a high level of a corresponding bit line selection signal immediately before the circuit is brought into an operation state, is provided in series, and further corresponds to the complementary common data line. A second switch MO selectively turned on under the same conditions as the first switch MOSFET pair between the complementary input / output node of the unit amplifier circuit and
An SFET pair and a third switch MOSFET selectively turned on immediately after the unit amplifier circuit is turned on.
Pairs are provided in series.

According to the above-mentioned means, the layout required area of the sense amplifier is reduced by sharing the complementary common data line, and the chip size of a dynamic RAM or the like is reduced.
The cost can be reduced, and the first bit of the continuous read operation is provided by the sense MOSFE.
The transmission of the read signal via the T pair speeds up the bit line selection operation. For the second and subsequent bits, the level on the complementary common data line can be increased by transmitting the signal via the second and third switch MOSFET pairs. It is possible to speed up single and continuous read operations of a dynamic RAM or the like. Further, the third switch MOSFET pair is turned on regardless of the operation mode,
It is possible to eliminate the critical path in the writing operation related to the control and to speed up the writing operation of the dynamic RAM or the like.

[0011]

FIG. 1 is a block diagram showing one embodiment of a dynamic RAM to which the present invention is applied. First, an outline of the configuration and operation of the dynamic RAM according to this embodiment will be described with reference to FIG. Although the circuit elements constituting each block in FIG. 1 are not particularly limited, they are formed on one semiconductor substrate such as single crystal silicon by a known MOSFET integrated circuit manufacturing technique.

Referring to FIG. 1, the dynamic RAM of this embodiment has a memory array MARY, which occupies most of the surface of a semiconductor substrate, as a basic component. The memory array MARY includes a predetermined number of word lines arranged in parallel in the vertical direction in the figure, a predetermined number of complementary bit lines arranged in parallel in the horizontal direction, and an intersection of these word lines and complementary bit lines. And a large number of dynamic memory cells arranged in a lattice. The specific configuration of the memory array MARY will be described later.

A word line forming the memory array MARY is coupled to an X address decoder XD below the word line, and is selectively selected. X address decoder X
D is supplied with i + 1-bit internal address signals X0 to Xi from an X address buffer XB and an internal control signal XG from a timing generation circuit TG. Further, X address signals AX0 to AXi are connected to the X address buffer XB via address input terminals A0 to Ai.
Are supplied in a time-division manner, and an internal control signal XL is supplied from the timing generation circuit TG.

The X address buffer XB takes in and holds the X address signals AX0 to AXi supplied in a time division manner through the address input terminals A0 to Ai in accordance with the internal control signal XL, and also stores these X address signals. Then, the internal address signals X0 to Xi are formed and supplied to the X address decoder XD. X address decoder XD
Is selectively activated in response to the high level of the internal control signal XG, decodes the internal address signals X0 to Xi, and selectively sets a corresponding word line of the memory array MARY to a predetermined selection level. .

Next, the complementary bit lines forming the memory array MARY are coupled to the corresponding unit circuit of the sense amplifier SA on the left side. In the sense amplifier SA,
A not-shown (n + 1) -bit bit line selection signal is supplied from the Y address decoder YD, and the timing generation circuit T
G supplies internal control signals PC and SC and common source signals CSP and CSN. The Y address decoder YD is supplied with i + 1 bit internal address signals Y0 to Yi from the Y address buffer YB.
The internal control signal YG is supplied from the timing generation circuit TG. The Y address buffers AB have Y address signals AY0 to AY via address input terminals A0 to Ai.
i is supplied in a time-division manner, and an internal control signal YL is supplied from the timing generation circuit TG.

The sense amplifier SA is connected to the memory array MAR
There are provided n + 1 unit circuits provided corresponding to the respective complementary bit lines of Y. Each of these unit circuits includes a unit amplifier circuit formed by cross-coupled a pair of CMOS (complementary MOS) inverters, and three unit amplifier circuits. N-channel MOSFET
And a bit line precharge circuit connected in series and parallel. Further, a sense MOSFET pair whose source is coupled to the ground potential VSS and whose gate is coupled to a non-inverting or inverting input / output node of the corresponding unit amplifier circuit, a drain of each sense MOSFET pair and a complementary common data line CD * And a first switch MOSFET pair respectively provided between the non-inverted and inverted signal lines of the corresponding unit amplifier circuit. Second and third switch MOSFET pairs provided in series with the inverted signal line are included.

Three N-channel MOSs forming a bit line precharge circuit of each unit circuit of the sense amplifier SA
The FETs are selectively and simultaneously turned on in response to the high level of the internal control signal PC, and connect the non-inverted and inverted signal lines of the corresponding complementary bit lines of the memory array MARY to the intermediate level between the power supply voltage VCC and the ground potential VSS. It is precharged to the potential HV. In addition, the unit amplifier circuit of each unit circuit is selectively and collectively activated by the power supply voltage VCC supplied to the common source signal line CSP and the ground potential VSS supplied to the common source signal line CSN. The small read signal output from the (n + 1) memory cells coupled to the selected word line of the array MARY via the corresponding complementary bit line is amplified, the power supply voltage VCC is set to the high level, and the ground potential VSS is set to the low level. To be a binary read signal.

On the other hand, the first and second switch MOSFET pairs of each unit circuit of the sense amplifier SA are connected to the corresponding bit line selection signal Y immediately before the unit amplifier circuit is brought into the operating state.
The third switch MOSFET pair is selectively turned on in response to the high levels of S0 to YSn, and is selectively and selectively received in response to the high level of the internal control signal SC immediately after the unit amplifier circuit is brought into the operating state. They are simultaneously turned on. At this time, the sense MOSFET pair of each unit circuit outputs a read signal output from one selected memory cell of the memory array MARY via the corresponding complementary bit line and amplified by the corresponding unit circuit of the sense amplifier SA. To the complementary common data line CD indirectly through its gate
* That is, it is transmitted to the read amplifier RA. The specific configuration and operation of the sense amplifier SA will be described later in detail.

A Y address buffer YB is provided with a Y address signal AY supplied through address input terminals A0 to Ai.
0 to AYi are taken in and held in accordance with the internal control signal YL, and based on these Y address signals, internal address signals Y0 to Yi are formed and supplied to the Y address decoder YD. The Y address decoder YD is selectively activated in response to the high level of the internal control signal YG, decodes the internal address signals Y0 to Yi, and selectively selects corresponding bits of the bit line selection signals YS0 to YSn. To a high level. These bit line selection signals YS0
To YSn are the first and second switches MOSF constituting the corresponding unit circuit of the sense amplifier SA as described above.
Each is supplied to a common coupled gate of the ET pair.

The complementary common data line CD * is commonly connected to the output terminal of the write amplifier WA and the input terminal of the read amplifier RA. The input terminal of the write amplifier WA is coupled to the output terminal of the data input buffer IB, and the input terminal of the data input buffer IB is coupled to the data input terminal Din. The output terminal of read amplifier RA is coupled to the input terminal of data output buffer OB, and the output terminal of data output buffer OB is connected to data output terminal Dou.
t. The write amplifier WA is supplied with the internal control signal WC from the timing generation circuit TG, and the data output buffer OB is supplied with the internal control signal RP.

When the dynamic RAM is selected in the write mode, the data input buffer IB captures and holds the write data supplied via the data input terminal Din and transmits the write data to the write amplifier WA. At this time, the write amplifier WA is selectively activated in response to the high level of the internal control signal WC. After the write data transmitted from the data input buffer IB is converted into a predetermined complementary write signal, the write amplifier WA C
D * via the sense amplifier SA to the memory array MAR
The data is written to one selected memory cell of Y.

On the other hand, when the dynamic RAM is selected in the read mode, the read amplifier RA reads from one selected memory cell of the memory array MARY via the complementary common data line CD *. The signal is further amplified and transmitted to the data output buffer OB.
At this time, the data output buffer OB outputs the internal control signal O
In response to the high level of C, it is selectively activated, and outputs a read signal transmitted from read amplifier RA via data output terminal Dout.

The timing generation circuit TG selectively forms the various internal control signals based on a row address strobe signal RASB, a column address strobe signal CASB, and a write enable signal WEB supplied from outside as a start control signal. It is supplied to each part of the dynamic RAM.

FIG. 2 is a partial circuit diagram of one embodiment of the memory array MARY and the sense amplifier SA included in the dynamic RAM of FIG. FIG.
4 and 4 show signal waveform diagrams of one embodiment of the single read operation mode and the continuous read operation mode of the dynamic RAM of FIG. 1, respectively. FIG. 5 shows one example of the write operation mode of the dynamic RAM. A signal waveform diagram is shown.
Based on these figures, the dynamic RA of this embodiment
M included in memory array MARY and sense amplifier S
The specific configuration and operation of A and its features will be described. In the following circuit diagrams, MOSFETs with an arrow at the channel (back gate) portion are P
It is of a channel type and is distinguished from an N-channel MOSFET without an arrow. In the following signal waveform diagram, the word line W0 in the memory array MARY is used.
Are alternately selected, and in the sense amplifier SA, the complementary bit line B0 * of the memory array MARY is alternatively selected.

In FIG. 2, the memory array MARY is
The drawing includes m + 1 word lines W0 to Wm arranged in parallel in the vertical direction and n + 1 sets of complementary bit lines B0 * to Bn * arranged in parallel in the horizontal direction. At the intersection of these word lines and complementary bit lines, an information storage capacitor Cs and an address selection MOSFET Qa (m +
1) × (n + 1) dynamic memory cells are arranged in a lattice. Address selection MOSF of n + 1 memory cells arranged in the same row of memory array MARY
Gates of ETQa are commonly coupled to corresponding word lines W0 to Wm, respectively. Further, the drains of the address selection MOSFETs Qa of the (m + 1) memory cells arranged in the same column of the memory array MARY alternate with the non-inverted or inverted signal lines of the corresponding complementary bit lines B0 * to Bn * with a predetermined regularity. Is combined with Memory array MARY
Storage capacitors C of all the memory cells constituting
A plate voltage, which is an intermediate potential HV, is supplied to the other electrode of s.

Next, the sense amplifier SA includes n + 1 unit circuits provided corresponding to the complementary bit lines B0 * to Bn * of the memory array MARY, each of which is represented in FIG. As shown, three N
A bit line precharge circuit in which channel MOSFETs NB to NC are connected in series / parallel;
FET P1 and N-channel MOSFET N1 and P-channel MOSFET P2 and N-channel MOS
A unit amplifier circuit including a pair of CMOS inverters formed of FET N2 cross-coupled to each other.

The commonly coupled drains of the MOSFETs P1 and N1 constituting the unit amplifier circuit of each unit circuit of the sense amplifier SA serve as a non-inverting input / output node of each unit amplifier circuit, and correspond to the corresponding complementary bit line B0 of the memory array MARY. * To Bn *, respectively.
The commonly coupled drains of the MOSFETs P2 and N2 serve as inverting input / output nodes of each unit amplifier circuit, and correspond to the corresponding complementary bit lines B0 * to B0 of the memory array MARY.
n * inverted signal lines. The commonly coupled sources of P-channel MOSFETs P1 and P2 are:
A power supply voltage supply node of each unit amplifier circuit is coupled to a common source signal line CSP,
The commonly coupled sources of TN1 and N2 are coupled to the common source signal line CSN as their ground potential supply nodes.

Each unit circuit of the sense amplifier SA further includes N-channel type switch MOSFETs N7 and N8 (in series) provided between the inverted or non-inverted signal line of the complementary common data line CD * and the ground potential of the circuit. First switch MOSFET pair) and sense MOSFET N
9 and NA and the complementary bit line B of the memory array MARY
Non-inverted or inverted signal lines of 0 * to Bn *, that is, provided in series between the non-inverted and inverted input / output nodes of each unit amplifier circuit and the non-inverted or inverted signal line of the complementary common data line CD *. N-channel type pair of switches MO
SFETs N3 and N4 (second switch MOSFET
Pair) and N5 and N6 (third switch MOSFE)
T pair). Of these, the gates of the sense MOSFETs N9 and NA are coupled to the non-inverted or inverted signal lines of the corresponding complementary bit lines B0 * to Bn * of the memory array MARY, that is, to the non-inverted or inverted input / output nodes of the corresponding unit amplifier circuit, respectively. Is done. Also, switch MOSFET
The internal control signal SC is commonly supplied to the gates of N5 and N6, and the corresponding bits of the bit line selection signals YS0 to YSn from the Y address decoder YD are commonly supplied to the gates of the switch MOSFETs N3 and N4 and N7 and N8. Supplied to

As shown in FIGS. 3 to 5, when the row address strobe signal RASB is set to the high level and the dynamic RAM is set to the non-selected state, the internal control signal PC is set to the high level such as the power supply voltage VCC. And
The internal control signal SC is at a low level such as the ground potential VSS. The common source signal line CSP has an invalid level such as the ground potential VSS, and the common source signal line CSN has an invalid level such as the power supply voltage VCC.
The word lines W0 to Wm of the memory array MARY are all set to a non-selection level such as the ground potential VSS, and the bit line selection signals YS0 to YSn are all set to a non-selection level such as the ground potential VSS.

Thus, in the memory array MARY,
The address selection MOSFETs Qa of all the memory cells are turned off and are not selected. In the sense amplifier SA, the switch MOSFET N3 of each unit circuit is used.
And N4, N5 and N6 and N7 and N8 are turned off.
The OSFETs NB to ND are simultaneously turned on, and the non-inverted and inverted signal lines of the complementary bit lines B0 * to Bn * are both precharged to the intermediate potential HV. The non-inverted and inverted signal lines of the complementary common data line CD * are both precharged to a high level such as the power supply voltage VCC by an equalizing MOSFET (not shown) of the read amplifier RA. The data output terminal Dout is connected to the internal control signal O.
The high impedance state Hz is set in response to the low level of C.

In the single read operation mode, the dynamic RAM is set to the selected state by changing the row address strobe signal RASB to a low level, as shown in FIG. X address signals AX0 to AXi are supplied to the address input terminals A0 to Ai in a combination designating the row address X0, that is, the word line W0, in synchronization with the falling edge of the row address strobe signal RASB. Signal CA
The Y address signal A is synchronized with the falling edge of SB.
Y0 to AYi are supplied in a combination specifying the column address Y0, that is, the bit line selection signal YS0. The write enable signal WEB remains at a high level while the dynamic RAM is selected.

In the dynamic RAM, the internal control signal PC is first set to a low level such as the ground potential VSS in response to the low level change of the row address strobe signal RASB, and then the designated word line W0 of the memory array MARY is turned on. High voltage V higher than voltage VCC by at least the threshold voltage of address selection MOSFET Qa.
A selection level such as CH is set. Further, the common source signal lines CSP and CSN are set to an effective level such as the power supply voltage VCC or the ground potential VSS, respectively, with a delay of a predetermined time, and prior to this, that is, each unit amplifier circuit of the sense amplifier SA operates. Immediately before the specified bit line selection signal YS0
The effective level is as follows. And the sense amplifier S
Immediately after each unit amplifier circuit of A is put into the operating state, that is, at the time when the read signal amplification operation by each unit amplifier circuit of the sense amplifier SA is completed, the internal control signal SC is set to the high level. The signal OC is set to the high level.

In the sense amplifier SA, first, upon receiving the low level of the internal control signal PC, the precharge operation of the complementary bit lines B0 * to Bn * by the bit line precharge circuit of each unit circuit is stopped. Also, the memory array MARY
In response to the high voltage VCH of the word line W0,
The n + 1 memory cells coupled to 0 are set to the selected state, and the minute read signals of the corresponding memory cells are output to the complementary bit lines B0 * to Bn *, respectively. These minute read signals are supplied to the sense amplifier SA by setting the common source signal lines CSP and CSN to an effective level.
Of the power supply voltage V
This is a binary read signal of a high level such as CC or a low level such as ground potential VSS.

On the other hand, if the bit line select signal YS0 is set to the high level immediately before the unit amplifier circuit is put into the operating state, the sense amplifier SA switches the switch MO of the corresponding unit circuit.
Switch MOSFET corresponding to SFET N7 and N8
A small read signal output to the designated complementary bit line B0 * is indirectly turned on together with N3 and N4, and indirectly via the gates of the corresponding sense MOSFETs N9 and NA to the complementary common data line CD *, that is, the read amplifier R.
A, and the amplification operation by the read amplifier RA is started. Also, immediately after the unit amplifier circuit is brought into the operating state,
When the internal control signal SC is set to the high level, the switch MOSFETs N5 and N6 of each unit circuit are simultaneously turned on, and the binary read signal obtained by the amplifying operation of the corresponding unit amplifier circuit is switched to the switch MOSFETs N5 and N6.
6 to the complementary common data line CD *, that is, the read amplifier RA. The read signal amplified by the read amplifier RA is output from the data output buffer OB via the data output terminal Dout in response to the high level of the internal control signal OC.

Note that the switch MOSFE is turned on after the unit amplifier circuit of each unit circuit of the sense amplifier SA is brought into the operating state.
Until TN5 and N6 are turned on, the amplitude of the read signal on the complementary common data line CD * is the same as that of the binary read signal on the complementary bit line B0 *.
Since the voltage is indirectly transmitted through the gates of the FETs N9 and NA, the value is set to a relatively small value V1.
After the OSFETs N5 and N6 are turned on, the voltage is set to a relatively large value V2 because the signals are directly transmitted through these switch MOSFETs. Just sense MOSF
Since the transmission of the read signal via the ETN 9 and the NA is performed without waiting for the amplification operation of the unit amplifier circuit, the bit line selection operation of the dynamic RAM is accelerated, and the access time in the read operation mode is shortened. Becomes

Next, when the dynamic RAM is set to the continuous read operation mode, as shown in FIG. 4, the column address strobe signal CASB is repeatedly changed to the low level while the row address strobe signal RASB is kept at the low level, Address input terminals A0 to Ai
Are synchronized with each falling edge of the column address strobe signal CASB.
i are sequentially supplied, for example, in a combination designating the column addresses Y0 and Y1. Thus, in the continuous read operation mode, a continuous read operation can be performed for a maximum of (n + 1) column addresses for one selected word line.

In the dynamic RAM, as described above, the internal control signal PC is first set to the low level in response to the low level change of the row address strobe signal RASB, and the designated word line W0 and bit line selection signal YS are set.
0, the common source signal lines CSP and CSN and the internal control signals SC and OC are sequentially set to a selection level or an effective level at predetermined timings. Among them, the word line W0 and the internal control signals SC and OC are kept at the selected level or the high level during the continuous read operation, but the common source signal lines CSP and CSN
Is returned to an invalid level every time the column address strobe signal CASB is set to the high level, and the bit line selection signal YS0 is replaced with the bit line selection signal YS1 in response to the next low level change of the column address strobe signal CASB.

Each unit circuit of the sense amplifier SA receives the high level of the internal control signal SC and receives a switch MOSFE.
Since TN5 and N6 are kept in the ON state, the read signals of the designated complementary bit lines B0 * and B1 * are directly supplied to the complementary common data via these switch MOSFETs N5 and N6 and the switch MOSFETs N3 and N4. It is transmitted to line CD *. As a result, the amplitude of the read signal on the complementary common data line CD * becomes a relatively large value V2, and the cycle time in the continuous read operation mode of the dynamic RAM is shortened.

On the other hand, when the dynamic RAM is set to the write operation mode, the write enable signal WEB
As shown in FIG. 5, for example, when the operation of amplifying the small read signal by the unit amplifier circuit of the sense amplifier SA is completed, the internal control signal WC is made high. Also, the data input terminal D
In is supplied with write data WD prior to the low level change of the write enable signal WEB. The write data WD is transmitted to the write amplifier WA via the data input buffer iB. When the internal control signal WC is set to the high level, the write amplifier WD supplies the write data to the memory via the complementary common data line CD * and the sense amplifier SA. Data is written to a selected one memory cell of the array.

In this embodiment, the switch MOSFETs N5 and N6, which are the transmission paths of the write data, are turned on immediately after the unit amplifier circuit of the sense amplifier SA is turned on as described above, and the write signal is written. At the time when the signal is output from the amplifier WA to the complementary common data line CD *, it is completely on. That is, in the dynamic RAM according to the present embodiment, a large number of switch MOSFETs serving as write data transmission paths are connected to the write amplifier WA.
Therefore, the writing operation of the write amplifier WA can be accelerated, and the writing operation of the dynamic RAM can be accelerated.

As is clear from the above description, in this embodiment, the complementary common data line CD * is connected to the read complementary common data line for transmitting the read signal of the memory cell designated to the read amplifier RA. , Light amplifier W
A is also used as a write complementary common data line for transmitting a write signal to a memory cell designated by A. As a result, the complementary common data line requiring a relatively large wiring width, that is, the layout required area of the sense amplifier SA can be reduced, so that the chip size of the dynamic RAM can be reduced and its cost can be reduced. Becomes

FIG. 6 is a partial circuit diagram of a second embodiment of the memory array MARY and the sense amplifier SA included in the dynamic RAM to which the present invention is applied, and FIG. A signal waveform diagram of one embodiment of one read operation mode is shown. This embodiment basically follows the embodiment shown in FIGS. 1 to 5, and therefore, a description will be added only for portions different from the embodiments.

In FIG. 6, each unit circuit of the sense amplifier SA includes an N-channel type switch MOSFET N7 provided in series between an inverted or non-inverted signal line of the complementary common data line CD * and the ground potential VSS. N
8 (first switch MOSFET pair) and sense M
The non-inverted and inverted signal lines of the OSFETs N9 and NA and the complementary bit lines B0 * to Bn * of the memory array MARY, that is, the non-inverted and inverted input / output nodes of each unit amplifier circuit and the non-inverted or inverted signal of the complementary common data line CD * A pair of N-channel switches M provided respectively between the lines M
OSFETs N3 and N4 (second switch MOSFET
Pairs) and.

The gates of the sense MOSFETs N9 and NA of each unit circuit are connected to the non-inverted or inverted signal lines of the corresponding complementary bit lines B0 * to Bn * of the memory array MARY, that is, the non-inverted signal of the corresponding unit amplifier circuit of the sense amplifier SA. Alternatively, they are respectively coupled to inverting input / output nodes. The gates of the switch MOSFETs N7 and N8 have bit line selection signals YSA0 to YSA from the Y address decoder YD.
n (first bit line selection signal), the corresponding bits are supplied in common, and the switch MOSFETs N3 and N3
4 have bit line select signals YSB0 to YSBn.
The corresponding bits of the (second bit line selection signal) are supplied in common.

Here, the bit line selection signals YSA0 to YS
An is a common source signal line C as shown in FIG.
Immediately before SP and CSN are set to the valid level, in other words, immediately before each unit amplifier circuit of the sense amplifier SA is put into the operating state, the voltage is alternatively set to the valid level, that is, the high voltage VCH. Also, bit line selection signals YSB0 to YSBn
Immediately after the common source signal lines CSP and CSN are set to the effective level, in other words, immediately after each unit amplifier circuit of the sense amplifier SA is set to the operating state, the effective level is set to the high level, that is, the high voltage VCH. Type RAM
Is kept at this effective level while the device is in the continuous read operation mode.

Thus, the designated complementary bit line B0 * of the memory array MARY, that is, the complementary input / output node of the corresponding unit amplifier circuit of the sense amplifier SA is connected to the corresponding sense MOSFE immediately before the unit amplifier circuit is brought into the operating state.
Immediately after the unit amplifier circuit is activated, the corresponding switch MOSFETs N3 and N3 are selectively and indirectly connected to the complementary common data line CD * via TN9 and NA.
4 selectively and directly via the complementary common data line CD *.
Connected to. As a result, also in this embodiment, the same operation and effect as those of the embodiments of FIGS. 1 to 5 can be obtained. In this embodiment, two bit line selection signals are required for the complementary bit lines B0 * to Bn *, but the required number of switch MOSFETs is small.

FIG. 8 is a partial circuit diagram of a third embodiment of the memory array MARY and the sense amplifier SA included in the dynamic RAM to which the present invention is applied, and FIG. A signal waveform diagram of one embodiment of one read operation mode is shown. This embodiment basically follows the embodiment shown in FIGS. 1 to 5, and therefore, a description will be added only for portions different from the embodiments.

In FIG. 8, each unit circuit of the sense amplifier SA includes an N-channel type switch MOSFET N7 and an N-channel type switch MOSFET N7 provided in series between the inverted or non-inverted signal line of the complementary common data line CD * and the ground potential VSS. N
8 (first switch MOSFET pair) and sense M
The non-inverted or inverted signal lines of the OSFETs N9 and NA and the complementary bit lines B0 * to Bn * of the memory array MARY, that is, the non-inverted and inverted input / output nodes of each unit amplifier circuit and the non-inverted or inverted signal of the complementary common data line CD *. A pair of N-channel switches M provided respectively between the lines M
OSFETs N3 and N4 (second switch MOSFET
Pairs) and.

The gates of the sense MOSFETs N9 and NA of each unit circuit are connected to the non-inverted or inverted signal lines of the corresponding complementary bit lines B0 * to Bn * of the memory array MARY, that is, the non-inverted signal of the corresponding unit amplifier circuit of the sense amplifier SA. Alternatively, they are respectively coupled to inverting input / output nodes. The gates of the switch MOSFETs N7 and N8 and the gates of N3 and N4 are commonly supplied with the corresponding bits of the bit line selection signals YS0 to YSn from the Y address decoder YD.

Here, the bit line selection signals YS0 to YSn
Is a common source signal line CSP as shown in FIG.
And the common source signal lines CSP and CSN are set to the valid level immediately before the potentials of the common source signal lines CSP and CSN are set to the intermediate potential HV immediately before the levels of the common source signal lines CSP and CSN are set to the valid level, that is, immediately before the unit amplifier circuits of the sense amplifier SA are activated. After that, when a relatively short predetermined time elapses, that is, immediately after each unit amplifier circuit of the sense amplifier SA is brought into the operating state, the voltage is alternatively set to the high voltage VCH.

When the bit line selection signal YS0 is alternatively set to the intermediate potential HV, in the corresponding unit circuit of the sense amplifier SA, the switch MOSFETs N7 and N8 are turned on, but the other pair of switch MOSFETs N3 and N4 are turned on. Since the non-inverted and inverted signal lines of the corresponding complementary bit line B0 * are precharged to the intermediate potential HV, they remain off. Therefore, memory array MA
The RY complementary bit line B0 *, that is, the complementary input / output node of the corresponding unit amplifier circuit of the sense amplifier SA, is connected to the corresponding sense MOSFET just before the unit amplifier circuit is brought into the operating state.
It is selectively and indirectly connected to complementary common data line CD * via TN9 and NA.

The unit amplifier circuit of the sense amplifier SA is activated, and the bit line selection signal YS0 is alternatively set to the high voltage VC.
When it is set to H, another pair of switch MOSFETs N3 and N4 are turned on in the unit circuit corresponding to the sense amplifier SA. Therefore, after the unit amplifier circuit is activated, the complementary bit line B0 of the memory array MARY is set.
* That is, the complementary input / output node of the corresponding unit amplifier circuit of the sense amplifier SA is connected to the corresponding switch MOSFET N3
And N4 selectively and directly to complementary common data line CD *. As a result, also in this embodiment, the same operation and effect as those of the embodiments of FIGS. 1 to 5 can be obtained. In the case of the present embodiment, both the required number of bit line selection signals and the required number of switch MOSFETs can be reduced, and the chip size of the dynamic RAM can be further reduced.

The operational effects obtained from the above embodiment are as follows. (1) Dynamic RA using direct sense
In M, etc., the complementary common data line is shared for writing and reading, thereby reducing the required layout area of the sense amplifier, reducing the chip size of the dynamic RAM and the like, and reducing its cost. Is obtained.

(2) In the above item (1), for example, the gate is coupled between the complementary common data line and the ground potential VSS to the non-inverting or inverting input / output node of the corresponding unit amplifier circuit of the sense amplifier. Sense MOSFE
T pair and a first switch MOSFE selectively turned on in response to the high level of the corresponding bit line selection signal immediately before the unit amplifier circuit of the sense amplifier is turned on.
T pairs are provided in series, and between the complementary common data line and the complementary input / output node of the corresponding unit amplifier circuit are selectively turned on under the same conditions as the first switch MOSFET pair. By providing two switch MOSFET pairs in series and a third switch MOSFET pair selectively turned on immediately after the unit amplifier circuit is turned on, the first bit of the continuous read operation is provided. Can speed up the bit line selection operation by transmitting a signal through a pair of sense MOSFETs, and increase the level of the complementary common data line for the second and subsequent bits by transmitting a signal through a pair of second and third switch MOSFETs. In addition, the effect of accelerating single and continuous read operations of a dynamic RAM or the like can be obtained.

(3) In the above items (1) and (2), the third switch MOSFET pair is turned on irrespective of the operation mode, and there is no critical path at the time of the write operation related to the control. And the like can be speeded up.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the above embodiment, and various modifications can be made without departing from the gist of the invention. Needless to say, there is. For example, in FIG. 1, the dynamic RAM can adopt a so-called multi-bit configuration in which a plurality of bits of storage data are simultaneously input or output. In this case, since the dynamic RAM requires a plurality of complementary common data lines,
The effect of the present invention on the chip size is even greater. The memory array MARY can be divided into a plurality of memory mats including its peripheral circuits, and can also adopt a shared sense system. Dynamic type R
The AM does not make it mandatory to adopt the address multiplex system, and its block configuration, the names and effective levels of the start control signal and the internal control signal, the combination thereof, and the like can take various embodiments.

In FIGS. 2, 6 and 8, the memory array MARY and the sense amplifier SA can include an arbitrary number of redundant elements, and as described above, include a plurality of memory mats including their peripheral circuits. It can also be split. Specific circuit configurations of the memory array MARY and the sense amplifier SA, the polarity and absolute value of the power supply voltage, and the MO
The conductivity type and the like of the SFET are not restricted by these embodiments.

In FIG. 3 to FIG. 5, FIG. 7, and FIG.
The absolute level and timing relationship of each signal does not limit the invention. In FIG. 7, bit line select signals YSA0 to YSAn which are alternatively enabled immediately before the unit amplifier circuit of the sense amplifier SA is brought into an operating state.
May be set to the invalid level immediately after the bit line selection signals YSB0 to YSBn are alternatively set to the valid level.

If it is not a problem to separately provide the read complementary common data line CDR * and the write complementary common data line CDW *, as shown in FIG. 10, for example, internal control signals for the MOSFETs NE and NF in FIG. By setting WP to an effective level such as the high voltage VCH immediately after the unit amplifier circuit of the sense amplifier SA is brought into the operating state, the cycle time of the continuous read operation of the dynamic RAM is increased, and the write operation thereof is accelerated. can do.

In the above description, the case where the invention made by the present inventor is mainly applied to the dynamic RAM, which is the field of application as the background, has been described.
The present invention is not limited to this. For example, the present invention can be applied to various memory integrated circuits such as a pseudo-static RAM having a dynamic RAM as a basic configuration and a dual-port memory, and a logic integrated circuit device incorporating these memory integrated circuits. . INDUSTRIAL APPLICABILITY The present invention can be widely applied to at least a semiconductor memory device adopting a direct sense method and an apparatus or a system including such a semiconductor memory device.

[0061]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, in a dynamic RAM or the like employing a direct sense method, the complementary common data line is shared for writing and reading, and the gate thereof is connected between the complementary common data line and the ground potential VSS. Selection by receiving a pair of sense MOSFETs respectively coupled to the non-inverting or inverting input / output nodes of the corresponding unit amplifier circuit and the corresponding bit line selection signal at a high level immediately before the unit amplifier circuit of the sense amplifier is activated. A first pair of switch MOSFETs which are turned on in a serial manner is provided in series, and further, the first pair of switch MOSFETs and the first pair of switch MOSFETs are provided between the complementary common data line and a complementary input / output node of a corresponding unit amplifier circuit. Second switch M selectively turned on under the same conditions
An OSFET pair and a third switch MOSFET that is selectively turned on immediately after the unit amplifier circuit is turned on.
T pairs are provided in series. As a result, the required layout area of the sense amplifier is reduced, and the dynamic RA
The size of the chip such as M can be reduced and the cost can be reduced. For the first bit of the continuous read operation, the bit line selection operation is accelerated by transmitting a signal through the sense MOSFET pair, and the second bit is Thereafter, the level of the complementary common data line is expanded by signal transmission through the second and third switch MOSFET pairs, so that single and continuous read operations of a dynamic RAM or the like can be speeded up. Further, the third switch MOSFET pair is turned on regardless of the operation mode,
It is possible to eliminate the critical path at the time of the write operation related to the control and to speed up the write operation of the dynamic RAM or the like.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a dynamic RAM to which the present invention is applied.

FIG. 2 is a partial circuit diagram showing one embodiment of a memory array and a sense amplifier included in the dynamic RAM of FIG. 1;

FIG. 3 is a signal waveform diagram showing one embodiment of a single read operation mode of the dynamic RAM of FIG. 1;

FIG. 4 is a signal waveform diagram showing one embodiment of a continuous read operation mode of the dynamic RAM of FIG. 1;

FIG. 5 is a signal waveform diagram showing one embodiment of a write operation mode of the dynamic RAM of FIG. 1;

FIG. 6 is a partial circuit diagram showing a second embodiment of a memory array and a sense amplifier included in a dynamic RAM to which the present invention is applied;

7 is a signal waveform diagram showing one embodiment of a read operation mode of the dynamic RAM of FIG. 6;

FIG. 8 is a partial circuit diagram showing a third embodiment of a memory array and a sense amplifier included in a dynamic RAM to which the present invention is applied.

FIG. 9 is a signal waveform diagram showing one embodiment of a read operation mode of the dynamic RAM of FIG. 8;

FIG. 10 shows a dynamic RAM to which the present invention is applied.
FIG. 11 is a signal waveform diagram showing a fourth embodiment of the read operation mode of FIG.

FIG. 11 is a partial circuit diagram showing an example of a memory array and a sense amplifier included in a dynamic RAM developed by the present inventors prior to the present invention.

[Explanation of symbols]

MARY: memory array, SA: sense amplifier, X
D: X address decoder, YD: Y address decoder, XB: X address buffer, YB: Y address buffer, A0 to Ai: Address signal or its input terminal, WA: Write amplifier, RA: Read Amplifier, I
B: Data input buffer, OB: Data output buffer, Din: Data input terminal, Dout: Data output terminal, TG: Timing generation circuit, RASB: Row address strobe signal or its input terminal, CASB
..... column address strobe signal or its input terminal,
WEB: Write enable signal or its input terminal. W
0 to Wm word line, B0 * to Bn * complementary bit line, Cs information storage capacitor, Qa address selection MOSFET, P1 to P2 P channel MOSF
ET, N1 to NF ... N-channel MOSFET. CS
P, CSN ... common source line, YS0 to YSn ... bit line selection signal, CD * ... complementary common data line. YSA
0 to YSAn, YSB0 to YSBn... Bit line selection signals.

Continued on front page (72) Inventor ▲ Taka ▼ Kazumasa Shima 2326 Imai, Ome-shi, Tokyo Inside Device Development Center, Hitachi, Ltd.

Claims (8)

[Claims] 1. A unit amplifier circuit provided corresponding to each complementary bit line of a memory array, and a sense MOSFE whose gate is coupled to a non-inverted or inverted input / output node of the corresponding unit amplifier circuit, respectively.
T pair, respectively, provided between the drain of the corresponding sense MOSFET pair and the inverted or non-inverted signal line of the first complementary common data line, and selectively turned on immediately before the unit amplifier circuit is brought into the operating state. First switch MOSFET
Immediately after the unit amplifier circuit is provided between the non-inverted or inverted input / output node of the corresponding unit amplifier circuit and the non-inverted or inverted signal line of the second complementary common data line. A second pair of switch MOSFETs selectively turned on or enabled. 2. The semiconductor memory device according to claim 1, wherein said first and second complementary common data lines are composed of the same complementary common data line. 3. The semiconductor device according to claim 1, wherein the first and second switch MOSFET pairs are selectively and simultaneously turned on in accordance with a common bit line selection signal. The storage device is the second switch MOSFET.
A third switch M provided in series with the T pair and selectively turned on immediately after the unit amplifier circuit is activated.
A semiconductor memory device including an OSFET pair. 4. The method according to claim 3, wherein the third switch MOSFET pair is continuously turned on while a continuous read operation is performed on the same word line of the memory array. A semiconductor memory device characterized by the following. 5. The first bit line selection signal according to claim 1, wherein the first switch MOSFET pair is selectively set to an effective level immediately before the unit amplifier circuit is activated. The second pair of switch MOSFETs is selectively turned on according to a second bit line selection signal which is selectively set to an effective level immediately after the unit amplifier circuit is brought into an operating state. A semiconductor memory device which is turned on in a typical manner. 6. The semiconductor memory device according to claim 5, wherein the second bit line selection signal is continuously set to a valid level while a continuous read operation is performed on the same word line of the memory array. A semiconductor memory device characterized by the above-mentioned. 7. The device according to claim 1, wherein the first and second switch MOSFET pairs are selectively and simultaneously turned on in accordance with a common bit line selection signal. The non-inverted and inverted signal lines are precharged to an intermediate potential between the first and second power supply voltages, and the bit line selection signal is initially set to the intermediate level when the bit line selection signal is set to a valid level. A semiconductor memory device having a predetermined high voltage potential when a predetermined time has elapsed since the unit amplifier circuit was activated. 8. The method according to claim 7, wherein the bit line selection signal is continuously set to the high voltage potential during a continuous read operation on the same word line of the memory array. A semiconductor memory device characterized by the following.