JPH06302190A - Semiconductor storage - Google Patents

Abstract

PURPOSE:To reduce the required number of complementary common data lines while accelerating the read mode of a dynamic RAM, etc., by realizing the complementary common data line for write and the complementary common data line for read with a set of complementary common data lines. CONSTITUTION:The output nodes of unit amplifiers USA0-USAn constituting sense amplifiers SA are connected to the noninverted and the inverted signal lines of the dealing complementary bit line B0 of a memory array MARY on the one hand. On the other hand, the output nodes are connected to complementary common data CD through a pair of N channel switch MOSFETs N3, N4. Bit line selection signals WYS0-WYSn for write are supplied in common from a Y address decoder YD to the gates of the switches N3, N4. Thus, the switches N3, N4 are turned on selectively by that the signals WYS0-WYSn become 'H', and a complementary write signal is written in the memory cell in the array MARY through the switches N3, N4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device and, more particularly, to a technique which is particularly effective when used for a dynamic RAM (random access memory) adopting a direct sense system.

[0002]

2. Description of the Related Art As illustrated in FIG. 3, complementary bit lines B0 * to Bn * of a memory array MARY (here, for example, a non-inverted bit line B0T and an inverted bit line B0B are combined to form a complementary bit line B0 *. In addition, a so-called non-inverted signal line or the like that is selectively set to a high level when it is enabled may be represented by adding T to the end of the name. Unit amplifier circuits USA0 to USAn provided corresponding to the so-called inverted signal lines and the like that are selectively brought to a low level when is enabled.
Corresponding bit line selection signals YS0 to YS0 provided respectively between the non-inverting and inverting input / output nodes of these unit amplifier circuits and the non-inverting and inverting signal lines of the complementary common data line CD *.
A pair of switch MOSFETs (metal oxide semiconductor type field effect transistors. In this specification, MOSFETs are collectively referred to as insulated gate type field effect transistors) N10 and N1 which are selectively turned on according to YSn.
1 and a sense amplifier SA including
Same switch MOSFET for writing and reading stored data to and from selected memory cell of ARY
And dynamic RA performed via complementary common data lines
There is M.

On the other hand, as illustrated in FIG. 4, the unit amplifier circuits USA0 to USAn and these unit amplifier circuits US
It is selectively turned on according to the corresponding write bit line selection signals WYS0 to WYSn provided between the non-inverted and inverted I / O nodes of A0-USAn and the non-inverted and inverted signal lines of the write complementary common data line WCD *, respectively. The switch MOSFETs N3 and N4 which are brought into a state and a pair of sense MOSFEs whose sources are coupled to the ground potential of the circuit and whose gates are coupled to the non-inverting and inverting input / output nodes of the corresponding unit amplifier circuits USA0 to USAAn, respectively.
TN7 and N8 are selectively provided according to the corresponding read bit line selection signals RYS0 to RYSn provided between the drains of these sense MOSFETs and the non-inverted and inverted signal lines of the read complementary common data line RCD *. Switch MOSFETs N5 and N placed in the state
A memory array M including a sense amplifier SA including
Separate switch MOSFETs for writing and reading stored data to and from selected memory cells of ARY
Also, there is a so-called direct sense dynamic RAM which is performed via complementary common data lines.

A dynamic RAM adopting the direct sense system is described in, for example, Japanese Patent Application No. 1-65841.

[0005]

In the dynamic RAM of FIG. 3, the full-swing complementary write signal output from the write amplifier WA is a switch for turning on the sense amplifier SA from the complementary common data line CD *. The data is transmitted to the designated memory cell of the memory array MARY through the MOSFETs N10 and N11 and written. The read signal output from the designated memory cell of the memory array MARY is the sense amplifier SA.
After being converted into a high-level or low-level binary read signal by the corresponding unit amplifier circuits USA0 to USAAn, the switch MOSFETs N10 and N11 which are turned on are transmitted to the read amplifier RA through the complementary common data line CD *. . That is, the dynamic type R of FIG.
In the case of AM, the write and read signals to and from the selected memory cell of the memory array MARY are transmitted as the voltage signals through the complementary common data line CD *, which allows the complementary common data line to be written and read. By sharing, the chip area of the dynamic RAM can be reduced.

However, in the complementary common data line CD *,
As is well known, a relatively large load capacitance is coupled, and its value is increasing as the dynamic RAM is highly integrated and scaled up. This delays the level change of the read signal on the complementary common data line CD * particularly in the read mode, which restricts the speeding up of the read mode of the dynamic RAM.

On the other hand, in the dynamic RAM shown in FIG. 4, the full-swing complementary write signal output from the write amplifier WA is also turned on from the write complementary common data line WCD * as the voltage signal to turn on the sense amplifier SA. It is transmitted to and written in a designated memory cell of the memory array MARY via the switch MOSFETs N3 and N4. However, the memory array MARY
The read signal output from the designated memory cell is the unit amplifier circuit USA0 corresponding to the sense amplifier SA.
~ After the high-level or low-level binary read signal is output by USAAn, the corresponding sense MOSFET N
It is converted into a current signal by 7 and N8 and is transmitted to the read amplifier RA from the switch MOSFETs N5 and N6 which are turned on through the read complementary common data line RCD *. That is, in the case of the dynamic RAM of FIG. 4, the read signal is transmitted as a current signal without changing the potential of the read complementary common data line RCD * to which a relatively large load capacitance is coupled. Therefore, the read mode of the dynamic RAM can be speeded up.

However, in recent years, the dynamic type RAM tends to be large-scaled and have a large number of bits, and accordingly, the required number of complementary common data lines is increasing. As described above, in the conventional dynamic RAM adopting the direct sense method, the read complementary common data line RCD is used.
Since the * and the write complementary common data line WCD * are separately provided, the chip area becomes large, which hinders the cost reduction of the dynamic RAM.

An object of the present invention is to reduce the chip area of a dynamic RAM and the like while promoting the cost reduction while utilizing the features of the direct sense system.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0011]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, in a dynamic RAM or the like that adopts the direct sense method, the first switch MOS that transmits the write signal output from the write amplifier as a voltage signal to the selected memory cell of the memory array.
The FET and the second switch MOSFET for transmitting the read signal output from the selected memory cell of the memory array to the read amplifier as a current signal are coupled to the same complementary common data line, and the direct sense system is adopted. The complementary complementary common data line for writing and the complementary common data line for reading, which are separately provided in the dynamic RAM or the like, are realized by a pair of complementary common data lines.

[0012]

According to the above means, the required number of complementary common data lines can be reduced while utilizing the advantage of the direct sense system, that is, the read mode of the dynamic RAM or the like can be accelerated. It is possible to reduce the chip area of the dynamic RAM or the like to be adopted and promote the cost reduction.

[0013]

1 is a block diagram of an embodiment of a dynamic RAM to which the present invention is applied. First, the outline of the configuration and operation of the dynamic RAM of this embodiment will be described with reference to FIG. The circuit elements forming each block in FIG. 1 are not particularly limited,
It is formed on a single semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique.

In FIG. 1, the dynamic RAM of this embodiment has a memory array MARY, which is arranged so as to occupy most of the surface of a semiconductor substrate, as its basic constituent element. As will be described later, the memory array MARY has m + 1 word lines W0 to Wm arranged in parallel in the vertical direction of the figure and n + 1 sets of complementary bit lines B arranged in parallel in the horizontal direction.
0 * to Bn * are included. At the intersections of these word lines and complementary bit lines, (m + 1) × (n + 1) dynamic memory cells are arranged in a grid pattern. The specific configuration of the memory array MARY will be described in detail later.

The word lines W0 to Wm forming the memory array MARY are coupled to the X address decoder XD.
The X address decoder XD has an X address buffer XB.
To i + 1 bit internal address signals X0 to Xi, and the timing generation circuit TG supplies the internal control signal XG. Further, the X address signal X is sent to the X address buffer XB via the address input terminals AX0 to AXi.
X0 to AXi are supplied, and the internal control signal AL is supplied from the timing generation circuit TG.

The X address buffer XB fetches the X address signals AX0 to AXi supplied via the address input terminals AX0 to AXi in accordance with the internal control signal AL,
The internal address signals X0 to Xi are formed based on these X address signals while being held, and are supplied to the X address decoder XD. The X address decoder XD is selectively activated by the internal control signal XG being set to the high level, decodes the internal address signals X0 to Xi, and corresponds to the word lines W0 to W of the memory array MARY.
Alternatively, m is set to a high-level selected state.

Next, the complementary bit lines B0 * to Bn * forming the memory array MARY are coupled to the sense amplifier SA. The sense amplifier SA includes a Y address decoder Y
D to write bit line selection signals WYS0 to WYSn
And read bit line selection signals RYS0 to RYSn, and the internal control signal P from the timing generation circuit TG.
A is supplied. The Y address decoder YD is supplied with the j + 1-bit internal address signals Y0 to Yj from the Y address buffer YB and the internal control signal YG from the timing generation circuit TG. Further, the Y address buffer YB is supplied with the Y address signals AY0 to AYj via the address input terminals AY0 to AYj, and the internal control signal AL is supplied from the timing generation circuit TG.

The sense amplifier SA is a memory array MAR.
It includes n + 1 unit circuits provided corresponding to the Y complementary bit lines B0 * to Bn *. As will be described later, each of these unit circuits has a unit amplifier circuit USA0-USAAn formed by cross-coupling a pair of CMOS inverters.
Between the non-inverted and inverted signal lines of the complementary bit lines B0 * to Bn *, that is, the non-inverted and inverted input / output nodes of the unit amplifier circuits USA0 to USAAn and the non-inverted and inverted signal lines of the complementary common data line CD *. A pair of firsts respectively provided in
Unit switch circuit US whose switch MOSFET and its gate whose source is coupled to the ground potential of the circuit correspond to
A pair of sense MOSFETs respectively coupled to non-inverting or inverting input / output nodes of A0-USAn, drains of these sense MOSFETs and complementary common data line CD *
And a pair of second switch MOSFETs respectively provided between the non-inverted and inverted signal lines.

Of these, the unit amplifier circuit US of each unit circuit
A <b> 0 to USAn are selectively and simultaneously activated by setting the internal control signal PA to a high level, and n + are coupled to the selected word line of the memory array MARY.
Corresponding complementary bit lines B0 * to B from one memory cell
The minute read signal output via n * is amplified to be a high level or low level binary read signal. The first switch MOSFET is alternatively turned on by setting the corresponding write bit line selection signals WYS0 to WYSn to a high level, and the write amplifier W
A complementary write signal supplied as a voltage signal from A through the complementary common data line CD * is transmitted to one selected memory cell of the memory array MARY to write it. Furthermore, the second switch MOSFET is selectively turned on by setting the corresponding read bit line selection signals RYS0 to RYSn to the high level, and the drain of the designated pair of sense MOSFETs and the complementary common data line. C
The connection with D * is selectively established. At this time, the sense MOSFET converts a read signal output as a voltage signal from one selected memory cell of the memory array MARY into a current signal, and transmits the current signal to the read amplifier RA via the complementary common data line CD *. . The specific configuration of the sense amplifier SA will be described later in detail.

The Y address buffer YB fetches the Y address signals AY0 to AYj supplied through the address input terminals AY0 to AYj in accordance with the internal control signal AL,
The internal address signals Y0 to Yj are formed based on these Y address signals while being held and supplied to the Y address decoder YD. The Y address decoder YD is selectively activated by the internal control signal YG being set to a high level, and decodes the internal address signals Y0 to Yj to write bit line selection signals WYS0 to WYSn or read bits. Line selection signals RYS0 to RYSn
Is alternatively set to the high level. Needless to say, the write bit line selection signals WYS0 to WYSn are alternatively set to the high level when the dynamic RAM is set to the write mode, and the read bit line selection signals RYS0 to RYS0.
RYSn is alternatively set to the high level when the dynamic RAM is set to the read mode.

The complementary common data line CD * is coupled to the output terminal of the write amplifier WA and further coupled to the input terminal of the read amplifier RA. The input terminal of the write amplifier WA is coupled to the output terminal of the data input buffer IB, and the input terminal of the data input buffer IB is coupled to the data input terminal Din. The output terminal of the read amplifier RA is coupled to the input terminal of the data output buffer OB, and the output terminal of the data output buffer OB is coupled to the data output terminal Dout. An internal control signal WP is supplied from the timing generation circuit TG to the write amplifier WA, and an internal control signal RP is supplied to the read amplifier RA.

The data input buffer IB fetches the write data supplied via the data input terminal Din and transfers it to the write amplifier WA when the dynamic RAM is selected in the write mode. The write amplifier WA is selectively activated by receiving the high level of the internal control signal WP, sets the write data transmitted from the data input buffer IB to a predetermined complementary write signal, and then sets the complementary common data line CD *. Through the memory array MA
Write to one selected memory cell of RY. In this embodiment, the level of the complementary write signal output from the write amplifier WA is fully swung between the power supply voltage of the circuit and the ground potential.

On the other hand, when the dynamic RAM is selected in the read mode, the read amplifier RA is selectively operated by setting the internal control signal RP to the high level to select the memory array MARY. The read signal output from the other memory cell via the complementary common data line CD * is further amplified and transmitted to the data output buffer OB. This read signal is sent from the data output buffer OB to the outside of the dynamic RAM via the data output terminal Dout. In this embodiment, the read signal transmitted via the complementary common data line CD * is the current signal as described above. Therefore, the read amplifier RA includes a current-voltage conversion circuit for converting the read signal into a voltage signal.

The timing generation circuit TG is provided with a chip enable signal CE which is externally supplied as a start control signal.
B, the write enable signal WEB, the output enable signal OEB, and the refresh control signal RFB are used to selectively form the various internal control signals described above, and a dynamic R
Supply to each part of AM.

FIG. 2 shows a circuit diagram of an embodiment of the memory array MARY and the sense amplifier SA included in the dynamic RAM of FIG. Based on the figure, the specific configurations and operations of the memory array MARY and the sense amplifier SA included in the dynamic RAM of this embodiment and the features of the dynamic RAM of this embodiment will be described. In the circuit diagram below, a MOSFET whose channel (back gate) is marked with an arrow
Is a P-channel type and is shown as distinguished from an N-channel MOSFET without an arrow.

In FIG. 2, the memory array MARY is
It includes m + 1 word lines W0 to Wm arranged in parallel in the vertical direction of the figure, and n + 1 sets of complementary bit lines B0 * to Bn * arranged in parallel in the horizontal direction. At the intersection of these word lines and complementary bit lines, an information storage capacitor Cs and an address selection MOSFET Qa (m +
1) × (n + 1) dynamic memory cells are arranged in a grid. Address selection MOSF of n + 1 memory cells arranged in the same row of the memory array MARY
The gates of ETQa are commonly coupled to corresponding word lines W0 to Wm, respectively. In addition, m arranged in the same row
The drains of the address selection MOSFETs Qa of the +1 memory cells are alternately coupled to the corresponding non-inverted or inverted signal lines of the complementary bit lines B0 * to Bn * with a predetermined regularity. A predetermined plate voltage HV is commonly supplied to the other electrodes of the information storage capacitors Cs of all the memory cells forming the memory array MARY.

Next, the sense amplifier SA includes n + 1 unit circuits provided corresponding to the complementary bit lines B0 * to Bn * of the memory array MARY. As shown in FIG. 2, each of these unit circuits has a unit amplifier circuit USA0-USAAn in which a pair of CMOS inverters composed of P-channel MOSFET P1 and N-channel MOSFET N1 or P-channel MOSFET P2 and N-channel MOSFET N2 are cross-coupled. including. MO constituting the unit amplifier circuits USA0 to USAn
The drains of the SFETs P1 and N1 that are commonly connected to each other serve as a non-inverting input / output node of each unit amplifier circuit, and
The commonly coupled drains of TP2 and N2 are used as inverting input / output nodes of each unit amplifier circuit. In addition, MOSFE
The sources of TP1 and P2 are commonly coupled to the common source line SP as a power supply voltage supply node of each unit amplifier circuit,
The sources of the MOSFETs N1 and N2 are commonly coupled to the common source line SN as a ground potential supply node of each unit amplifier circuit.

The common source line SN receives an internal control signal PA at its gate, and is an N-channel type drive MOSFE.
The common source line SP is coupled to the ground potential of the circuit through TN9, and the gate of the common source line SP is the inverted signal of the internal control signal PA by the inverter V1, that is, the inverted internal control signal P.
It is coupled to the power supply voltage of the circuit through a P-channel drive MOSFET P3 that receives AB. As a result, the drive MOSFETs N9 and P3 are selectively turned on when the internal control signal PA is set to the high level and the inverted internal control signal PAB is set to the low level, whereby the unit amplifier circuits USA0 to USAAn are selectively selected. And they are activated all at once.

The non-inverting and inverting input / output nodes of the unit amplifier circuits USA0-USAAn forming the sense amplifier SA are
On the other hand, it is coupled to the non-inverted and inverted signal lines of the corresponding complementary bit lines B0 * to Bn * of the memory array MARY, and on the other side, a pair of N-channel type switch MOSFETs N3 and N4 (first switch MO
SFET) to the complementary common data line CD *. The gates of the switch MOSFETs N3 and N4 are
Corresponding write bit line selection signals WYS0 to WYSn are commonly supplied from the Y address decoder YD.

As a result, the switch MOSFETs N3 and N4 have the corresponding write bit line selection signal WYS.
When 0 to WYSn are set to the high level, they are alternatively turned on, and are complementary to the corresponding unit amplifier circuits USA0 to USAn of the sense amplifier SA, that is, the complementary bit lines B0 * to Bn * of the memory array MARY. The common data line CD * is selectively connected. Dynamic type R
Complementary common data line C when AM is in write mode
A full swing complementary write signal is supplied to the D * from the write amplifier WA. This complementary write signal is transmitted as a voltage signal to one selected memory cell of the memory array MARY via the switch MOSFETs N3 and N4 which are turned on, and is written therein.

Each unit circuit of the sense amplifier SA further has a pair of N-channel type sense MOSFETs whose sources are coupled to the circuit ground potential (first power supply voltage).
Another pair of N channel type switch MOSFETs N5 and N6 (second switch M) provided between N7 and N8 and the drains of these sense MOSFETs and the non-inverted and inverted signal lines of the complementary common data line CD *, respectively.
OSFET). Of these, sense MO
The gates of the SFETs N7 and N8 are coupled to the non-inverting and inverting input / output nodes of the corresponding unit amplifier circuits USA0 to USAAn, that is, the non-inverting and inverting signal lines of the corresponding complementary bit lines B0 * to Bn *, respectively, and the switch MOSFE.
The Y address decoder YD is provided at the gates of TN5 and N6.
To the corresponding read bit line selection signals RYS0-R
YSn is supplied.

As a result, the switch MOSFETs N5 and N6 have corresponding read bit line selection signals RYS.
When 0 to RYSn are set to the high level, they are alternatively turned on, and the corresponding sense MOSFETs N7 and N8 are turned on.
The drain and the complementary common data line CD * are selectively connected. At this time, the sense MOSFETs N7 and N8 convert the read signal established as a binary voltage signal at the non-inverting and inverting input / output nodes of the corresponding unit amplifier circuits USA0 to USAAn into a current signal, and the complementary common data line CD *. To the read amplifier RA. As a result, the read signal is transmitted to the read amplifier RA at a high speed without the need to change the potential of the complementary common data line CD * to which a relatively large load capacitance is coupled,
As a result, the read mode of the dynamic RAM can be speeded up.

As described above, in the dynamic RAM of this embodiment, the first switch for transmitting the complementary write signal output from the write amplifier WA as a voltage signal to one selected memory cell of the memory array MARY. M
The complementary common data line CD * in which the OSFETs N3 and N4 and the second switch MOSFETs N5 and N6 for transmitting the read signal output from one selected memory cell of the memory array MARY to the read amplifier RA as a current signal are the same. And the write complementary common data line and the read complementary common data line, which are separately provided in the conventional dynamic RAM adopting the direct sense method, are realized by a pair of complementary common data lines CD *. As a result, the required number of complementary common data lines can be reduced while taking advantage of the features of the direct sense method, that is, while increasing the read mode of the dynamic RAM, and thus the chip area of the dynamic RAM is reduced. It is possible to promote cost reduction.

As shown in the above embodiment, the present invention is a dynamic RAM adopting a direct sense system.
The following operational effects can be obtained by applying the present invention to a semiconductor memory device such as. That is, (1) dynamic RA using the direct sense method
In M and the like, a first switch MOSFET for transmitting a write signal output from the write amplifier to the selected memory cell of the memory array as a voltage signal, and a read signal output from the selected memory cell of the memory array as a current A complementary complementary common data line for writing, which is separately provided in the conventional dynamic RAM adopting the direct sense method, by coupling the second switch MOSFET transmitting to the read amplifier as a signal to the same complementary common data line. Also, there is an effect that the complementary common data line for reading can be realized by one set of complementary common data lines.

(2) According to the above item (1), it is possible to reduce the required number of complementary common data lines while taking advantage of the direct sense method, that is, while accelerating the read mode of a dynamic RAM or the like. The effect of being able to be obtained is obtained. (3) According to the above items (1) and (2), it is possible to reduce the chip area of a dynamic RAM or the like that employs the direct sense method and to promote cost reduction.

The invention made by the inventors of the present application has been specifically described above based on the embodiments. However, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say.
For example, in FIG. 1, the memory array MARY of the dynamic RAM can be divided into a plurality of sub memory arrays, or a so-called shared sense method can be adopted. Further, the dynamic RAM can have a so-called multi-bit configuration in which a plurality of bits of stored data are simultaneously input or output, or a so-called address multiplex system. Various embodiments can be adopted for the block configuration of the dynamic RAM, the combination of the activation control signal and the internal control signal, and the like.

In FIG. 2, the sense amplifier SA is a precharge circuit for setting the non-inverted and inverted signal lines of the complementary bit lines B0 * to Bn * to the half precharge level when the dynamic RAM is in the non-selected state. Can be included. The drive MOSFETs N9 and P3 are
It can be configured by a plurality of drive MOSFETs that are in a parallel configuration and are sequentially turned on after a predetermined time. When the dynamic RAM has a multi-bit configuration, the sense amplifier SA can simultaneously set a plurality of sets of complementary bit lines and complementary common data lines. In this case, the required number of complementary common data lines is still only one half, and the effect of the present invention is more exerted. Depending on the configuration of the read amplifier RA, the sense MOSFET N7
And the sources of N8 can be coupled to the supply voltage of the circuit. Furthermore, various embodiments can be adopted for the specific circuit configuration of the memory array MARY and the sense amplifier SA, the polarity and absolute value of the power supply voltage, the conductivity type of the MOSFET, and the like.

In the above description, the case where the invention made by the present inventor is mainly applied to the dynamic type RAM which is the field of application which is the background of the invention has been described.
The present invention is not limited to this, and can be applied to various memory integrated circuits such as a pseudo static RAM having a dynamic RAM as a basic configuration and a dual port memory, and a logic integrated circuit device including these memory integrated circuits. . The present invention can be widely applied to at least a semiconductor memory device employing the direct sense method and a semiconductor device incorporating such a semiconductor memory device.

[0039]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, in a dynamic RAM or the like adopting the direct sense method, the first switch MO that transmits the write signal output from the write amplifier to the selected memory cell of the memory array as a voltage signal.
The direct sense method is adopted by coupling the SFET and the second switch MOSFET for transmitting the read signal output from the selected memory cell of the memory array to the read amplifier as a current signal to the same complementary common data line. The complementary complementary common data line for writing and the complementary common data line for reading, which are separately provided in the conventional dynamic RAM or the like, are realized by one set of complementary common data lines. As a result, it is possible to reduce the required number of complementary common data lines while utilizing the advantage of the direct sense method, that is, while increasing the speed of the read mode of the dynamic RAM and the like. It is possible to reduce the chip area and promote cost reduction.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a dynamic RAM to which the present invention is applied.

FIG. 2 is a circuit diagram showing an embodiment of a memory array and a sense amplifier included in the dynamic RAM of FIG.

FIG. 3 is a circuit diagram showing an example of a memory array and a sense amplifier included in a conventional dynamic RAM.

FIG. 4 is a circuit diagram showing another example of a memory array and a sense amplifier included in a conventional dynamic RAM.

[Explanation of symbols]

MARY ... Memory array, SA ... Sense amplifier, XD ... X address decoder, YD ... Y address decoder, XB ... X address buffer, YB.
..Y address buffer, WA ... Write amplifier, R
A ... Read amplifier, IB ... Data input buffer, OB ... Data output buffer, TG ... Timing generation circuit. W0 to Wm ... Word line, B0 * to B
n * ... Complementary bit line, Cs ... Information storage capacitor, Qa ... Address selection MOSFET, USA0
USAn ... Unit amplifier circuit, P1 to P3 ... P channel MOSFET, N1 to N11 ... N channel MOSFET, V1 ... Inverter.

Claims (2)

[Claims] 1. A semiconductor memory device which employs a direct sensing method and performs write and read operations of stored data to and from selected memory cells of a memory array through the same complementary common data line. 2. The semiconductor memory device, wherein a unit amplifier circuit provided corresponding to each complementary bit line forming the memory array, non-inverting and inverting input / output nodes of the unit amplifier circuit, and the complementary common data. A pair of first switch MOSFETs which are respectively provided between the non-inverted line and the inverted signal line and which are selectively turned on in accordance with the corresponding write bit line selection signal, and the source of which is the first switch MOSFET.
Of the pair of sense MOSFETs, the gates of which are coupled to the power supply voltage of the pair and the gates of which are coupled to the non-inverting or inverting input / output nodes of the corresponding unit amplifier circuit,
A pair of second switch MOSFETs provided between the drain of ET and the non-inverted or inverted signal line of the complementary common data line and selectively turned on in accordance with a corresponding read bit line selection signal; 2. The semiconductor memory device according to claim 1, further comprising a sense amplifier.