JPH11328952A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the power consumption in a selfrefresh mode on the like while securing the high speed operations of a dynamic RAM in a normal mode. SOLUTION: In the dynamic RAM having a selfrefresh mode, MOSFETP1 to P4, which constitute the peripheral circuit of an X address decoder XD, and N1 to N4 are set to a low threshold value voltage. Then, a substrate voltage switching circuit VS is provided so that the potentials of substrate voltages VBP and VBN supplied to the MOSFETP1 to P4 and the N1 to N4 are made to the same potential of an internal voltage VDL supplied to the sources of each MOSFET as the operating power supply or a ground potential VSS during a normal mode. During a selfrefresh mode, the voltages are set to an internal voltage VPP, that is higher than the voltage VDL, or set to an internal voltage VBB, which is a prescribed negative potential.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a dynamic RAM (random access memory) having a self-refresh mode and a technique particularly effective when used for speeding up and reducing power consumption.

[0002]

2. Description of the Related Art Information storage capacitor and address selection M
A memory array in which dynamic memory cells composed of OSFETs (metal oxide semiconductor type field effect transistors; in this specification, MOSFETs are collectively referred to as insulated gate type field effect transistors) are arranged in a lattice pattern as a basic component. There is a dynamic RAM.
The dynamic memory cells constituting the memory array of the dynamic RAM require a refresh operation for reading and rewriting the stored data within a predetermined period. For example, the refresh operation for all the word lines is autonomously performed during standby or the like. Has a self-refresh mode for execution.

[0003]

In recent years, the technology for miniaturization and high integration of semiconductor integrated circuits has been remarkably advanced, and dynamic RAMs and the like have also benefited from them and have been increasing in scale and capacity. In addition, miniaturized MOSFET
In order to prevent the destruction of elements such as the above, and to reduce the power consumption of large-scale and large-capacity dynamic RAMs and the like, the operating voltage of the operating power supply is being reduced. In order to make up for the delay, the threshold voltage of MOSFETs, which constitute peripheral circuits and the like, is being reduced.
However, lowering the threshold voltage of the MOSFET, on the other hand, causes an increase in the subthreshold current,
As a result, a reduction in power consumption of the dynamic RAM particularly in the self-refresh mode is hindered.

SUMMARY OF THE INVENTION An object of the present invention is to provide a dynamic RAM in which power consumption in a self-refresh mode or the like is reduced while ensuring high-speed operation in a normal mode.
And other semiconductor integrated circuit devices.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0006]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, in a dynamic RAM or the like having a self-refresh mode, the threshold voltage of a MOSFET constituting a peripheral circuit and the like is lowered, a substrate voltage switching circuit is provided, and P-channel and N-channel MOSFETs constituting a peripheral circuit and the like are provided. The potential of the substrate voltage supplied to the substrate unit is set to M
The same potential as the first internal voltage or the ground potential supplied to the source of the OSFET, and in the self-refresh mode, for example, a word line selection potential or a predetermined negative potential higher than the first internal voltage, respectively.

According to the above means, in the normal mode, high-speed operation is performed by utilizing the characteristics of the low threshold voltage type MOSFET.
Can be greatly reduced in the reverse bias state, so that the power consumption in the self-refresh mode can be significantly reduced while maintaining the high speed in the normal operation of the dynamic RAM or the like.

[0008]

FIG. 1 is a block diagram showing one embodiment of a dynamic RAM (semiconductor integrated circuit device) to which the present invention is applied. First, an outline of the configuration and operation of the dynamic RAM according to this embodiment will be described with reference to FIG. The circuit elements constituting each block in FIG. 1 are formed on a single semiconductor substrate surface such as single crystal silicon by a known MOSFET integrated circuit manufacturing technique.

Referring to FIG. 1, a dynamic RAM of this embodiment has a memory array MARY, which occupies most of the semiconductor substrate surface, as a basic component. Memory array MARY includes a predetermined number of word lines arranged in parallel in the vertical direction in the figure, and a predetermined number of sets of complementary bit lines arranged in parallel in the horizontal direction. At the intersections of these word lines and complementary bit lines, a large number of dynamic memory cells composed of information storage capacitors and address selection MOSFETs are arranged in a grid.

A word line constituting the memory array MARY is coupled to an X address decoder XD and is alternatively set to a predetermined selection level. The X address decoder XD is supplied with i + 1-bit internal address signals X0 to Xi from an X address buffer XB, and is supplied with an internal control signal XG from a timing generation circuit TG. The X address buffer XB is supplied with X address signals AX0 to AXi from an external access device via address input terminals A0 to Ai in a time-division manner, and receives an i + 1-bit refresh address signal from a refresh control circuit RFC. R0 to Ri are supplied, and further, internal control signals XL and RF are supplied from the timing generation circuit TG. The internal control signal RF is a dynamic R
When the AM is selected in the normal operation mode, it is set to the low level, and the self-refresh mode and the CBR (C
(AS before RAS) When set to a selected state in a refresh mode such as a refresh mode, it is set to a high level.

When the dynamic RAM is selected in the normal operation mode and the internal control signal RF is at a low level, the X address buffer XB is an (i + 1) -bit X address supplied via address input terminals A0 to Ai. The signals AX0 to AXi are captured and held according to the internal control signal XL. When the dynamic RAM is selected in the refresh mode and the internal control signal RF is set to the high level, the i + 1-bit refresh address signal R supplied from the refresh control circuit RFC is supplied.
0 to Ri are captured and held in accordance with the internal control signal XL. Then, based on these X address signals or refresh address signals, internal address signals X0 to Xi are formed and supplied to an X address decoder XD.

X address decoder XD is selectively activated in response to the high level of internal control signal XG, decodes internal address signals X0-Xi, and selects a corresponding word line of memory array MARY. To the selection level.

In this embodiment, a peripheral circuit of a dynamic RAM including an X address decoder XD is constituted mainly by a low threshold voltage type MOSFET, and is generated by lowering a power supply voltage VDD supplied from the outside. The internal voltage VDL and the ground potential VSS are used as the operation power supply. The word line selection level is an internal voltage VPP generated by boosting the power supply voltage VDD and having an absolute value greater than the power supply voltage VDD. The non-selection level is the ground potential VSS supplied from the outside. .

On the other hand, a substrate portion of a P-channel MOSFET constituting a peripheral circuit such as an X address decoder XD has:
The substrate voltage VBP is supplied via the substrate voltage switching circuit VS, and the substrate voltage VBN is supplied to the substrate of the N-channel MOSFET. Of these, P-channel MOS
The substrate voltage VBP supplied to the substrate portion of the FET has the same potential as the high-potential-side operation power supply of the peripheral circuit, that is, the internal voltage VDL when the dynamic RAM is in the normal operation mode. Is applied, the word line selection potential, that is, the internal voltage VPP
And the same potential. The substrate voltage VBN supplied to the substrate portion of the N-channel MOSFET is set to the same potential as the low-potential-side operation power supply of the peripheral circuit, that is, the ground potential VSS when the dynamic RAM is set in the normal operation mode. Is set to a predetermined negative potential, that is, internal voltage VBB, when in the self-refresh mode.
A specific configuration example of the X address decoder XD, a specific connection form of the substrate voltage supply path, a potential of each voltage, and the like will be described later in detail.

The refresh control circuit RFC is supplied with an internal control signal RF from the timing generation circuit TG, and its output signal, ie, refresh address signals R0 to Ri.
Is supplied to the X address buffer XB as described above. As described above, the internal control signal RF is set to a low level when the dynamic RAM is selected in the normal mode, and is set to the self refresh mode or the CBR mode.
When set to the selected state in the refresh mode, it is set to the high level at a predetermined timing.

In this embodiment, a dynamic RA
M is a self-refresh mode capable of autonomously executing a refresh operation on all word lines at a predetermined cycle;
It has a CBR refresh mode in which an external access device takes the initiative and can be executed while sequentially specifying word lines by a refresh address counter in a refresh control circuit RFC. Among them, the CBR refresh mode uses a predetermined combination of start-up control signals, that is, a column address strobe signal CASB (here, a so-called inverted signal or the like which is selectively set to a low level when it is enabled) has the same name. The row address strobe signal RASB is denoted by suffix B.
The self-refresh mode is selectively designated by being set to a low level prior to the column address strobe signal CAB.
After being set to the low level after the delay of SB, it is selectively designated by continuing to be at the low level for more than a predetermined time.

When the dynamic RAM is set to the refresh mode and the internal control signal RF is set to the high level, the refresh control circuit RFC counts up the internal refresh address counter and sequentially generates the refresh address signals R0 to Ri. Supply to X address buffer XB.

Next, the complementary bit lines constituting the memory array MARY are coupled to a sense amplifier SA on the left side of the figure, and are selectively connected to the complementary common data lines CD0 * to CD7 through the sense amplifier SA in groups of eight. * (Here, for example, the non-inverted common data line CD0 and the inverted common data line CD
0B together with the complementary common data line CD0 *
And is represented by Hereinafter the same). To the sense amplifier SA, a bit line selection signal of a predetermined bit (not shown) is supplied from the Y address decoder YD, and an internal control signal PA and an internal control signal PC (not shown) are supplied from the timing generation circuit TG. In addition, the Y address decoder YD supplies i + from the Y address buffer YB.
1-bit internal address signals Y0 to Yi are supplied, and internal control signal YG is supplied from timing generation circuit TG.
Is supplied. Further, in the Y address buffer YB,
Y address signals AY0 to AYi are supplied from an external access device via address input terminals A0 to Ai in a time-division manner, and an internal control signal YL is supplied from a timing generation circuit TG.

A Y address buffer YB is provided with a Y address signal AY supplied through address input terminals A0 to Ai.
0 to AYi are captured and held in accordance with the internal control signal YL, and internal address signals Y0 to Yi are formed based on these Y address signals and supplied to the Y address decoder YD. The Y address decoder YD is selectively activated in response to the high level of the internal control signal YG, decodes the internal address signals Y0 to Yi, and
The bit corresponding to the bit line selection signal for the sense amplifier SA is alternatively set to the high selection level.

The sense amplifier SA is connected to the memory array MAR
Y includes a predetermined number of unit circuits provided corresponding to respective complementary bit lines of Y. Each of these unit circuits includes a pair of C
A unit amplifier circuit in which MOS (complementary MOS) inverters are cross-coupled; a bit line precharge circuit in which three N-channel precharge MOSFETs are connected in series / parallel; and a pair of N-channel switch MOSs
And an FET. Among them, the unit amplifier circuit of each unit circuit is selectively and simultaneously operated by the dynamic RAM being selected and the internal control signal PA being set to the high level, and the selected word line of the memory array MARY is selected. The small read signals output from the predetermined number of memory cells coupled via the corresponding complementary bit lines are respectively amplified to produce high-level or low-level binary read signals.

On the other hand, the precharge MOSFETs constituting the bit line precharge circuit of each unit circuit are selectively and simultaneously turned on in response to the high level of the internal control signal PC, and the corresponding complementary bit of the memory array MARY is turned on. The non-inverted and inverted signal lines are precharged to a predetermined intermediate potential. Also, switch MOSFET of each unit circuit
The pair is selectively turned on eight sets at a time in response to the high level of the corresponding bit of the bit line selection signal, and the corresponding eight sets of complementary bit lines and complementary common data lines CD0 * to CD7 * of the memory array MARY are provided. To connect selectively.

The complementary common data lines CD0 * to CD7 *
The data input / output circuit IO is coupled to a corresponding unit circuit. The data input / output circuit IO is supplied with internal control signals WP and OC (not shown) from the timing generation circuit TG.

The data input / output circuit IO includes eight unit circuits provided corresponding to the complementary common data lines CD0 * to CD7 *. Each of these unit circuits includes a write amplifier, a main amplifier, and a data input buffer. And a data output buffer. Of these, the output terminals of the write amplifier and the input terminal of the main amplifier that constitute each unit circuit are connected to the corresponding complementary common data lines CD0 * to CD7 *.
Are commonly connected to each other. Also, the input terminals of the write amplifier of each unit circuit are respectively coupled to the output terminals of the corresponding data input buffers, and the output terminals of the main amplifier of each unit circuit are coupled to the input terminals of the corresponding data output buffers. The input terminal of the data input buffer and the output terminal of the data output buffer constituting each unit circuit are commonly coupled to the corresponding data input / output terminals D0 to D7, respectively. The internal control signal WP is commonly supplied to the write amplifier of each unit circuit, and the internal control signal OC is commonly supplied to the data output buffer of each unit circuit.

The data input buffers of the unit circuits of the data input / output circuit IO are provided with data input terminals D0 to D0 when the dynamic RAM is selected in the write mode.
The 8-bit write data supplied through the interface 7 is fetched and transmitted to the corresponding write amplifier. At this time, the write amplifier of each unit circuit operates the internal control signal WP
, Selectively enter an operation state in response to the write data transmitted from the corresponding data input buffer as predetermined complementary write signals, and then from the complementary common data lines CD0 * to CD7 * via the sense amplifier SA. To write to the selected eight memory cells of the memory array MARY.

On the other hand, when the dynamic RAM is selected in the read mode, the main amplifier of each unit circuit of the data input / output circuit IO changes the sense amplifiers SA and SA from the selected eight memory cells of the memory array MARY. The binary read signal output via complementary common data lines CD0 * to CD7 * is further amplified and transmitted to a corresponding data output buffer. At this time, the data output buffer of each unit circuit selectively operates in response to the high level of the internal control signal OC, further amplifies the read data transmitted from the corresponding main amplifier, and then outputs the data input / output terminal D0. Through D7 to an external access device.

The timing generation circuit TG generates the above-mentioned various internal control signals and the like based on a row address strobe signal RASB, a column address strobe signal CASB and a write enable signal WEB supplied as a start control signal from an external access device. It is selectively formed and supplied to each part of the dynamic RAM.

The dynamic RAM is further supplied with a power supply voltage VDD via an external terminal VDD and a ground potential VSS via an external terminal VSS. Also,
The dynamic RAM includes predetermined internal voltages VPP (second internal voltage), VDL (first internal voltage), and VBB (third internal voltage) based on power supply voltage VDD and ground potential VSS.
Voltage generator circuit VG for generating an internal voltage of the X-ray decoder, and a substrate voltage VB for peripheral circuits such as the X address decoder XD.
A substrate voltage switching circuit VS for selectively switching the potentials of P (first substrate voltage) and VBN (second substrate voltage). Substrate voltage switching circuit VS includes internal voltages VPP, VDL and VBB from internal voltage generating circuit VG.
And an internal control signal SRF is supplied from the timing generation circuit TG. Although not particularly limited,
The power supply voltage VDD is, for example, +2.5 V (volt).
The internal voltages VPP, VDL and VBB are each +
3.6V (first potential), + 1.8V and -1.0
V (second potential). Also, the internal control signal SRF
Is selectively set to a high level at a predetermined timing when the dynamic RAM is set to the self refresh mode.

In the substrate voltage switching circuit VS, the dynamic RAM is set to the normal operation mode and the internal control signal SR
When F is at a low level, the substrate voltages VBP and VBN supplied to the substrate portions of the P-channel and N-channel MOSFETs constituting the peripheral circuit are made equal to the internal voltage VDL or the ground potential VSS supplied to the respective sources. When the dynamic RAM is set to the self-refresh mode and the internal control signal SRF is set to the high level, each potential is set to the internal voltage VPP or VB.
B. The specific configuration and operation of the substrate voltage switching circuit VS including the substrate voltage supply path will be described later in detail.

FIG. 2 is a connection diagram of one embodiment for explaining a substrate voltage supply path of the dynamic RAM of FIG. 1, and FIG. 3 is a diagram of one embodiment of the dynamic RAM of FIG. A signal waveform diagram is shown. The specific connection form of the substrate voltage supply path of the dynamic RAM of this embodiment, the specific configuration and operation of the X address decoder XD and the substrate voltage switching circuit VS, and the features thereof will be described with reference to both figures. Note that the circuit configuration of the X address decoder XD shown in FIG. 2 is a basic configuration example for explaining the substrate voltage supply path, and does not limit the logical configuration and function of the X address decoder XD. . In addition, a MOSF whose substrate (channel) portion is marked with an arrow
ET is a P-channel type (first conductivity type) and an N-channel type (second conductivity type) MOSFET without an arrow.
Are shown separately from

In FIG. 2, X address decoder XD
Includes, but is not limited to, inverters V1 and V2 and a NAND (NAND) gate NA1. The inverters V1 and V2 each include a P-channel MOSFET P1 and an N-channel MOSFET N1, and a P-channel MOSFET P2 and an N-channel MOSFET N2. The NAND gate NA1 includes two P-channel MOSFETs P3 and P4 and N-channel MOSFETs N3 and N4, respectively. It should be noted that P-channel MOSFETs P1 to P2 constituting inverters V1 and V2 and NAND gate NA1
4 and N-channel MOSFETs N1 to N4 are both low threshold voltage type MOSFETs, and have a relatively small threshold voltage, for example, 0.8 V during normal operation.

P channel MOSFETs P1 to P1 constituting inverters V1 and V2 and NAND gate NA1
The source of P4 has an internal voltage VDL (first operating power supply)
And the ground potential VSS (second operation power supply) is supplied to the sources of the N-channel MOSFETs N1 to N4. A substrate voltage VBP is commonly supplied from the substrate voltage switching circuit VS to the substrate portions of the P-channel MOSFETs P1 to P4 constituting these inverters and NAND gates, and the substrate voltage VBN is supplied to the substrate portions of the N-channel MOSFETs N1 to N4. Supplied in common.

An internal signal S1 is supplied from a preceding circuit (not shown) to an input terminal of an inverter V1 constituting the X address decoder XD, that is, a commonly coupled gate of the MOSFETs P1 and N1. The output signal S2 of the inverter V1 is the input terminal of the inverter V2, that is, the MOS transistor.
The output signal S3 of the inverter V2 is supplied to one input terminal of the NAND gate NA1, that is, the commonly coupled gate of the MOSFETs P3 and N3. The internal signal S5 is supplied to the other input terminal of the NAND gate NA1, that is, the commonly coupled gates of the MOSFETs P4 and N4 from another preceding circuit (not shown).
Are supplied to a subsequent circuit (not shown).

As a result, the inverter V1 logically inverts the internal signal S1 to generate an internal signal S2.
Logically inverts the internal signal S2 to obtain an internal signal S3. The NAND gate NA1 is connected to the internal signals S3 and S3.
5 are both set to a high level to selectively set the output signal, that is, the internal signal S4 to a low level such as the ground potential VSS. When one of the internal signals S3 and S5 is set to a low level, the internal signal S4 is set to the internal voltage. High level such as VDL.

Next, substrate voltage switching circuit VS has a switch SW1 receiving internal voltage VPP at one input terminal and internal voltage VDL at the other input terminal, and a ground potential VSS at one input terminal. A switch SW2 for receiving the internal voltage VBB at the other input terminal. The potentials at the output terminals of these switches SW1 and SW2 are supplied to the peripheral circuits of the dynamic RAM including the X address decoder XD as the substrate voltages VBP and VBN, respectively. An internal control signal SRF is commonly supplied to the control terminals of the switches SW1 and SW2 from the timing generation circuit TG. The switches SW1 and SW2 are composed of, for example, MOSFETs whose gates receive the internal control signal SRF or its inverted signal.

Switch SW of substrate voltage switching circuit VS
Reference numeral 1 denotes an off state when the dynamic RAM is set to the normal operation mode and the internal control signal SRF is set to the low level, and the internal voltage VDL is selected to be the substrate voltage VBP. When the dynamic RAM is in the self-refresh mode and the internal control signal SRF is at the high level, it is turned on, and the internal voltage VPP is selected to be the substrate voltage VBP. Similarly, the switch SW2 is turned off when the dynamic RAM is set in the normal operation mode and the internal control signal SRF is set to the low level, and selects the ground potential VSS to set the substrate potential VBN. And
When the dynamic RAM is set to the self-refresh mode and the internal control signal SRF is set to the high level, the dynamic RAM is turned on, the internal voltage VBB is selected and the substrate voltage VBN is selected.
And

The self-refresh mode of the dynamic RAM is not particularly limited, but as shown in FIG. 3, the row address strobe signal RASB is set to a low level such as the ground potential VSS prior to the column address strobe signal CASB. Thereafter, the internal control signal SRF is selectively designated by being kept at the low level for more than the predetermined time ts. In response to this, the internal control signal SRF is changed from a low level such as the ground potential VSS to a high level such as the internal voltage VDL. You.

When the dynamic RAM is set to the normal operation mode and the internal control signal SRF is set to the low level,
In the substrate voltage switching circuit VS, the switches SW1 and SW2 are turned off as described above. Therefore, X
P-channel MOSF forming inverters V1 and V2 of address decoder XD and NAND gate NA1
Substrate voltage VBP supplied to substrate parts of ETP1 to P4
Is set to the same potential as the internal voltage VDL supplied to its source, that is, for example, +1.8 V, and an N-channel MOSFET
The substrate voltage VBN supplied to the substrate units TN1 to N4 is
The same potential as the ground potential VSS supplied to the source, that is, 0V. Therefore, the threshold voltages of MOSFETs P1 to P4 and N1 to N4 are low threshold voltage type M
OSFET's original relatively small value, for example, 0.8V
And the drain-source current becomes large, and the high-speed operation in the normal mode of the dynamic RAM is maintained. However, the sub-threshold current of each MOSFET is increased to some extent by reducing the threshold voltage, but this does not cause much problem in a normal operation mode in which high-speed operation is regarded as important.

On the other hand, when the dynamic RAM is set to the self-refresh mode and the internal control signal SRF is set to the high level, the switches SW1 and SW2 are turned on in the substrate voltage switching circuit VS. Therefore, inverters V1 and V2 of X address decoder XD and P-channel MOSFE forming NAND gate NA1 are provided.
The substrate voltage VBP supplied to the substrate portions of TP1 to P4 is
An internal voltage VPP having an absolute value larger than the internal voltage VDL, that is, for example, +3.8 V, and an N-channel MOSFET
The substrate voltage VBN supplied to the substrate portions N1 to N4 is the negative potential internal voltage VBB, that is, −1.0V. Therefore, MOSFETs P1 to P4 and N1 to N4
It becomes a so-called reverse bias state, and its threshold voltage takes a relatively large value. As a result, these MOSFETs
Of the dynamic RAM in the self-refresh mode is greatly reduced. However, the operation of each MOSFET is correspondingly delayed by increasing the threshold voltage, but this is not a problem in the self-refresh mode where low power consumption is regarded as important.

As described above, in this embodiment, the sub-threshold current in the self-refresh mode is greatly reduced and the power consumption is reduced while maintaining the high speed in the normal operation of the dynamic RAM. Can be.

The operation and effect obtained from the above embodiment are as follows. That is, (1) In a dynamic RAM or the like having a self-refresh mode, a MOSFE constituting a peripheral circuit or the like is used.
In addition to lowering the threshold voltage of T, a substrate voltage switching circuit is provided, and P channel and N
In the normal mode, the potential of the substrate voltage supplied to the substrate portion of the channel MOSFET is the same as the first internal voltage or the ground potential supplied to the source of each MOSFET,
In the self-refresh mode, the potential is set to, for example, a word line selection potential or a predetermined negative potential higher than the first internal voltage.
By utilizing the characteristics of the SFET, high-speed operation is performed, and in the self-refresh mode, each MOSFET can be reverse-biased to greatly reduce its sub-threshold current. (2) According to the above item (1), an effect is obtained that the power consumption in the self-refresh mode can be significantly reduced while maintaining the high speed in the normal operation of the dynamic RAM or the like.

Although the invention made by the inventor has been specifically described based on the embodiments, the invention is not limited to the above-described embodiments, and can be variously modified without departing from the gist of the invention. Needless to say, there is. For example, in FIG. 1, a memory array MARY of a dynamic RAM can be divided into an arbitrary number of memory mats including its direct peripheral circuits. Also, dynamic RAM
Can have any bit configuration, such as × 4 bits or × 16 bits, and does not require address multiplexing as an essential condition. Furthermore, dynamic type R
The AM may have an arbitrary block configuration, and various embodiments may be adopted for the names, combinations, effective levels, power supply voltages and polarities and absolute values of the internal voltages of the start control signal, the address signal, and the internal control signal. sell.

In FIG. 2, the specific configuration of the X address decoder XD and the substrate voltage switching circuit VS and the MOS
The conductivity type and the like of the FET are not limited by the present invention. In this embodiment, the P channel and the N channel M
The substrate voltages VBP and V supplied to the substrate portion of the OSFET
Although the potential of BN is switched at the same time in accordance with the internal control signal SRF, it is also possible to switch only one of them which has a large effect. In FIG. 3, the level and timing condition of the activation control signal for designating the self-refresh mode can be arbitrarily set. Also,
The specific potentials of the substrate voltages VBP and VBN in the normal mode and the self-refresh mode are not limited to those in this embodiment. Further, in this embodiment, the potentials of the substrate voltages VBP and VBN are selectively raised or lowered only in the self-refresh mode. For example, the potential of each substrate voltage is also lowered in the so-called data retention mode or power down mode. It can be selectively raised or lowered.

In the above description, the case where the invention made by the present inventor is mainly applied to the dynamic RAM, which is the field of application as the background, has been described.
The present invention is not limited to this, and can be applied to, for example, various memory integrated circuit devices having a dynamic RAM as a basic configuration, and logic integrated circuit devices including such a memory integrated circuit device. INDUSTRIAL APPLICABILITY The present invention can be widely applied to a semiconductor integrated circuit device requiring at least a substrate voltage and having a normal operation mode and another operation mode in which power consumption is suppressed, and a device or system including the same.

[0044]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, in a dynamic RAM or the like having a self-refresh mode, the threshold voltage of a MOSFET constituting a peripheral circuit and the like is lowered, a substrate voltage switching circuit is provided, and P-channel and N-channel MOSFETs constituting a peripheral circuit and the like are provided. The potential of the substrate voltage supplied to the substrate unit is set to M
The first internal voltage or the ground potential supplied to the source of the OSFET as the operating power is the same as the first internal voltage, and in the self-refresh mode, for example, the word line selection potential or the predetermined negative potential is higher than the first internal voltage. In the normal mode, high-speed operation is performed by utilizing the characteristics of the low threshold voltage type MOSFET. In the self-refresh mode, each MOSFET can be reverse-biased and its subthreshold current can be greatly reduced. The power consumption in the self-refresh mode can be significantly reduced while maintaining the high-speed operation in the normal operation.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a dynamic RAM to which the present invention is applied.

FIG. 2 is a connection diagram showing one embodiment for describing a substrate voltage supply path of the dynamic RAM of FIG. 1;

FIG. 3 is a signal waveform diagram showing one embodiment of the dynamic RAM of FIG. 1;

[Explanation of symbols]

MARY ... memory array, XD ... X address decoder, XB ... X address buffer, RFC ... refresh control circuit, SA ... sense amplifier, YD ... Y address decoder, YB ... Y address buffer, IO ...
Data input / output circuit, TG ... Timing generation circuit, VG
..., Internal voltage generation circuit, VS, substrate voltage switching circuit, D0 to D7, input / output data or input / output terminals thereof,
RASB... Row address strobe signal or its input terminal, CASB... Column address strobe signal or its input terminal, WEB... Write enable signal or its input terminal, A0 to Ai... Address signal or its input terminal, VDD. Power supply voltage or its input terminal, VSS ...
... ground potential or its input terminal, VPP, VDL, VBB
...... Internal voltage, VBP, VBN ...... Substrate voltage. S1-S
5 internal signal, V1 to V2 inverter, NA1
... Nand (NAND) gates, P1-P4 ... P-channel MOSFET, N1-N4 ... N-channel MOS
FET, SW1 to SW2 ... switch.

Claims (5)

[Claims] 1. A semiconductor integrated circuit device comprising a MOSFET, wherein a potential of a substrate voltage supplied to a substrate portion of the predetermined MOSFET is selectively switched according to an operation mode. 2. The device according to claim 1, wherein the predetermined MOSFET receives a first operating power supply at a source thereof and a first operating power supply at a substrate thereof.
A first conductivity type MOSFET receiving a substrate voltage of
And a second conductivity type MOSFET receiving the substrate voltage of the first operation voltage, wherein the potential of the first substrate voltage is selectively set to the first operation power supply potential or the first operation voltage in accordance with an operation mode. A first potential higher than a power supply potential; a potential of the second substrate voltage is selectively set to a second operation power supply potential or a second potential lower than the second operation power supply potential according to an operation mode; A semiconductor integrated circuit device. 3. The semiconductor integrated circuit device according to claim 1, wherein the first and second conductivity type MOSFETs are low threshold voltage type MOSFETs. 4. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is a dynamic RAM having a self-refresh mode, and the first and second conductivity type MOSFETs are the dynamic RAMs. Type RAM
Wherein the potentials of the first and second substrate voltages are selectively set to the first and second potentials, respectively, when the dynamic RAM is in a self-refresh mode. And a semiconductor integrated circuit device. 5. The first operating power supply according to claim 1, wherein the first operating power supply is a first internal voltage obtained by stepping down an externally supplied power supply voltage, The second operating power supply is a ground potential supplied from the outside, and the first potential is a potential of a second internal voltage which is obtained by boosting the power supply voltage and is also a word line selection level. A semiconductor integrated circuit device, wherein the second potential is a potential of a third internal voltage which is a predetermined negative potential.