JP2001024168A - Semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To optimize gate classifications and oxide-film thickness of MOSFETs constituting each section of a dynamic type RAM or the like in response to the applications of the MOSFETs, and to increase the operating speed of the dynamic RAM containing the MOSFETs and lower the dissipation power of the MOSFETs. SOLUTION: An address selecting MOSFET Qa for a memory cell is composed of an (n) channel MOSFET having a conductivity p+ gate different from the diffusion layer of the MOSFET Qa and having a comparatively thick oxide film. A general peripheral circuit such as a sense amplifier using inner voltage having an absolute value smaller than external supply voltage as a main operating power supply is constituted of a (p) channel and (n) channel MOSFETs having a p+ gate and an n+ gate having the same conductivity type as the diffusion layer of the general peripheral circuit respectively and having comparatively thin oxide films. The input stage and output stage or the like of a data input-output circuit IO using the external supply voltage as the main operating power supply are configured of (p) channel and (n) channel MOSFETs having the p+ gate and the n+ gate having the same conductivity type as the diffusion layer of the data input-outp'ut circuit IO respectively and the comparatively thick oxide film.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, for example, to a dynamic RAM (random access memory) having a memory array and peripheral circuits, and to a technique particularly effective when used for high speed and low power consumption. Things.

[0002]

2. Description of the Related Art A dynamic circuit including an information storage capacitor and an N-channel type address selection MOSFET (metal oxide semiconductor type field effect transistor. In this specification, a MOSFET is generally referred to as an insulated gate type field effect transistor). -Type RA having a memory array in which memory cells are arranged in a lattice as a basic component
There is M. The dynamic RAM further includes a C-channel having a combination of P-channel and N-channel MOSFETs.
Peripheral circuits such as a sense amplifier and an address decoder having a MOS (complementary MOS) circuit as a basic element are provided.

[0003]

SUMMARY OF THE INVENTION Prior to the present invention, the inventors of the present invention disclosed a high-speed, large-capacity dynamic RAM.
I was involved in the development of, and noticed the following problems. In other words, this dynamic RAM has an information storage capacitor as described above and an N-channel type address selection MOSF.
A P-channel and N-channel MOSFET comprising a memory array in which dynamic memory cells including ETs are arranged in a lattice and a peripheral circuit having a CMOS circuit as a basic element are formed by a gate process, as is well known. And characteristic operating characteristics according to the oxide film thickness. Also,
In the dynamic RAM, as the speed and capacity of the RAM increase, it is important to properly use the MOSFET in accordance with the operating characteristics of the MOSFET. As a result, the refresh characteristics, power consumption, access time, and manufacturing cost of the dynamic RAM are reduced. to be influenced.

That is, in a recent integrated circuit using a CMOS circuit as a basic element, as a gate process of a MOSFET, for example, a ^{p.sup. +} Gate in which a P-type impurity is implanted into a gate layer made of polysilicon (polycrystalline silicon) or the like;
A so-called dual gate process in which an n ⁺ gate for implanting a type impurity is used is used.

As is well known, MOSFET, i.e. the N-channel MOSFET, the charge transferred through the surface channel line having a P-channel MOSFET and an n ⁺ gate having a p ⁺ gate having a gate of the same conductivity type as the diffusion layer Therefore, the threshold voltage becomes relatively small, and high-speed operation becomes possible. However, if an N-channel MOSFET having an n ⁺ gate is used as it is for an address selection MOSFET of a memory cell, the leak amount of the memory cell increases, and the refresh characteristics of the dynamic RAM deteriorate. In order to cope with this, in a conventional dynamic RAM, a method of applying a so-called return implantation to a channel portion of an address selection MOSFET to increase its threshold voltage to about 1 V (volt) is adopted.

[0006] On the other hand, with the recent development of integrated circuit miniaturization technology, dynamic RAMs have
In order to prevent the destruction of elements such as FETs and to reduce the power consumption of circuits, lowering the operating power supply voltage is becoming common. Although the thickness of the oxide film of the MOSFET has been reduced along with this, the address selection MOSFE of the memory cell to which a relatively high potential word line selection voltage is applied.
For the MOSFETs at the input stage and the output stage such as T and a data input / output circuit serving as an interface circuit with the outside, it is essential to increase the thickness of the oxide film thereof to some extent in consideration of withstand voltage.

For this reason, in the conventional dynamic RAM, a so-called two-type gate oxide film thickness process is used.
Peripheral circuits such as a sense amplifier which uses a relatively low potential internal voltage as a main operation power supply are MOSFEs having a relatively thin oxide film.
A method in which an address selection MOSFET, an input buffer, an output buffer, and the like of a memory cell configured by T and receiving a high-potential word line selection voltage or using an external power supply voltage as a main power supply are configured by MOSFETs having a relatively thick oxide film. Is taken.

However, when the gate process and the oxide film thickness process of the MOSFET become complicated as described above, the manufacturing process of the dynamic RAM becomes complicated and causes an increase in cost. Therefore, in the conventional dynamic RAM, apart from the inevitable two types of gate oxide film thickness processes, the MOSFETs of all the blocks including the P-channel MOSFET are unified with n ⁺ gates, and the manufacturing process including the gate process is simplified. A method is adopted for achieving this. In order to support this, in the address selection MOSFET of the memory cell, return implantation to the channel is performed to increase the threshold voltage,
In the P-channel MOSFET serving as the n ⁺ gate, a P-type impurity is implanted at a predetermined depth of the channel for threshold voltage control, and charge transfer is performed by a so-called buried channel.

However, miniaturization of dynamic RAMs
As the voltage is further reduced, the address selection MOSF of the memory cell in which the threshold voltage is controlled by the return implantation is performed.
In ET, the electric field at the junction becomes too strong, the junction leakage increases, and the refresh characteristics of the dynamic RAM deteriorate. In addition, in an n ⁺ -gate P-channel MOSFET in which charge transfer is performed by a buried channel, a sufficient source / drain current cannot be secured because the width of the channel in the depth direction is narrow, and the operation of the MOSFET becomes slow. However, speeding up of a dynamic RAM is restricted.

An object of the present invention is to increase the threshold voltage of an address selection MOSFET without increasing junction leakage, and optimize the gate type and oxide film thickness of MOSFETs constituting each part according to the intended use. It is an object of the present invention to achieve high speed and low power consumption of a dynamic RAM or the like including the above.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0012]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, a dynamic RA including a memory array in which dynamic memory cells including an information storage capacitor and an address selection MOSFET are arranged in a lattice, and a peripheral circuit having a CMOS circuit as a basic element.
M, etc., the address selection MOSFET of the memory cell
Has a p ⁺ gate of a conductivity type different from that of the diffusion layer,
N-channel MOSFET having relatively thick oxide film
And a peripheral circuit such as a sense amplifier mainly using an internal voltage having a smaller absolute value than the external power supply voltage as a main operation power supply, and has a p ⁺ gate and an n ⁺ gate of the same conductivity type as the diffusion layer, respectively. It is composed of P-channel and N-channel MOSFETs having a relatively thin oxide film. In addition, for example, the input stage and the output stage of a data input / output circuit using an external power supply voltage as a main operation power supply have a p ⁺ gate and an n ⁺ gate of the same conductivity type as the diffusion layer, respectively, and have a relatively thick oxide. It is composed of P-channel and N-channel MOSFETs having a film.

According to the above means, a dynamic RAM
Since the gate type and oxide film thickness of the MOSFET constituting each part can be optimized according to the application,
Without increasing the junction leakage, the address selection M
The threshold voltage of the OSFET can be increased to improve the refresh characteristics of the memory cell and thus the dynamic RAM and the like. The source voltage of the P-channel and N-channel MOSFETs constituting each peripheral circuit can be reduced while preventing the breakdown voltage of a predetermined MOSFET. -The operation can be speeded up by sufficiently securing the drain current, whereby the speed and power consumption of a dynamic RAM or the like can be further reduced.

[0014]

FIG. 1 is a block diagram showing one embodiment of a dynamic RAM (semiconductor integrated circuit device) to which the present invention is applied. First, an outline of the configuration and operation of the dynamic RAM according to this embodiment will be described with reference to FIG. The circuit elements constituting each block in FIG. 1 are formed on a single semiconductor substrate surface such as single crystal silicon by a known MOSFET integrated circuit manufacturing technique.

Referring to FIG. 1, the dynamic RAM of this embodiment has a memory array MARY arranged so as to occupy most of the surface of a semiconductor substrate as its basic component. Memory array MARY includes a predetermined number of word lines arranged in parallel in the vertical direction in the figure, and a predetermined number of sets of complementary bit lines arranged in parallel in the horizontal direction. At the intersections of these word lines and complementary bit lines, a large number of dynamic memory cells composed of information storage capacitors and address selection MOSFETs are arranged in a grid. Note that the memory array M
The specific configuration of the ARY will be described later in detail.

The word lines forming the memory array MARY are connected to an X address decoder XD at the bottom of the figure, and are alternatively set to a predetermined selection level. The X address decoder XD is supplied with i + 1-bit internal X address signals X0 to Xi from the X address buffer XB, an internal control signal XG from the timing generation circuit TG, and a word line from the internal voltage generation circuit VG. An internal voltage VPP (second internal voltage) serving as a selection voltage is supplied. Also, the X address buffer XB receives i from an external access device via address input terminals A0 to Ai.
An + 1-bit X address signal is supplied in a time-division manner, and an internal control signal XL is supplied from a timing generation circuit TG. Note that the internal voltage VPP serving as the word line selection voltage is:
For example, a positive potential having a relatively large absolute value such as +3.5 V is used.

The X address buffer XB captures and holds the X address signal supplied via the address input terminals A0 to Ai according to the internal control signal XL.
Based on these X address signals, internal address signals X0 to Xi composed of non-inverted and inverted signals are formed and supplied to an X address decoder XD. The X address decoder XD is selectively activated by receiving the high level of the internal control signal XG, and the X address buffer XD
The internal X address signals X0 to Xi supplied from B are decoded, and the corresponding word lines of the memory array MARY are alternatively set to a selection level such as the internal voltage VPP.

Next, the complementary bit lines constituting the memory array MARY are coupled to a sense amplifier SA on the left side of the figure, and the complementary common data lines CD0 * to CDj are selectively connected by j + 1 pairs via the sense amplifier SA. *(here,
For example, the non-inverting common data line CD0T and the inverting common data line CD0B are indicated by asterisks like a complementary common data line CD0 *. In addition, a so-called non-inverted signal or the like which is selectively set to a high level when it is made valid is represented by adding a T to the end of its name, and a so-called low level is selectively set to a low level when it is made valid. Inverted signals and the like are indicated by adding a B to the end of their names. The same applies hereinafter).

The sense amplifier SA is supplied with a bit line selection signal of a predetermined bit (not shown) from the Y address decoder YD, and a sense amplifier drive control signal PA and a precharge control signal PC (not shown) from the timing generation circuit TG. . Also, the Y address decoder YD supplies the i + 1 bit internal Y from the Y address buffer YB.
Address signals Y0 to Yi are supplied, and an internal control signal YG is supplied from a timing generation circuit TG. The Y address buffer YB is supplied with an i + 1-bit Y address signal from an external access device via address input terminals A0 to Ai in a time-division manner, and is supplied with an internal control signal YL from a timing generation circuit TG.

The Y address buffer YB takes in and holds the Y address signal supplied via the address input terminals A0 to Ai according to the internal control signal YL.
Based on these Y address signals, internal address signals Y0 to Yi composed of non-inverted and inverted signals are formed and supplied to a Y address decoder YD. Further, the Y address decoder YD selectively operates in response to the high level of the internal control signal YG, and the Y address buffer YD
The internal Y address signals Y0 to Yi supplied from B are decoded, and the corresponding bit of the bit line selection signal for the sense amplifier SA is selectively set to a high level.

The sense amplifier SA is connected to the memory array MAR
It includes a predetermined number of unit circuits provided corresponding to the respective complementary bit lines of Y. Each of these unit circuits includes a unit amplifier circuit formed by cross-coupled a pair of CMOS inverters and an N-channel -Line precharge circuit formed by serially / parallel-coupled three type precharge MOSFETs, and a pair of N-channel type switch MOSFETs.
T. Of these, the unit amplifier circuit of each unit circuit is selectively and simultaneously operated by the dynamic RAM being selected and the sense amplifier drive control signal PA being set to the high level, and the memory array MAR
A small read signal output from a predetermined number of memory cells coupled to the Y selected word line via the corresponding complementary bit line is amplified to be a high level or low level binary read signal.

On the other hand, the precharge MOSFETs constituting the bit line precharge circuit of each unit circuit are turned on all at once in response to the high level of the precharge control signal PC, and the corresponding complementary bit lines of the memory array MARY are turned off. The inversion and inversion signal lines are precharged to a predetermined intermediate potential. In addition, the switch MOSFET pair of each unit circuit receives j.
+1 sets are selectively turned on, and the memory array MA
RY is selectively connected between the corresponding j + 1 pairs of complementary bit lines and the complementary common data lines CD0 * to CDj *. The specific configuration and operation of the sense amplifier will be described later in detail.

The complementary common data lines CD0 * to CDj * are
The data input / output circuit IO is coupled to a corresponding unit circuit. The data input / output circuit IO is supplied with internal control signals WP and OC (not shown) from the timing generation circuit TG.

The data input / output circuit IO includes j + 1 unit circuits provided corresponding to the complementary common data lines CD0 * to CDj *. Each of these unit circuits includes a write amplifier, a main amplifier, and a data input buffer. And a data output buffer. Of these, the output terminals of the write amplifier and the input terminals of the main amplifier that constitute each unit circuit are connected to the corresponding complementary common data lines CD0 * to CD0.
j * are commonly connected. Also, the input terminals of the write amplifier of each unit circuit are respectively coupled to the output terminals of the corresponding data input buffers, and the output terminals of the main amplifier of each unit circuit are coupled to the input terminals of the corresponding data output buffers. The input terminals of the data input buffers and the output terminals of the data output buffers that constitute each unit circuit are commonly coupled to corresponding data input / output terminals D0 to Dj, respectively. The internal control signal WP is commonly supplied to the write amplifier of each unit circuit, and the internal control signal OC is commonly supplied to the data output buffer of each unit circuit.

The data input buffer of each unit circuit of the data input / output circuit IO has data input terminals D0 to D0 when the dynamic RAM is selected in the write mode.
The write data of j + 1 bits supplied via j is taken in and transmitted to the corresponding write amplifier.
At this time, the write amplifier of each unit circuit selectively operates in response to the high level of the internal control signal WP, and sets the write data transmitted from the corresponding data input buffer to a predetermined complementary write signal. Data is written from the common data lines CD0 * to CDj * to the (j + 1) memory cells in the selected state of the memory array MARY via the sense amplifier SA.

On the other hand, when the dynamic RAM is selected in the read mode, the main amplifier of each unit circuit of the data input / output circuit IO outputs complementary common data from the j + 1 memory cells in the selected state of the memory array MARY. The binary read signal output via lines CD0 * to CDj * is further amplified and transmitted to the corresponding data output buffer. At this time, the data output buffer of each unit circuit selectively operates in response to the high level of the internal control signal OC, and outputs these read data from the data input / output terminals D0 to Dj to an external access device.

The timing generation circuit TG generates various internal control signals and the like based on a row address strobe signal RASB, a column address strobe signal CASB, and a write enable signal WEB supplied as an activation control signal from an external access device. It is selectively formed and supplied to each part of the dynamic RAM.

The dynamic RAM is further supplied with an external power supply voltage VDD via a power supply voltage supply terminal VDD and a ground potential VSS via a ground potential supply terminal VSS.
Is supplied. In addition, the dynamic RAM further includes an external power supply voltage VDD and a ground potential VSS.
An internal voltage generation circuit VG for generating internal voltages VCL and VDL as first internal voltages and internal voltages HV and VPP is provided.

In this embodiment, the external power supply voltage VDD
Is not particularly limited, but its central potential is, for example, +3.
3 V, and a relatively large potential fluctuation of about ± 10% is allowed. The internal voltage VCL has a central potential lower than the external power supply voltage VDD, for example, +2.5 V, and is supplied to the X address decoder XD, the Y address decoder YD, and the like to be the main operating power supply. On the other hand, the internal voltage V
The DL has a central potential lower than the external power supply voltage VDD, for example, +1.8 V, and is supplied to the sense amplifier SA and the like to become a main operating power supply. Also, the internal voltage HV
Has a center potential of one half of the internal voltage VDL, that is, for example, +0.9 V, and becomes a precharge potential of a complementary bit line included in the memory array MARY. Internal voltage V
As described above, PP has a center potential whose external power supply voltage V
+ 3.5V, which is higher than DD, and the X address decoder X
D is supplied to a word line selection voltage.

FIG. 2 shows a board layout of an embodiment of the dynamic RAM of FIG. Based on the figure,
The outline of the substrate layout of the dynamic RAM according to this embodiment will be described. In the following description of the substrate arrangement, the positional relationship shown in FIG.

In FIG. 2, the memory array MARY constituting the dynamic RAM of this embodiment is not particularly limited, but is actually four pairs of memory arrays MARYL0.
And MARYR0, MARY1 and MARYR1, M
ARYL2 and ARYR2 and ARYL3 and ARYR3. Each pair of memory arrays has sense amplifiers SA0 to SA0 obtained by dividing the sense amplifier SA into four.
SA3 are symmetrically arranged to sandwich the corresponding one.

That is, a pair of memory arrays MARYL0 and MARYR0 are arranged at the upper left of the semiconductor substrate CHIP surface with the corresponding sense amplifier SA0 interposed therebetween, and a pair of memory arrays at the upper right portion with the corresponding sense amplifier SA1 interposed therebetween. Memory arrays MARYL1 and MARYR1 are arranged. In the lower left portion of the semiconductor substrate CHIP surface, a pair of memory arrays MARYL2 and MARYR2 are arranged with the corresponding sense amplifier SA2 interposed therebetween, and in the lower right portion, a pair of memory arrays MARYL3 with the corresponding sense amplifier SA3 interposed therebetween. And MARYR3 are arranged.

A vertically adjacent memory array MARYL
0 and MARYR0 and MARYL2 and MARYR2, along the center line on the side of the semiconductor substrate CHIP surface,
A part of an X address decoder XD and an X address buffer XB, which are peripheral circuits PC, are arranged in the memory array MAR.
YL1, MARYR1, MARY3, and MARYR
Between 3, another part of these peripheral circuits is arranged. In addition, the memory array MARYL0 adjacent in the horizontal direction is
And between MARYR0 and MARY1 and MARYR1, along a vertical center line of the semiconductor substrate CHIP surface, a Y address decoder YD, a Y address buffer YB, a data input / output circuit IO, and a timing generation circuit (not shown), which are also peripheral circuits PC. A part of TG etc. is arranged,
Memory arrays MARY2 and MARYR2 and MARY
Another part of these peripheral circuits is arranged between L3 and MARYR3.

FIG. 3 is a partial circuit diagram of one embodiment of the memory array and the sense amplifier included in the dynamic RAM of FIG. The specific configuration and operation of the memory array and the sense amplifier included in the dynamic RAM of this embodiment will be described with reference to FIG.
In FIG. 3, the MOSFET with an arrow on its channel (back gate) portion is a P-channel type, and is distinguished from an N-channel MOSFET without an arrow. In FIG. 3, the memory array MARY0
L and MARY0R, the memory array MA
RYL0 and MARYR0 to MARYL3 and MA
RYR3 will be described, and sense amplifier SA0 will be described using sense amplifier SA0.

In FIG. 3, the memory array MARY0L
Although not particularly limited, m + 1 word lines WL0 to WLm arranged in parallel in the vertical direction in the figure and n + 1 sets of complementary bit lines BL arranged in parallel in the horizontal direction in the figure
0 * to BLn *. The intersection of the word line and the complementary bit line is substantially (m + 1) × (n) composed of the information storage capacitor Cs and the address selection MOSFET Qa.
+1) dynamic memory cells are arranged in a lattice.

The information storage capacitor Cs of m + 1 memory cells arranged in the same column of the memory array MARY0L
Is connected to the corresponding address selection MOSFET Q
The common bit lines are alternately and commonly connected to the non-inverted or inverted signal lines of the complementary bit lines BL0 * to BLn * via a. Further, the address selection MOSFETs of n + 1 memory cells arranged in the same row of the memory array MARY0L
The gates of Qa are commonly coupled to corresponding word lines WL0 to WLm, respectively. The internal voltage HV is commonly supplied from the internal voltage generation circuit VG to the other electrode of the information storage capacitor Cs of the memory cell constituting the memory array MARY0L.

Similarly, the memory array MARY0R has (m + 1) word lines W arranged in parallel in the vertical direction in FIG.
R0 to WRm and n arranged in parallel with the horizontal direction in the drawing.
+1 sets of complementary bit lines BR0 * to BRn *. At the intersections of these word lines and complementary bit lines, dynamic memory cells each composed of an information storage capacitor Cs and an address selection MOSFET Qa are arranged in a lattice.

The information storage capacitor Cs of m + 1 memory cells arranged in the same column of the memory array MARY0R
Is connected to the corresponding address selection MOSFET Q
Through a, they are alternately and commonly connected to non-inverted or inverted signal lines of the complementary bit lines BR0 * to BRn * in a predetermined combination. Also, address selection MOSFETs of n + 1 memory cells arranged on the same row of the memory array MARY0R
The gates of Qa are commonly coupled to corresponding word lines WR0-WRm, respectively. The internal voltage HV is commonly supplied from the internal voltage generation circuit VG to the other electrode of the information storage capacitor Cs of the memory cell constituting the memory array MARY0R.

Next, the sense amplifier SA0 is connected to the complementary bit lines BL0 of the memory arrays MARYL0 and MARYR0.
* To BLn * and n + 1 unit circuits provided corresponding to BL0 * to BLn *. Each of these unit circuits is not particularly limited, but is a P-channel MOSFE.
TP2 and N-channel MOSFET N2 and P-channel MOSFET P3 and N-channel MOSFET N3
And a unit amplifier circuit formed by cross-coupled a pair of CMOS inverters comprising

The non-inverting input / output nodes S0T to SnT and the inverting input / output nodes S0B to SnB of the unit amplifier circuit of each unit circuit of the sense amplifier SA0 are arranged on the left side.
Complementary bit line BL0 * of memory array MARY0L via N-channel type shared MOSFETs N4 and N5
~ BLn *. On the right side, N
The memory array M is provided via channel type shared MOSFETs NB and NC (in this specification, serial numbers of MOSFETs exceeding 10 are represented by alphabets; the same applies hereinafter).
ARY0R are coupled to complementary bit lines BR0 * to BRn *. The shared control signal SHL is commonly supplied from the timing generation circuit TG to the gates of the shared MOSFETs N4 and N5, and the shared control signal SHR is commonly supplied to the gates of the shared MOSFETs NB and NC.

In this embodiment, the shared control signal S
HL and SHR are equal to the internal voltage VPP, for example, +3.
5 V is set to a high level, and the ground potential VSS, that is, 0 V, is set to a low level. Therefore, the shared MOSFET N
4 and N5 are selectively and simultaneously turned on in response to the high level of the shared control signal SHL, and are not affected by the threshold voltage.
0 complementary input / output nodes S0 * to Sn * of each unit amplifier circuit
And complementary bit lines BL0 *-of memory array MARY0L
BLn * is connected. In addition, shared MO
The SFETs NB and NC are selectively and simultaneously turned on in response to the high level of the shared control signal SHR,
The complementary input / output node S0 of each unit amplifier circuit of the sense amplifier SA0 is not affected by the threshold voltage.
* To Sn * and the complementary bit lines BR0 * to BRn * of the memory array MARY0R are connected.

P-channel MOSFETs P2 and P3 forming a unit amplifier circuit of each unit circuit of the sense amplifier SA0
Are commonly coupled to a common source line CSP, and N
The sources of the channel MOSFETs N2 and N3 are commonly coupled to a common source line CSN. Common source line CS
P is coupled to an internal voltage supply point VDL via a P-channel type drive MOSFET P1, and a common source line CSN
Are coupled to a ground potential supply point VSS via an N-channel drive MOSFET N1. Drive MOSFET N1
The sense amplifier drive control signal PA is supplied from the timing generation circuit TG to the gate of the drive MOSFET P1.
Is supplied with an inverted signal from the inverter V1. Internal voltage VD at internal voltage supply point VDL
L is set to a positive potential such as +1.8 V as described above.

As a result, the unit amplifier circuits constituting each unit circuit of the sense amplifier SA0 selectively and simultaneously operate when the sense amplifier drive control signal PA is set to the high level and the drive MOSFETs P1 and N1 are turned on. And the memory array MARY0L or MARY
The small read signal output from the (n + 1) memory cells coupled to the selected word line of 0R via the corresponding complementary bit lines BL0 * to BLn * or BR0 * to BRn * is amplified to raise the internal voltage VDL to high. It is a binary read signal having a low level and the ground potential VSS at a low level.

Between the non-inverting input / output nodes S0T to SnT of the unit amplifier circuit of each unit circuit of the sense amplifier SA0 and the corresponding inverting input / output nodes S0B to SnB, three N-channel precharge MOSFETs N6 to N6 are connected. There is provided a bit line precharge circuit in which N8 is connected in series / parallel. MOSF constituting each bit line precharge circuit
The gates of ETN6 to ETN have timing generation circuits TG
Supplies a precharge control signal PC in common from the
The internal voltage HV is supplied from the internal voltage generation circuit VG to the commonly coupled sources of the SFETs N7 and N8. As described above, the internal voltage HV is set to a half of the internal voltage VDL, that is, for example, +0.9 V, and the internal voltage VPP is set to, for example, +3.5 V.

As a result, the MOSFE constituting the bit line precharge circuit of each unit circuit of the sense amplifier SA0
TN6 to TN8 are selectively turned on when the precharge control signal PC is set to a high level like the internal voltage VPP, and the non-inverting input / output nodes S0 of each unit amplifier circuit are turned on.
Inverting input / output nodes S0B to SnB corresponding to T to SnT
Is short-circuited to a precharge potential such as the internal voltage HV.

Each unit circuit of the sense amplifier SA0 further includes complementary input / output nodes S0 * to Sn * of the unit amplifier circuit and complementary common data lines CD0 * to CDj * (CD in FIG. 3).
0 * only) and a pair of N-channel type switch MOSFETs N9 and NA provided between them. The gates of these switch MOSFETs N9 and NA are sequentially coupled in common j + 1 sets at a time, and the corresponding bits of the bit line selection signals YS0 to YSp are commonly supplied from the Y address decoder YD. Needless to say, the bit number p + 1 of the bit line selection signals YS0 to YSp has a relationship of p + 1 = (n + 1) / (j + 1) with respect to the number n + 1 of unit circuits of the sense amplifier SA0.

As a result, the switch MOSFETs N9 and NA of each unit circuit of the sense amplifier SA0 are selectively turned on j + 1 sets at a time when the corresponding bits of the bit line selection signals YS0 to YSp are set to the high level. The non-inverted and inverted input / output nodes of the corresponding j + 1 unit amplifier circuits of the amplifier SA0 and the complementary common data line CD0
* To CDj * are selectively connected.

In this embodiment, the memory array MAR
As will be described later, the address selection MOSFET Qa constituting each of the memory cells Y0L and MARY0R is an N-channel MOSFET having a p ⁺ gate of a conductivity type different from that of the diffusion layer and having a relatively thick oxide film.
Further, shared MOSFETs N4 and N5 and NB and NC constituting each unit circuit of the sense amplifier SA0.
And the precharge MOSFETs N6 to N8 constituting the bit line precharge circuit, the shared control signals SHL and SHR supplied to their gates and the precharge control signal PC are at the high level of the internal voltage VPP. N-channel MOSF having n ⁺ gate of the same conductivity type as layer and relatively thick oxide film
Other MOSFETs are P-channel or N-channel MOSFETs having n ⁺ gates or p ⁺ gates of the same conductivity type as the diffusion layers, respectively, and having a relatively thin oxide film. MOSF constituting each part
The ET gate type, oxide film thickness, characteristics thereof, and the like will be described later in detail.

FIG. 4 is an explanatory diagram of one embodiment for explaining the proper use of gate type and oxide film thickness in the dynamic RAM of FIG. FIG. 5 is a partial sectional structural view of an embodiment of a memory array and a sense amplifier included in the dynamic RAM of FIG. 1, and FIG. 6 is a diagram of an embodiment of another peripheral circuit. A partial cross-sectional structural view is shown. Based on these figures, the proper use of the gate type and the oxide film thickness in the dynamic RAM of this embodiment, the device structure of the MOSFET constituting each part, and the characteristics thereof will be described.

In FIG. 4, a dual gate process is used in the dynamic RAM of this embodiment, and P-type or N-type impurities are implanted into a gate layer made of, for example, polysilicon in the MOSFET constituting each part of the dynamic RAM. Is selectively p ⁺ gate or n ⁺
It has a gate. Further, in the dynamic RAM of this embodiment, a two-type gate oxide film thickness process is used, and the MOSFET constituting each part is, for example, 6n.
An oxide film having a relatively large thickness such as m or an oxide film having a relatively small thickness such as 4 nm is provided.

In this embodiment, the memory array MAR
The address selection MOSFET Qa of the memory cell which constitutes Y and receives a word line selection voltage having a relatively large absolute value such as +3.5 V at its gate, that is, an internal voltage VPP,
As illustrated on the left side of FIG. 5, it is composed of an N-channel MOSFET (NMOS) having a p ⁺ gate of a conductivity type different from that of the diffusion layer and having a relatively thick oxide film.

A peripheral circuit using an external power supply voltage VDD having a relatively large absolute value such as +3.3 V or an internal voltage VPP such as +3.5 V as a main operating power supply, that is, an input buffer of a data input / output circuit IO , An output stage of an output buffer, an input stage receiving a start control signal of the timing generation circuit TG, an input stage receiving address signals A0 to Ai of an X address buffer XB and a Y address buffer YB, and an X address decoder XD The MOSFET forming the post-stage portion serving as the word line drive circuit of FIG.
As shown in FIG. 1, the P-channel MOSFET (PMOS) and the N-channel MOSFET each have a p ⁺ gate or an n ⁺ gate of the same conductivity type as the diffusion layer and have a relatively thick oxide film.

On the other hand, other peripheral circuits using an internal voltage VCL or VDL having a relatively small absolute value such as +2.5 V or +1.8 V as a main operating power supply, ie, a word line drive circuit of the X address decoder XD are excluded. General circuit, general circuit of Y address decoder YD, shared MOSFET and precharge MOS of sense amplifier SA
The MOSFETs constituting the general circuit excluding the portion related to the FET and the general circuit excluding the input stage of the data input / output circuit IO, the timing generation circuit TG, the X address buffer XB, and the Y address buffer YB are the sense amplifier on the right side of FIG. And as illustrated in FIG. 6, each has a p ⁺ gate or n ⁺ gate of the same conductivity type as the diffusion layer,
P-channel MOSFET having relatively thin oxide film
And an N-channel MOSFET. However, the shared MOSFET that constitutes each unit circuit of the sense amplifier SA
And only the precharge MOSFET, as described above,
Since the high level of the shared control signal and the precharge control signal supplied to the gate is the internal voltage VPP, an N ⁺ gate having the same conductivity type as the diffusion layer and having a relatively thick oxide film It consists of a channel MOSFET.

As is well known, P-channel and N-channel MOSFETs having a relatively thin oxide film have a relatively low withstand voltage, but have a relatively large gate capacitance, so that a relatively large source / drain current cannot be obtained. And can operate at high speed even when the operating power supply is lowered. Further, the P-channel and N-channel MOSFETs having relatively thick oxide films have slightly smaller gate capacitances, but have relatively higher withstand voltages, and serve as interface circuits for buffers and X-address decoders to which the internal voltage VPP is applied. And a memory cell to which a word line driving voltage is applied.

On the other hand, the N-channel MOSFET having a P-channel MOSFET and an n ⁺ gate having a p ⁺ gate of the same conductivity type as the diffusion layer, its threshold voltage to charge transferred through the surface channel is performed It is relatively small and can operate at a relatively high speed. N channel M having ap ⁺ gate of a conductivity type different from that of the diffusion layer
OSFET, ie, memory cell address selection MOSF
In the ET, the threshold voltage can be increased without performing return implantation, and by not performing return implantation, the electric field strength at the junction is reduced, junction leakage is reduced, and the dynamic type is reduced. The refresh characteristics of the RAM can be improved.

For these reasons, in the dynamic RAM of this embodiment, although the manufacturing process is slightly complicated, the gate type and the oxide film thickness of the MOSFET constituting each part are optimized according to the application. As a result,
The source and drain currents of the P-channel and N-channel MOSFETs constituting each peripheral circuit are sufficiently secured while preventing the breakdown of the predetermined MOSFET, and the operation thereof is sped up to further increase the speed and lower the speed of the dynamic RAM. Power consumption can be reduced.

The operation and effect obtained from the above embodiment are as follows. (1) Information storage capacitor and address selection MOSFE
In a dynamic RAM or the like having a memory array in which dynamic memory cells including T are arranged in a lattice and a peripheral circuit having a CMOS circuit as a basic element, an address selection MOSFET of the memory cell is connected to a conductive layer different from its diffusion layer. has a type p ⁺ gate, and with constituting a N-channel MOSFET having a relatively thick oxide film, a peripheral circuit such as a sense amplifier for the main operating power supply a small internal voltage of the absolute value of, for example, an external power supply voltage,
It is composed of a P-channel MOSFET and an N-channel MOSFET each having ap ⁺ gate and an n ⁺ gate of the same conductivity type as the diffusion layer and having a relatively thin oxide film. In addition, for example, peripheral circuits such as an input buffer and an output buffer, which use an external power supply voltage as a main operating power supply, have p ⁺ gates and n ⁺ gates of the same conductivity type as the diffusion layers, and a relatively thick oxide film. Having P-channel M
By using an OSFET and an N-channel MOSFET, an MO that constitutes each unit such as a dynamic RAM is provided.
The effect is obtained that the gate type and oxide film thickness of the SFET can be optimized according to the application.

(2) According to the above item (1), there is an effect that the threshold voltage of the address selection MOSFET can be increased without increasing the junction leakage, and the refresh characteristics of the memory cell and, consequently, the dynamic RAM can be improved. can get. (3) According to the above item (1), the source / drain currents of the P-channel and N-channel MOSFETs constituting each peripheral circuit can be sufficiently ensured while the breakdown voltage of the predetermined MOSFET is prevented, and the operation can be speeded up. The effect is obtained. (4) According to the above items (1) to (3), there is obtained an effect that a higher speed and lower power consumption of a dynamic RAM or the like can be achieved.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the above embodiment, and various modifications can be made without departing from the gist of the invention. Needless to say, there is. For example, in FIG. 1, the memory array MARY of the dynamic RAM can be divided into an arbitrary number of memory mats or sub memory arrays including its direct peripheral circuits. In addition, the dynamic RAM does not require the use of the shared sense method or the address multiplex method. Furthermore, the block configuration of the dynamic RAM can take various embodiments, and the names and effective levels of the activation control signal and the internal control signal, the power supply voltage and the polarity and absolute value of each internal voltage, etc. of the present invention are also included in the present invention. Has no effect on the gist.

In FIG. 2, the number of divisions of the memory array MARY and its peripheral circuits can be set arbitrarily. In addition, the specific shape of the semiconductor substrate CHIP, the arrangement position of each part, and the like are not limited to the present embodiment, and can take various embodiments.

In FIG. 3, memory array MARY0L
And MARY0R may include an arbitrary number of redundant elements, and may employ a so-called hierarchical word line system or hierarchical bit line system. The specific configuration and the like of the sense amplifier SA0 and each unit circuit thereof can take various embodiments without being limited to the present embodiment.

In FIG. 4, the combination of the MOSFET gate type and the oxide film thickness is merely an example, and can be set arbitrarily according to the operating power supply of each circuit and its use.
In FIGS. 5 and 6, the type of wiring layer used for forming each part, the number of metal wiring layers, the specific shape and combination, and the like can take various embodiments.

In the above description, the case where the invention made by the present inventor is mainly applied to the dynamic RAM, which is the field of application as the background, has been described.
The present invention is not limited to this, and can be applied to, for example, various memory integrated circuit devices such as a synchronous DRAM having a dynamic RAM as a basic configuration, and a single-chip microcomputer equipped with such a memory integrated circuit device. The present invention provides at least an address selection M
The present invention can be widely applied to a semiconductor memory device including a memory array in which memory cells including OSFETs are arranged in a lattice and a peripheral circuit, and a device or system including such a semiconductor memory device.

[0064]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, a dynamic type R including a memory array in which dynamic type memory cells including an information storage capacitor and an address selection MOSFET are arranged in a lattice, and a peripheral circuit having a CMOS circuit as a basic element.
In an AM or the like, the address selection MOSFET is formed of an N-channel MOSFET having a p ⁺ gate of a conductivity type different from that of the diffusion layer and having a relatively thick oxide film, and for example, having an absolute value smaller than the external power supply voltage. A peripheral circuit such as a sense amplifier using an internal voltage as a main operating power supply is connected to ap ⁺ gate and n ^{+ of the} same conductivity type as the diffusion layer.
It is composed of P-channel and N-channel MOSFETs each having a gate and a relatively thin oxide film. In addition, for example, peripheral circuits such as an input buffer and an output buffer, which use an external power supply voltage as a main operating power supply, have p ⁺ gates and n ⁺ gates of the same conductivity type as the diffusion layers, and a relatively thick oxide film. It has P-channel and N-channel MOSFETs.

This makes it possible to optimize the gate type and oxide film thickness of the MOSFETs constituting each part of the dynamic RAM or the like according to the intended use.
By increasing the threshold voltage of the ET, the refresh characteristics of the memory cell and thus the dynamic RAM and the like can be improved, and the P-channel and N-channel transistors constituting each peripheral circuit can be prevented while preventing the breakdown voltage of a predetermined MOSFET.
Ensure sufficient source / drain current of OSFET,
The speed of the operation can be increased, whereby the speed and power consumption of a dynamic RAM or the like can be further reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a dynamic RAM to which the present invention is applied.

FIG. 2 is a board layout diagram showing one embodiment of a dynamic RAM of FIG. 1;

FIG. 3 is a partial circuit diagram showing one embodiment of a memory array and a sense amplifier included in the dynamic RAM of FIG. 1;

FIG. 4 is an explanatory diagram showing an embodiment for explaining proper use of gate types and oxide film thicknesses in the dynamic RAM of FIG. 1;

FIG. 5 is a partial sectional structural view showing one embodiment of a memory array and a sense amplifier included in the dynamic RAM of FIG. 1;

FIG. 6 is a partial cross-sectional structural diagram showing one embodiment of another peripheral circuit included in the dynamic RAM of FIG. 1;

[Explanation of symbols]

MARY ... memory array, XD ... X address decoder, XB ... X address buffer, SA ... sense amplifier, YD ... Y address decoder, YB ... Y address buffer, IO ... data input / output circuit, TG ... ... Timing generation circuit, VG ... Internal voltage generation circuit, D0 to Dj
...... Input / output data or its input / output terminal, RASB ... Row address strobe signal or its input terminal, CASB
..... column address strobe signal or its input terminal,
WEB: Write enable signal or its input terminal, A
0 to Ai ... address signal or its input terminal, VDD ...
... Power supply voltage or its input terminal, VSS... Ground potential or its input terminal. CHIP: Semiconductor substrate (chip), M
ARYL0 and MARYR0 to MARYL3 and M
ARYR3: Memory array, PC: Peripheral circuit, SA
0 to SA3 Sense amplifier. WL0-WLm, WR0
To WRm ... word line, BL0 * to BLn *, BR0 *
... BRn * ... complementary bit line, Cs ... information storage capacitor, Qa ... address selection MOSFET, S0 * -S
n *: complementary input / output node of each unit amplifier circuit of the sense amplifier, CSP, CSN: common source line, CD0 * to
CDj *: complementary common data line, YS0 to YSp: bit line selection signal, SHL, SHR, shared control signal, PC, precharge control signal, PA: sense amplifier drive control signal, P1 to P3 P-channel MOSF
ET, N1 to NC ... N-channel MOSFET, V1 ...
... Inverter, HV ... Internal voltage (intermediate voltage). M1
M3... First to third layer metal wiring, PMOS... P
Channel MOSFET, NMOS ... N-channel MOS
FET.

 ────────────────────────────────────────────────── ─── Continuing from the front page (72) Atsushi Ogishima, Inventor 5-2-1, Kamimizuhoncho, Kodaira-shi, Tokyo F-term in Hitachi Semiconductor Group 5B024 AA01 AA13 BA07 BA10 BA17 BA29 CA16 CA27 5F048 AB01 AB06 AB07 AB08 AC03 AC10 BA01 BB06 BB07 BB16 5F083 AD42 GA01 GA05 LA03 LA04 LA05 LA06 LA09 LA10 LA30 PR42 PR52 ZA05 ZA07

Claims (5)

[Claims] 1. A memory array in which a dynamic memory cell including an N-channel type address selection MOSFET having a p ⁺ gate implanted with a P-type impurity and having a relatively thick oxide film is arranged in a lattice, having the p ⁺ gate, and relatively thin and P-channel MOSFET having an oxide film, has a n ⁺ gate n-type impurity is implanted, and the basic elements and an n-channel MOSFET having a relatively thin oxide film And a first peripheral circuit. 2. The P-channel MOS transistor according to claim 1, wherein said semiconductor memory device further comprises said p ⁺ gate and a relatively thick oxide film.
A semiconductor memory device comprising: a second peripheral circuit having ET and an N-channel MOSFET having an n ⁺ gate and a relatively thick oxide film as basic elements. 3. The semiconductor memory device according to claim 1, further comprising: a first internal voltage having an absolute value smaller than the external power supply voltage based on the external power supply voltage; An internal voltage generating circuit for generating a second internal voltage having an absolute value larger than the first internal voltage, wherein the first peripheral circuit uses the first internal voltage as a main operating power supply, A peripheral circuit using the external power supply voltage or the second internal voltage as a main operation power supply. 4. The device according to claim 3, wherein the second peripheral circuit includes a part relating to a shared MOSFET and a precharge MOSFET of a sense amplifier, a part relating to a word line driving circuit of an X address decoder, a data input / output circuit, A timing generator, an X address buffer, and a part relating to an input stage buffer of a Y address buffer. The first peripheral circuit includes a part excluding the part of the sense amplifier, and an X address decoder. And a Y address decoder, a data input / output circuit, a timing generation circuit, an X address buffer, and a part excluding the above part of the Y address buffer. . 5. The semiconductor memory device according to claim 1, wherein the semiconductor memory device is a dynamic RAM, and in a predetermined manufacturing process thereof, a dual gate process and a two-gate oxidation method are used. A semiconductor memory device characterized by using a film thickness process.