JP2001093993A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve operation speed with small power consumption, avoiding the problem of leakage current at standby due to a sub-threshold current in a static memory that is operated with a low voltage of approximately 1 V power supply voltage and further securing the voltage margin of the memory cell of a static memory that decreases due to the drop of the power supply voltage. SOLUTION: In a static memory cell, that is made of a MOS transistor with a relatively high threshold voltage crossed and connected, a MOS transistor for controlling the power feeder line voltage is provided. The power feeder voltage control transistor is turned on, after the word line voltage is turned off for feeding a high voltage VCH to a feeder line, so that the voltage difference between two storage nodes in a memory cell in a unselected state becomes larger than the voltage difference between the two nodes, when a voltage corresponding to write information is written to the two nodes in the selected memory cell from data paired lines DL and /DL.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit which operates at a low voltage, in particular, a semiconductor integrated circuit in which a static memory cell constituted by a MIS transistor or a MOS transistor (hereinafter simply abbreviated as MOS or MOS transistor) is used as a memory cell. The present invention relates to a circuit, and more particularly to a circuit suitable for high speed and low power of a static memory (static random access memory).

[0002]

2. Description of the Related Art A MOS transistor, which is a kind of a field effect transistor having a gate insulating film, has a lower operating voltage since its breakdown voltage decreases as the device is miniaturized. Even in this case, in order to maintain high-speed operation, it is necessary to lower the threshold voltage (VT) of the MOS transistor in accordance with the lowering of the operating voltage. The operating speed is governed by the effective gate voltage of the MOS transistor, that is, the value obtained by subtracting VT from the operating voltage, and the higher the value, the higher the operating speed. But generally VT is 0.4V
Below this level, as is well known, a DC current called a subthreshold current, which increases exponentially with a decrease in VT, flows through the MOS transistor which should be cut off. Therefore, a semiconductor integrated circuit composed of a large number of MOS transistors has a CMO
Even in the case of the S circuit, the DC current increases significantly. Therefore, a high-speed, low-power, low-voltage operation will be an essential problem in future semiconductor devices. That is, a sub-threshold current is generated, and a large DC current is generated in the entire chip. Therefore, the VT of the transistors in the memory cell, especially the cross-coupled transistors,
Cannot be less than about 0.4V. However, in that case, the effective gate voltage becomes lower as the operating voltage decreases. For this reason, the operating margin (margin) of the memory cell is narrowed, the operating speed is reduced, or the memory cell is susceptible to VT manufacturing variations.

FIG. 2 shows a conventional memory cell and a waveform diagram to further explain the above-mentioned problems.

A CMOS static memory (SRAM) is taken as an example of a memory cell.

First, when a memory cell is in a non-selected state, that is, when the word line WL is at a low level such as 0V, the storage node N2 in the cell is at a high level such as 1V equal to the power supply voltage VCC, and the other storage nodes N1 are at 0V. Consider a case where such low-level information is stored. Conventionally, the VT of all the transistors of the memory cell is 0.4
Since the voltage is V or more, both the N-channel MOS transistor QS2 and the P-channel MOS transistor QC1 are non-conductive. This is because the voltage between the gate and the source is 0 V in QS2 and QC1. Therefore, the current flowing through VCC is negligible. This is why SRAMs have low power. The voltage margin of this memory cell becomes smaller as VCC-VT becomes smaller. Therefore, VT must be lowered as VCC is lowered.
When the voltage drops below V, a subthreshold current starts to flow through the two transistors QS2 and QC1, which should be non-conductive, and increases exponentially with a decrease in VT. In general, VT varies due to variations in the manufacturing process, and the subthreshold current increases as the temperature rises. Therefore, considering the VT variation and the rise in junction temperature, this current is further increased under the worst conditions. Since this current flows through all the memory cells in the chip, a total current of about 10 mA or more may flow even in an SRAM of about 128 K bits. This current is also a data holding current of the entire cell array. The data holding current of a normal SRAM using a MOS transistor whose threshold voltage is relatively large so that a subthreshold current does not substantially occur is 10 μm.
This is a major problem, considering that it can be less than A. Therefore, VT must be set to a relatively large value such as about 0.4 V or more in terms of current. Here, let us consider a case where VCC is lowered while VT is fixed at 0.5 V, for example. The demand to lower VCC is MOS
In addition to the requirement for lowering the withstand voltage of the transistor, it comes from the requirement for lowering the power or the requirement for driving with one battery. For example, when the degree of miniaturization of a MOS transistor is 0.5 μm or less or the thickness of its gate insulating film is 6 nm or less, the external power supply voltage V
Even if CC is set to a low voltage of about 1.5 to 1.0 V, the transistor operates at a sufficiently high speed. Therefore, VCC can be reduced to this level with priority given to low power. However, when VCC is lowered, the voltage margin of the memory cell is significantly reduced. That is, the effective gate voltage of the conduction transistor QS1 is VCC-VT, and when VCC approaches VT, the effective gate voltage decreases and the rate of variation with respect to variation in VT increases. Also, the well-known soft error resistance is reduced, and a margin for equivalent noise such as a threshold voltage difference (so-called offset voltage) between cross-coupled pair transistors (QS1 and QS2, QC1 and QC2) in the memory cell is also reduced. descend.

[0006] Even when a memory cell is selected, VT is set at 0.
If it is as high as 5 V and VCC is low, the speed becomes low or the operation margin is reduced. When VCC of, for example, 1 V is applied to the word line WL, QT1 and QS1 become conductive, and a minute voltage change is applied to DL by a current flowing therethrough and a load resistor (actually constituted by a MOS transistor) connected to the data line DL. (0.2
V) appears. On the other hand, QS2 is non-conductive because its gate voltage is sufficiently lower than VT, so that the other data line / D
No voltage change appears at L. The information stored in the memory cell is discriminated based on the voltage polarity between the data pair lines, and reading is performed. Here, the larger the voltage change that appears in DL, the more stable the discrimination. For this purpose, it is necessary that a current as large and constant as possible flows through QS1 and QT1. Since the effective gate voltages of QS1 and QT1 are almost equal to VCC-VT, the current decreases as VCC decreases, and the current is strongly affected by VT variations.

[0007] From the above, in the conventional circuit and driving method, VCC
The DC current increases remarkably, the operating speed of the memory cell decreases or fluctuates, or the operating margin decreases with the decrease in the operating current. Therefore, the performance of an SRAM chip or a microprocessor chip having a built-in SRAM, for example, is significantly deteriorated as VCC decreases.

[0008]

SUMMARY OF THE INVENTION An object of the present invention is to provide a static memory or a semiconductor device having a built-in static memory, such as an increase in sub-threshold current and a voltage margin associated with a low voltage operation of a static memory cell composed of MOS transistors. It is to suppress the decrease.

[0009]

SUMMARY OF THE INVENTION The object of the present invention is to provide a static memory cell in which MOS transistors are cross-coupled such that substantially no current flows between the drain and the source even when the voltages at the gate and the source are equal. The voltage difference between two storage nodes in a memory cell in a non-selected state is equal to the voltage when the memory cell is selected and a voltage corresponding to write information is applied to the storage node of the memory cell from the data pair line. This is realized by controlling the voltage of at least one power supply line of the memory cell so as to be larger than the voltage difference between the two storage nodes. This allows
Even if the main power supply voltage at the time of selecting the memory cell is low, the voltage between the two storage nodes in the memory cell can be sufficiently high, so that the memory cell can operate stably with low power, with a wide operation margin.

[0010]

Embodiments of the present invention will be described below with reference to the drawings.

FIGS. 1A to 1C show an embodiment of the present invention. FIG. 1A shows an example in which a transistor QP as means for controlling the connection between the operating potential point VCH of the circuit and the memory cell is added for each cell, FIG. 1B shows an example in which QP is added for each row, c) shows an example in which QP is shared by all cells.

For simplicity, the threshold voltage VT of all transistors in the memory cell is set to 0.5V. Therefore, if the gate and source voltages are approximately equal, no subthreshold current flows through the transistor. FIG. 1A is a conceptual diagram of the present invention which is the most basic. P-channel MOS QC1, which is a power supply node on the high potential side of the memory cell MC,
A P-channel MOS QP acting as a switch is inserted between the common source of QC2 and the power supply VCH with respect to the memory cell. N, which is a power supply node on the low potential side of the memory cell MC
The common source of the channel MOSs QS1 and QS2 is the reference potential V
It is connected to SS (normally ground potential 0 V). The memory cell MC exemplified here is a static memory cell including a MOS transistor whose gate and drain are cross-coupled to each other. More specifically, there are an inverter composed of QC1 and QS1, and an inverter composed of QC2 and QS2. The storage cell in which the output of one inverter is connected to the input of the other inverter, and the storage nodes N1 and N2
And transfer MOS transistors QT1 and QT2, one ends of which are connected respectively. The operating environment of the memory cell MC is such that a power supply having a sufficiently high current supply capability of a voltage VCC supplied from the outside is provided, and VCH having a voltage higher than VCC is provided.
Is assumed to be a power supply having a low current supply capability. In a power supply having a low current supply capability, there is a problem that the voltage of the power supply temporarily drops when a current exceeding the supply capability flows.

When writing data to a memory cell from a data pair line, VCC is normally applied to one of the pair lines and 0 is applied to the other while QP is off. At this time, assuming that the word line voltage is VCC, one of the storage nodes N1 and N2 is VCC-VT reduced by VT of QT1 or QT2.
, And 0 is input to the other. However, in this state, the storage voltage (difference voltage between nodes N1 and N2) becomes VCC-VT. For example, 0.5V when VCC = 1V and VT = 0.5V.
And too low. Therefore, after writing, that is, after turning off the word line voltage, QP is turned on, and a sufficiently high VCH (for example, 2 V) is applied to the common source. Then, the cross-coupled transistor in the memory cell is activated to function as a differential amplifier, and as a result, one of N1 and N2 is charged to VCH and the other becomes 0. Eventually, the storage voltage will increase from VCC-VT to VCH. The timing at which QP is turned on does not have to coincide with the word line selection timing. However, in order to prevent unnecessary current from flowing from the power supply VCH having a weak current supply capability to the data lines DL and / DL via the memory cells. It is desirable that the timing be after the word line voltage is turned off. Note that the node N during the period from turning off the word line to turning on the QP is described.
The write data of N1 and N2 is held by the parasitic capacitance of each of the nodes N1 and N2. As described above, if QP is turned on and VCH is continuously supplied to the memory cell during the data holding period or standby after the memory cell is activated, the operation margin of the memory cell during this period is expanded. The operation is fast and stable even when reading data from a memory cell. This is because the current driving capability of QS1 or QS2 is improved by an increase in the gate voltage. As described above, writing can be performed while QP is in a non-conducting state, so that any write data becomes a dynamic operation in the memory cell and high-speed writing can be performed with low power. If VCH is directly connected to the memory cell without QP, or if QP is turned on during writing, in the case of writing that inverts the stored information stored up to that point,
Inconveniences such as a high current flowing through QP for a long time and high power or difficulty in inversion are caused.

FIG. 1B shows an embodiment in which QP is shared by a plurality of memory cells, and the memory cell becomes smaller as the number of transistors decreases. Now, as mentioned above, MCP
If data is written while 1 is non-conductive, M
For example, 0 is applied to the gate of QC1, and VC is applied to the gate of QC2.
C-VT (0.5 V) is forcibly applied. Therefore Q
C1 becomes conductive, and VCH, which has charged the parasitic capacitance of the common power supply line PL1, until then, discharges to VCC-VT. At this time, the memory cell MC2 on the same word line WL1 is substantially performing a read operation, but the memory cell MC2 on the same word line WL1 loses MC2 due to the aforementioned voltage drop of PL1.
Is not destroyed. The storage voltage of MC2 only drops from VCH up to that point to VCC-VT which is the voltage of PL1. The sensitivity of the differential amplifier in the memory cell is determined by, for example, the offset voltage of a paired transistor, which is, for example, about 0.2 V or less. Since VCC-VT is higher than this sensitivity, no information is destroyed. That is, if QP1 is turned on after the end of writing and VCH is again supplied to PL1, the storage voltage of MC2 also becomes VCH similarly to MC1. In this embodiment, only one power supply line corresponding to the selected word line needs to be charged to VCH. Many other feeders (P
L2, etc.) remain at VCH, so that the charging operation does not occur even if the corresponding charging transistor (QP2) is turned on. That is, the charging of the power supply line is localized, and the power consumption is reduced.

FIG. 1C shows an embodiment in which the charging transistor QP is shared by all the memory cells, and the degree of integration is higher than that of the above-described example. However, in this case, the voltages of all the power supply lines including the power supply lines of the memory cells on the non-selected word line side drop, so that the charge / discharge power for charging them to VCH increases or the speed decreases. Care must be taken because of the possibility of It should be noted that the area of the memory cell can be reduced by making the power supply line adjacent to the word line common. For example, in the first case (b), if PL1 and PL2 are formed as one common power supply line and controlled by one transistor, the number of wirings of the memory cell is effectively reduced.

A circuit configuration in which a switch MOS transistor is provided at a power supply node on the high potential side of an SRAM memory cell is disclosed in Japanese Patent Application Laid-Open Nos.
As described in Japanese Patent No. 108297, the potential connected via the switch MOS is a power supply potential supplied to the device, and has a completely different idea from the present invention.

Hereinafter, a more specific embodiment will be described mainly with reference to FIG. 1B, including not only a write operation but also a read operation.

FIG. 3 is a circuit diagram of the embodiment of the present invention, FIG. 4 is a timing chart at the time of reading, and FIG. 5 is a timing chart at the time of writing.

Taking a flip-flop type cell including a P-channel MOS transistor and an N-channel MOS transistor as a memory cell as an example, the threshold voltages VT of all the transistors in the cell are high enough to make the subthreshold current almost negligible. , For example, 0.5V. For the sake of simplicity, we will take a 4-bit cell array,
VCC = Single power supply of SRAM and VCC =
It is assumed that 1V and VCH = 2V. The features of the present invention are as follows: (1) The voltage of the cell power supply lines (PL1 and PL2) is switched according to the operation timing of the cell. That is, the information holding voltage (2 V in FIG. 3) when the cell is not selected is determined by the voltage applied from the power supply line of the cell, and its magnitude is larger than the write voltage written from the data line to the cell when the cell is selected. Thus, the voltage of the feed line of the cell is controlled.

(2) Data lines (DL1, / DL1, DL
2, / DL2) is a substantially intermediate voltage (VCC / 2 = 0.5 V) of the maximum voltage that can be taken by the data line (VCC = 1 V in FIG. 3).
Operate based on This reduces the charge / discharge power of the data line by half.

(3) The amplitude of the pulse voltage of the selected word line is larger than the maximum voltage of the data line. The threshold voltage VT of the selection transistor connected to the word line
In order to eliminate the influence of the above, the amplitude of the pulse voltage is set to a value (VCH) larger than the maximum voltage of the data line by VT or more by a booster circuit or the like in the chip. Further, the current driving capability of QT1 and QT2 is improved by the boosted amount, and the speed is increased.

Let us consider a case where the SRAM portion incorporated in a microprocessor chip or the like, or the SRAM chip itself (hereinafter, the SRAM collectively) is inactivated by the SRAM activation signal CE. The main part in the SRAM is in a precharge state by a precharge signal φP. For example, the power supply lines (PL1, PL2) of the cell are precharged to a voltage VCH sufficiently boosted inside the chip based on the external power supply voltage (VCC). A decrease in the storage voltage in the cell due to a small leak current in the cell is prevented by the compensation current from the P-MOSs QP1 and QP2, whereby the storage state of each cell is maintained. Here, VCH is formed by a voltage conversion circuit VC2. VC2 is formed by boosting VCC inside the chip using a charge pump circuit for driving a capacitor, and its current driving capability is correspondingly low. However, since the threshold voltage of the transistor in the cell is set sufficiently high at 0.5 V or more, a large capacity SR
Even in AM, the total leakage current of the cell can be sufficiently reduced to 10 μA or less at most. Therefore, a compensation current can be supplied from the VCH boosting circuit to all the memory cells. The details of the booster circuit are described in “Super LSI Memory (Baifukan, published in November 1994), page 315”. Regarding an on-chip booster circuit that operates on a very low voltage power supply VCC of about 1 V, which is a subject of the present application, see “1995 Symposium on VLSI Circuits Digestof Techi”.
ncal Papers, (1995), pp. 75-76 ". The threshold voltage of a MOS transistor used in the booster circuit of this document is about 0.6 V. If a MOS transistor with a lower threshold voltage is used, a booster circuit that can operate with a lower power supply voltage VCC can be obtained. it is conceivable that.
When using a transistor having a low threshold voltage, it is necessary to pay attention to the above-described sub-threshold current, but if the number of transistors is sufficient to form a booster circuit, the leakage current will not be practically endurable. It is possible to do so. A circuit configuration in which a booster circuit for generating a boosted voltage from an external power supply is connected to a power supply node on the high potential side of an SRAM memory cell is disclosed in
As described in Japanese Patent No. 223581, the potential of the booster circuit or an external power supply is connected to the power supply node.

During the precharge period inactivated by the SRAM activation signal CE, each of the data lines (DL1, / DL1, DL2, / DL2 (in this specification, the inverted signal which is a pair of complementary signals is / DL1) is precharged to VCC / 2 by the precharge circuit PC. By doing so, the voltage amplitude of the data line is reduced by half as compared with the conventional VCC precharge, so that the data line charge / discharge power which has conventionally been a problem when simultaneously writing multi-bit data can be reduced by half. In this case, the VCC / 2 power supply is formed by a voltage conversion circuit VC1 from VCC, and specifically, a circuit or the like described in FIG. 4.60 on page 324 of the "ultra LSI memory" can be used.

Since VCC / 2 is formed inside the chip, it generally has low load current driving capability. Therefore, at the time of precharge, one of the data pair lines is directly set to 0 by this VCC / 2 power supply.
When precharging from Vcc / 2 to Vcc / 2, a sufficient charging current cannot be supplied, so that the level of Vcc / 2 fluctuates. Since the number of data pairs is usually as large as 64 or 128 or more, this variation is a serious problem. Therefore, an amplifier AMP is provided for each data line. The function of the amplifier AMP is to amplify a small differential voltage appearing on the data pair line at the time of cell reading at a high speed up to VCC. As a result, one of the data pair lines becomes 0 and the other becomes VCC. In the next precharge operation, QEQ is turned on and the data pair lines are automatically balanced to VCC / 2. Therefore, it is not necessary to supply a large charging current from the VCC / 2 power supply. If the precharge period is long, it is sufficient that a small current can be supplied to suppress the level variation of the data pair line gradually due to the small leakage current.

Therefore, if AMP is used, a built-in VCC / 2 power supply circuit can be used.

Hereinafter, a case where data is read from a memory cell will be described with reference to FIG. The SRAM is activated by the SRAM enable signal CE. When a certain word line, for example, WL1 is selected and a pulse of VCH is applied to WL1, all the cells (MC1, MC2) on WL1 are activated. This word line selection signal pulse is formed by a row address decoder XDEC / driver DRV upon receiving a row address signal AX. If 0V and 2V (= VCH) are stored in the nodes N1 and N2 in the cell MC1, respectively, QT1 and QS1 conduct, so that the data line DL1 gradually discharges toward 0V. On the other hand, since the gate voltages of QS2 and QC2 are almost 0, a current flows through QC2 and QT2, and the data line DL1 slightly rises from 0.5V (= VCC / 2). Since it takes time for the minute differential voltage appearing on the data pair line to be sufficiently large, the amplifier AM
A pulse is applied to the drive lines SP and SN of the P and the data lines DL
1, and / DL1 are rapidly amplified to 0 and 1V, respectively. A
Since MP does not determine the degree of integration or subthreshold current of SRAM as much as the cell, the size of the transistor in the AMP can be selected larger than that in the cell, and the threshold voltage can be as low as about 0.2 V, so high-speed amplification can be achieved. Is possible. Further, the AMP is activated when a memory cell is selected by the amplifier driving circuit SPG, and in the non-operation state (standby state), the drive lines SP and SN are kept at the same potential, so that a subthreshold current becomes a problem. Never. The AMP operates even when the data pair voltage is about 0.5 V.

The difference voltage of the data pair amplified sufficiently as described above is applied to the column address decoder YDEC.
I / O by read selection signal φR1 of driver DRV
The read / write control circuit RWC is output on the pair line.
And the data output DOUT. Here, QR1 and QR2 are circuits for converting the voltage of the data pair line into a current. Assuming that the threshold voltage of these transistors is 0.5 V, the current on the I / O line does not flow because the voltage of the data line DL1 is 0 V, whereas the current flows on the / I / 0 line because it is 1 V at / DL1. Which large current flows can be detected in the RWC in the form of the polarity discrimination of the differential current or the differential voltage (using the resistor R in the figure). If the threshold voltage VT of QR1 and QR2 is sufficiently low, for example, 0.2V, the amplifier A
Since a small voltage difference before amplification by MP can be detected, the speed is increased by that amount. This is because the transconductance is increased by an amount corresponding to the reduction in VT, and a larger current can flow.

In the above read operation (FIG. 4), the node voltage of the memory cell MC1 will be examined in detail. If QP1 or QP2 is turned on during this operation period, or if VCH (2 V) is forcibly applied to the feeder line PL1 or the like by removing QP1 or QP2, a problem occurs. When VCH is an external voltage having a large current driving capability, a large DC current continues to flow from all the cells on PL1 during a period in which a voltage is applied to the word line, resulting in a large power. Alternatively, when the power supply voltage VCH boosted in the chip is used as in the present embodiment, the level of VCH is reduced because the current driving capability of the booster circuit is insufficient. Therefore P
The storage voltage of the unselected cells on L1 also drops. Once the voltages of all the power supply lines have dropped, it takes a long time to recover the level of VCH. This is because the total parasitic capacitance of the feed line is large. Therefore, the cycle time of the SRAM becomes slow.
Therefore, when the cell is inactive, all the power supply lines PL1 and PL2 are forcibly set to VCH (2 V) by the precharge signal .PHI.P, but during the activation period, each power supply line is disconnected from the VCH generation circuit. Each power supply line is substantially in a floating state, and the level of VCH is held in their parasitic capacitance. However, when the cell is activated (in this case, a read operation), the cell node N1 eventually becomes 0, and QC2 conducts strongly. Since the sources of these transistors are connected to PL1, the floating voltage of PL1 drops from VCH, and as a result N1 and N2 tend to charge high. However, N1 remains at 0 because it is forcibly fixed to the voltage of DL1 (0 V). On the other hand, Q
The gate of T2, ie, the voltage of WL1 is 2V, and / DL1 is also 1
Since V is V, QT2 conducts and N2 continues to be charged until QC2 equalizes the voltage of PL1 and N2.
V. The feed line, which is obviously discharged to 1 V, is localized. That is, it is only PL1, and PL2 corresponding to other unselected word lines is not discharged and remains at VCH.
In an actual memory, there are many power supply lines, and only one of them is discharged, so there is no useless charge / discharge power, and the power supply line to be charged by the built-in VCH generation circuit is localized to one. Therefore, the design of the VCH generation circuit becomes easy.

The write operation to the cell MC1 is performed by applying a differential voltage to the common I / O pair line as shown in FIG.
Now, an example will be described in which information reverse to the information stored so far is written in MC1. Data pair lines DL1, / DL1
Are applied with voltages of 1 V and 0 V, respectively, and the voltages are applied to the cell nodes N1 and N2 as they are. Therefore, a difference voltage of 1 V has been written to the nodes N1 and N2. After turning off word line WL1 from 2V to 0, ΦP
When the precharge operation is performed at the
Is amplified up to 2 V by the amplifying action of the cell itself. This is because the voltage of the cell feed line PL1 becomes 2V. This higher voltage becomes the subsequent information holding voltage.

Here, also in the write operation, WL1 must be turned off to minimize the capacity to be charged by the VCH generating circuit before applying VCH to PL1.

The above operation does not destroy the information stored in the other memory cells MC on the selected word line WL1 as described above. While the memory cell MC1 is performing a read or write operation and exchanging information (data) with the I / O pair line, a selection pulse is always applied to WL1 of MC2. The operation is performed between MC2 and the data pair lines DL2 and / DL2. Therefore, even if PL1 changes from 2V to 1V, if VCH of 2V is applied again, two nodes in MC2 will be at VC.
Return to H, 0. Also, there is no adverse effect on the information stored in the memory cells MC3 and MC4 on the unselected word line WL2.
This is because the sub-threshold current does not flow to the transistors in MC3 and MC4 because the VT is sufficiently high, and the junction leakage current is negligibly small even if it flows, so that the power supply line PL2 maintains VCH at the time of precharge. .

The amplitude of the pulse voltage of the selected word line is VCC
If the maximum value (VD) that the data line can take is set at VCC-VT or less, the word voltage does not need to be generated from the step-up power supply VCH, and the transistors (QT1, QT2) in the memory cell can be used during cell writing. Since the influence of the threshold voltage VT can be eliminated, the design becomes easy. FIG. 6 shows an embodiment in such a case. FIG. 6A shows a circuit diagram, and FIG. 6B shows a waveform diagram. FIG.
3 shows a portion related to the driving method of the memory cells in the entire SRAM shown in FIG. 3. The difference from FIG. 3 lies in the precharge circuit PC and the read / write circuit RWC. Further, in this embodiment, the signal level of the word line is set to the reference potential of 0 V and the power supply potential VCC, and the power supply node on the high potential side of the memory cell at the time of non-selection is set to V.
CH (= 2Vcc), the power supply node on the low potential side of the memory cell was set to 0 V, which is the reference potential. The precharge potential of the data line is set to a potential which is higher than the reference potential (0 V = VSS) by at least the sensitivity voltage of the memory cell.

The sensitivity voltage or sensitivity of a memory cell is
For example, this is the minimum potential difference necessary for inverting the state of the memory cell which is a flip-flop circuit by the potential difference applied between DL and / DL in FIG. Data line D
In order to make the potential difference applied between L and / DL a sensitivity voltage, the precharge potential of the data line should be half or more of this sensitivity voltage. Normal memory cell sensitivity voltage is 0.2V
In this case, the reference voltage VR is set to 0.2 V with a margin, and the precharge potential of the data line is set to 0.2 V.
V. In other words, this embodiment is an example in which the maximum value of the voltage amplitude that the data line can take is lowered to a low voltage VR close to the sensitivity voltage of the memory cell itself, which is lower than VT (0.5 V). Since the voltage amplitude of the data line of the memory cell is minimized, high-speed and low-power operation can be performed accordingly. For this reason, the data pair line can be precharged by a step-down power supply comprising a comparator using QL1 and VR as reference voltages.

The storage voltage of the memory cell can be made sufficiently high as VCH (2 V).

The read operation will be described below with reference to FIG. First, all the cell power supply lines are precharged to VCH (2 V) by the precharge signal φP. After the completion of the precharge, a pulse having an amplitude VCC (1 V) is applied to the selected word line (WL1). No in cell
Taking the case where N1 is 0 and N2 is VCH (2V) as an example, Q
T1 conducts and the data line DL1 discharges from 0.2V toward 0. On the other data line / DL1, QT2 conducts but QS2 does not conduct, so that the electric charge of the node N2 is distributed to / DL1 and the data line rises slightly from 0.2V to υ.
This increase is slight because the data line capacity is over 100 times larger than the node capacity in the cell. At this time, the voltage of N2 is discharged from 2V to υ. The differential voltage appearing on the data pair in this manner is taken out to the I / O pair as cell read information through the read transistors QR1 and QR2. Here, a P-channel MOS is used for QR1 and QR2 in order to obtain a large gain.
As a result of this series of operations, PL1 eventually drops to υ. However, the next time the precharge operation starts, since .SIGMA. Is greater than the sensitivity of the cell itself, it is normally amplified to VCH by the cross-coupled P-channel MOSs QC1 and QC2. If the voltage difference Ｎ between N2 and N1 is less than this sensitivity, amplification is not performed normally during precharge, and inverted information may be held. In the write operation, after a differential voltage of 0.2 V is applied to one of the data pair lines selected from the I / O pair line and 0 is applied to the other, a PL1 is applied by a precharge operation as in the read operation. 2V
By doing.

FIG. 7 shows an embodiment in which a large storage voltage is obtained by pulse driving two power supply nodes on the high potential side and the low potential side of a memory cell during precharge.
(A) shows the circuit diagram, and (b) shows the waveform diagram. FIG.
3 shows a portion related to the driving method of the memory cell in the entire SRAM of FIG. 3. The difference from FIG. 3 is that the potential on the low potential side of the memory cell is changed according to the selection / non-selection of the memory. It is to be able to change.
That is, the power supply node on the low potential side of the memory cell is set to 0 V, which is the reference potential when not selected, and to a potential lower than VCC / 2 by at least the above-described sensitivity voltage of the memory cell when selected. In this embodiment, the signal level of the word line is 0 V which is the reference potential and the power supply potential VCC.
In this case, the precharge potential of the data line is VCC / 2, and the power supply node on the high potential side of the memory cell when not selected is VCH (= 2
VCC).

In FIG. 6, the precharge voltage of the data line is a low voltage near 0 V.
It is characterized by being CC / 2. Therefore, the read transistors QR1 and QR2 in FIG. 6 can be replaced with N-channel MOS suitable for high-speed operation. Also, two types of amplifiers (QS1, QS2, QC1
And QC2) are activated, so that the signal is amplified at a higher speed.
Now, VCH = 3V, VCC = 1.5V, VT = 0.5V, VR =
Let's assume 0.2V. It is also assumed that a VCC / 2 precharge circuit PC as shown in FIG. 3 is connected to each data pair line. During the precharge period, all data lines are set to 0.
A power supply line such as 75V, PL1 is set to 3V, and a power supply line connected to the N-channel MOS in the cell is set to 0V, such as PL1 '. This is because during the precharge period, QL2 is cut off by QL3, and PL1 'is set to 0 by QL4. Also, two nodes (N
1, N2) is 3 V or 0 according to the stored information. When the precharge is completed, PL1 is maintained at 3V. On the other hand, PL1 'starts rising toward VCC by the resistor R', but (VCC / 2) -VR, that is, 0.55V
Then, the voltage limiting circuit formed by the comparator and QL2 using (VCC / 2) -VR as a reference voltage is activated, and further increase is suppressed. At the same time, for example, the low voltage side node N1 also becomes 0.55V. Here, R 'is set to a relatively high resistance value in order to suppress power consumption, but a MOS transistor can be used instead.
When the word voltage rises, N1 is 3V and N1 is 0.55.
Since the voltage is V, QT1 and QS1 conduct, and the data line DL1 is discharged. Since there is only a difference of VR between DL1 and PL1 ',
Eventually, DL1 is discharged to the voltage of PL1 'of 0.55V.
On the other hand, since QS2 is non-conductive, the electric charge of the node N2 is discharged to / DL1 through QT2 and N2 and / DL1
Is approximately equal to 0.75 V + υ. This difference voltage appearing on the data pair lines is taken out to the I / O pair lines through selection of a read circuit connected to each data line. Subsequent precharge causes the voltage between nodes N1 and N2 to be approximately 0.2.
The difference voltage of V is rapidly amplified to 3V. PL1 'is 0
Since N1 was 0.55V and N2 was a voltage slightly higher than 0.75V (そ れ), both QS1 and QS2 conduct, and the difference voltage of approximately 0.2V between N1 and N2 becomes Amplified by cross-coupled amplifiers QS1 and QS2. This difference voltage is also amplified by the other cross-coupled amplifiers QC1 and QC2. In the example of FIG. 6, the amplifier composed of QS1 and QS2 was non-conductive at the beginning of the amplification in the cell at the start of the precharge, and the amplification was performed only by the amplifier composed of QC1 and QC2, so that the speed was slightly lower. However, in this example, both amplifiers contribute to the amplifying action at the beginning of amplification, so that the speed is high. Obviously, in the write operation, 0.75 V is applied to one of the selected data pair lines and 0.55 V is applied to the other in accordance with the write data. Of course, PL1 'is controlled so that it becomes 0.55 V at the time of cell selection as well as at the time of reading.
In this example, since the voltage amplitude of the data line is as small as about 0.2, it can be driven by a VCC / 2 voltage generation circuit built in the chip. Therefore, the amplifier AMP of FIG. 3 can be removed in some cases, and the chip becomes small. Further, since the data pair line always operates near VCC / 2, the stress voltage applied to the transistors for the precharge circuits and the readout circuits (QR1, QR2) on each data line is reduced by half, so that the reliability is improved. Incidentally, the precharge voltage of the data line is not necessarily required to be VCC / 2. Obviously, the precharge voltage of the data line may be set to be higher than the sensitivity of the amplifier in the cell with respect to the PL1 'voltage at the time of selection.

In this embodiment, the N-channel MOS in the cell is used.
QL2, for each source drive line PL '(PL1', PL2 ')
An example in which a power supply circuit including QL3 and a comparator is connected has been described. This is to increase the access time by increasing the time for raising PL1 'to 0.55V. However, in order to reduce the chip area, this circuit can be shared with other power supply lines as shown in FIG. During the precharge period, the common power supply line PLC is always fixed at (VCC / 2) -VR by the common power supply circuit, but all the power supply lines (PL1 '... PLn') are zero. Now PL1 '
Is selected, .phi.X1 becomes 0 and PL1 'is disconnected from the PLC. Thereafter, / ΦP becomes VCC and discharges PL1 to 0.

FIG. 9 shows that the voltage of the data line at the time of reading is VCC.
This is an example of application to a driving method that takes a value in the vicinity. FIG. 9 shows FIG.
Of the entire SRAM described above, a portion related to the driving method of the memory cell is taken out. The difference from FIG. 3 lies in the precharge circuit PC and the read / write control circuit RWC. In this embodiment, the signal level of the word line is set to the reference potential of 0 V and the power supply potential VCC, and the power supply node on the high potential side of the memory cell when not selected is VCH (= 2 V).
CC), the power supply node on the low potential side of the memory cell was set to 0 V, which is the reference potential. Also, the precharge potential of the data line is set to V
CC.

Each data line is connected to transistors QD1 and QD2 serving as a load for the selected cell and a transistor QEQ for balancing the data pair voltage. These circuits are the precharge circuit PC of this embodiment. The operation will be described below using the read operation timing of FIG.

During the precharge period, the data pair line is connected to VCC.
(1V), and PL1 is VCH (2V). Here, the data pair lines DL1, / DL1 are selected by the column address selection signal ΦRW1 (ΦRW1 is from 1V to 0), and the word line W
It is assumed that L1 is selected and a pulse of 0 to 1 V is applied. Assuming that N2 is 2 V, a direct current flows between QD1, QT1, and QS1, and as a result, a small ratio voltage VS (about 0.2 V) appears on DL1. On the other hand, N1 is almost 0, QS2 is non-conductive, and QT2 is also non-conductive as is apparent from the voltage relationship, so that no current flows through the paths of QD2, QT2, and QS2. The reason for this is that the voltage of N1 rises slightly due to the ratio operation, because the size of the transistor in the cell is designed to be lower than VT. Therefore, a differential signal of only VS appears on the data pair line. Since this voltage is a ratio voltage, the voltage is directly transmitted to the I / O pair line and read out without using a complicated read circuit as shown in FIG. Here, since QS2 and QT2 are always non-conductive, the charge stored in the node N2 is not lost. That is, the voltage of PL1 remains at 2V. Therefore, even if the current driving capability of the VCH booster circuit built in the chip is not so large, no current flows through PL1, which is the load, so that Qp1 can be removed and connected directly in some cases. However, this can be done only in the read operation. The fact that this becomes difficult in a write operation will be described with reference to FIG.

When writing is performed so that 1 V is applied to one DL1 of the data pair line and 0 V is applied to the other data line / DL1 from the I / O pair line, the node N1 in the cell becomes almost zero.
From 0.5V. The threshold voltage of QT1 is 0.5V and W
This is because the voltage of L1 is 1 V, and the voltage dropped by the threshold voltage becomes the voltage of N1. On the other hand, N2 is 2
It becomes 0 from V. This is because QT2 conducts and N2 discharges so as to be equal to the voltage of / DL1. Therefore, QC1 is Q
The degree of conduction is higher than that of C2, and PL1 in the floating state is forcibly discharged to 0.5 V applied from the data line to N1. Therefore, PL1 must be charged to 2 V again by the subsequent precharge.

If the voltage drop of PL1 is large, a boosted voltage (VCH) generating circuit must supply a corresponding charge to PL1 and the load on the boosting circuit becomes heavy. For this reason, the area of the VCH generation circuit itself increases, and the power consumption increases. FIG. 12 shows a load circuit for suppressing the voltage drop to near VCC. In FIG. 12 (a), QP is turned off during the time period when a cell is selected, and QR is turned on instead.

Since the voltage of the power supply line changes from VCH to VCC,
One of the nodes in the cell (for example, N1) does not drop to 0.5 V as shown in FIG. 11 and is suppressed to VCC (1 V).

In FIG. 12B, the precharge pulse / Φ
P is removed to simplify the design. The threshold voltage is about 0.2 V, which is lower than that of other transistors.
Channel MOS QR is used. Since the power supply line is diode-connected, conduction occurs when the voltage of the power supply line becomes equal to or lower than VCC-VT, that is, 0.8 V, so that a voltage drop of less than that value can be prevented. In other words, one of the cell nodes
1, the voltage does not drop to 0.5V and is suppressed to 0.8V. This transistor QR also prevents the voltage level of the floating PL1 from being excessively lowered by the diffusion layer leakage current in the cell when the pulse timing of Qp is off for a long time, and also enlarges the voltage margin of the cell. I do.

Assuming the voltage application shown in FIGS. 10 and 11, in addition to the configuration in which the word line and the power supply line are installed in parallel as shown in FIG. 9, the word lines WL1 and WL2 and the power supply line PL1 and PL1 as shown in FIG. PL2 may be arranged orthogonally. For example, when cells on WL1 are read, all the cells perform the same operation as in FIG. 10, so that the voltage (VCH) levels of all the power supply lines do not change. However, in the write operation, only the power supply line belonging to the selected data pair line changes. For example, when a pulse voltage of a combination of 1 V and 0 corresponding to the write information is applied to the data pair lines DL1 and / DL1 (obviously omitted in the figure), the cell MC1 performs the same operation as in FIG. 2V to 0.5V
Descends to Since the cell MC2 performs the same operation as in FIG. 10, the voltage VCH of PL2 does not change. Whether the mutual arrangement of the word line and the feed line is parallel or orthogonal depends on the cell layout and area. In FIG. 9, although the feeder line and the data pair line intersect, there is a drawback that the wiring must be laid out with different wiring layers, but there is an advantage of low noise. For example, consider a case where a large voltage change occurs in PL1 because a pulse is applied to WL1 and cell MC1 is written. At this time, since the cell MC2 is performing a read operation effectively, its signal is transmitted to the data pair line DL.
2, / DL2. Since this signal is very small, MC
Operation 2 is strongly susceptible to noise. However, since the data pair line is orthogonal to PL1, noise generated by the voltage change of PL1 via the coupling capacitance is canceled on the data pair line. FIG. 13 is the opposite of FIG.
For example, differential noise is generated in the adjacent data pair line (DL2, / DL2) due to the voltage fluctuation of PL1. However, in this case, as is well known in dynamic memories and the like, noise can be canceled out by intersecting the data pairs in the middle.

In the above embodiment, it has been assumed that VCH is generated from a power supply in which VCC is boosted in the chip. This is for realizing a VCC single power supply operation which is easy for the user to use. However, in some cases, VCH may be the chip external power supply itself. For example, as shown in FIG. 14, the case of two external power supplies (VCC1, VCC2) can be considered. The chip includes an input / output interface circuit INTF, a static memory SRAM, and an arithmetic circuit (for example, a microprocessor M).
PU)). INTF operates relatively large components at relatively high voltages (VCC1) to ensure existing logic interface levels. On the other hand, since CORE determines the performance (speed, power) and chip area of the chip, the main part of this part is improved in performance by using a fine element operating at a low voltage (VCC2). Elements in the CORE are generally finer than elements in the INTF. In such a chip, VCC1 may be regarded as VCH in the above embodiments. By doing so, the entire chip operates with two power supplies, but there is no problem such as output level fluctuation accompanying the internal power supply operation, and the design becomes easy. FIG. 15 shows an example in which FIG. 14 is applied to a chip realized by a single power supply. The main part of CORE is connected to an external single power supply (V
In a chip operated by an internal power supply (VCC2) obtained by stepping down CC1), VCC1 may be regarded as VCH in the above embodiments.

In the above embodiment, the memory cell is assumed to be of the CMOS type. However, in the present invention, since the function of the differential amplifier in the memory cell is applied, at least the number of latch-type amplifiers cross-coupled in the memory cell is small. You only need one. Instead of the P-channel MOS (QC1, QC2), a well-known high-resistance polysilicon load or the like may be used. VCH of nodes N1 and N2
Because it can be amplified by the cross-coupled N-channel MOSs (QS1, QS2). VT of N-channel transfer transistors QT1 and QT2 having a transfer function in a memory cell.
May be lower than the VT of other transistors in the memory cell, for example, 0.2. At the time of selection, the effective gate voltages of QT1 and QT2 increase by the amount of lowering VT, the drive current increases, and high-speed operation becomes possible. However, Q when not selected
In order to eliminate the sub-threshold current flowing through T1 or QT2, the word line in the non-selected state, that is, the gates of QT1 and QT2 must be biased so as to be deeper than 0 to a negative voltage, for example, -0.2V. Must. The gate voltage and the source voltage are respectively VG,
Assuming that VS, the effective gate voltage when QT1 or QT2 is not selected is VG-VS-VT, but when VG, VS and VT are -0.2V or less, respectively, this effective gate voltage is 0V and 0.2V. -0.4V or less. On the other hand, if the minimum value of VT at which the subthreshold current can be ignored is 0.4 V,
Under normal bias conditions, the effective gate voltage of a transistor having a VT of 0.4 V is such that VG, VS, and VT are 0, respectively.
Since it is 0 and 0.4V, it becomes -0.4V. Therefore, in the above-described system in which the low VT and the negative voltage gate are combined, a lower effective gate voltage is applied, and no subthreshold current flows. In this case, the selected word voltage is a pulse which rises from -0.2 V in a non-selected state to VCC or more.

Although it has been assumed that the VT of the P-channel and N-channel transistors in the memory cell is equal to 0.5 V, this is not always necessary. Since the N-channel transistor is an important transistor that determines a read current to the data line and the like, this VT is set to a VT that is as low as possible, for example, 0.4 V, at which the subthreshold current does not matter. However, the P-channel transistor mainly charges a very small capacity in the memory cell and may be a little slower.
V or more, for example, may be set to 0.6V. For simplicity, it has been assumed that VCH is twice VCC. However, as long as VCH is lower than the withstand voltage of the transistor, for example, the gate withstand voltage,
It should be CC or more.

Further, there is a method of charging the power supply line at a high speed while increasing the sensitivity in the memory cell. As described above, a circuit in which transistors are cross-coupled in a memory cell can be regarded as a differential amplifier.
The capacitance difference between N2 also affects the sensitivity of the differential amplifier. Depending on the layout of the memory cells, there may be a case where a difference in capacitance can be caused by giving priority to high density, but if this value is large, the sensitivity is deteriorated. That is, immediately before the amplification, a larger voltage difference is required between the nodes N1 and N2. The sensitivity due to the capacitance difference becomes worse as the speed of raising the power supply line (eg, PL1) to VCH is higher. This problem is caused by the problem shown in FIG.
It can be solved by step amplification. That is, each feed line (PL
1) are connected in parallel with two transistors having significantly different channel widths (for example, 10 times). When ΦP is applied, the transistor (QP1) having a small channel width is turned on to charge the power supply line little by little, and after a large voltage difference between the nodes N1 and N2 is amplified, ΦP 'is applied to apply the ΦP'. The large transistor (QP1 ') is turned on to charge at high speed.

FIG. 17 is a sectional view of an embodiment of the present invention.
As shown in this embodiment, the switch MOS (QP) and the PMOS transistor of the memory cell are formed in an n-well. However, since the source or drain electrode of each transistor becomes as large as VCH, the potential of those wells also increases. It is necessary to keep VCH. At this time, the potential of the n-well forming the PMOS transistor of the peripheral circuit is VCC.
In this case, the substrate may be made P-type.

FIG. 18 is an embodiment of another sectional view of the present invention. In this embodiment, the switch MOS and the PM of the memory cell
Since a large voltage VCH is applied to the OS transistor, the breakdown voltage is increased by making the gate oxide films of these MOSs thicker than the peripheral circuits. Since the MOS transistor of the peripheral circuit has a low oxide film pressure, the transconductance is increased, and there is an effect that the MOS transistor can operate at high speed.

FIG. 19 is a sectional view of another embodiment of the present invention. This embodiment is an embodiment in which the switch MOS and the PMOS of the memory cell are not separated as in the case where the switch MOS is attached to each memory cell as shown in FIG. In such a case, the wells forming both MOS transistors may be set to the potential of VCH.

FIG. 20 is a sectional view of another embodiment of the present invention.
This is an embodiment when the present invention is formed on an N-type substrate. N
When the present invention is applied on the mold substrate, the peripheral circuit, the switch MOS, and the PMOS of the memory cell cannot be separated. Therefore, as shown in this embodiment, a common deep P well is formed in the switch MOS and the PMOS of the memory cell, and an N well is formed therein to change the potential from the peripheral circuit.

To make the most of the advantages of the present invention, it is desirable that the memory array and peripheral circuits be further improved. FIG. 21 shows an embodiment applied to an SRAM portion in a chip or a one-chip SRAM. The memory part is divided into a plurality of memory arrays (MA1, MA2,...). The global word line is wired over a plurality of memory arrays. In the memory array, sub-word lines (WL11,..., WLn1, WL12,..., WLn2,.
M data lines, data line directions (DL11, / DL11,..., D
L12, / DL12,...) And a plurality of m × n memory cells MC arranged in a matrix. Switch M
OS transistors (QPL11, ..., QPLn1, QPL12, ...,
QPLn2,...) To a power supply node on the higher potential side of the plurality of memory cells, to which a boosted voltage VCH is applied.
, PLn1, PL12,..., PLn2,...) Are wired so as to form pairs with the above-described sub-word lines. Incidentally, the sub-word line can be simply read as a word line in correspondence with the above-described embodiment.

Now, in the method based on FIG. 9, the VT of the MOS transistors (QC1, QC2, QS1, QS2) forming the memory cell of the memory cell MC is 0.5 V, as shown in FIG.
The VT of the transfer MOS transistors (QT1, QT2) is 0.2
V. That is, the MOS transistor included in the memory cell is set to a threshold voltage at which the subthreshold current does not cause a problem in the entire SRAM, and the transfer MOS transistor is set to a threshold voltage that requires attention. The power supply VCC externally supplied to the SRAM is 1 V, the boosted voltage VCH formed from the VCC by the voltage conversion circuit VC2 is 2 V (= 2VCC), and the negative voltage −VWB similarly formed from the VCC by the voltage conversion circuit VC3. Is 0.2
V.

For example, one sub-word line WL11 is selected, that is, the aforementioned negative voltage -VWB (for example, -0.2
To apply a cell activation pulse rising from V) to VCC (1 V) to WL11, the global word line GL1 and control line RX1 may be selected by an address signal. R
X1 is selected by using YDEC DRV and the timing control circuit TC, and substantially selects the memory array M1.
A memory array selection signal $ sr1, which is a signal for selecting A1, is used. That is, by LCB receiving Фsr1-
A pulse rising from VWB to VCC is applied to RX1, and G
A pulse rising from VCC to -VWB may be applied to GL1 by another level converter LCB connected to L1. The global word line GL1 has a row address AX
Are selected by the row address decoder / driver XDEC / DRV. At this time, the other GL lines (global word lines) and the other RX lines remain at VCC and -VWB, respectively. On the other hand, in the switch MOS selection signal group (ФP1, ФP2...), Only ФP1 becomes a pulse rising from 0 to VCH by another level converter LCA, and the other
Remains. Therefore, the switch MOS connected to PL11,..., PLn1 is turned off, and the corresponding switch MOS group of the non-selected memory array remains on. ФP1
Is raised from 0V to VCH using a memory array selection signal $ sp1, which is formed using the YDEC DRV and the timing control circuit TC2, and is a signal that substantially selects the memory array MA1. Thus, WL11
The upper memory cell (MC) group is activated and operates as described above.

Here, Q'D1, Q'D2 on each data pair line
Is an accelerating transistor for precharging the data pair line voltage up to VCC at high speed. RWC is a read / write circuit selected by a column read selection signal (@ RY1) similar to that shown in FIG.
Is used. In addition, a column write selection signal (@WY
N / P channel MO selected by (1, / ФWY1)
S are connected in parallel.

As described above, the word line and the power supply line are divided into multiple parts.
By partially driving, the load on the built-in VCH or -VWB generation circuit can be reduced, and the design of a single power supply becomes easier. This is because a power supply line or a word line that needs to supply power to VCH or −VWB due to a change in the voltage with the operation is localized in the sub-power supply line sub-word line WL11. This embodiment has the advantage that an increase in area due to division is small since only one switch MOS needs to be added for each power supply line. However, for example, ΔP1 is high voltage (VC
H) Since it is a pulse, the power for charging and discharging the gate capacitances of a large number of switch MOSs connected to this line becomes relatively large.

FIG. 23 shows the calculated operating voltage margin of the memory cell of FIG. In this figure, the horizontal axis is the power supply voltage VCC supplied from the outside, and the vertical axis is the data line DL and / or the data line DL when the word line WL is selected (from 0 V to VCC).
The signal rise time τ is defined as the time required for the potential difference of DL to reach 100 mV. The smaller the signal rise time τ, the better. Conventional assumes that all the six MOS transistors in the memory cell of FIG. 22 have the same threshold voltage VT = 0.75V, and that QC1 and QC2
Of the conventional memory cell in which the source-side power supply node (the high-potential side power supply node of the memory cell) is directly connected to the power supply voltage VCC. In this conventional configuration, since the VT of the MOS transistor is large, the subthreshold current does not substantially matter. However, in the conventional configuration, it can be seen that when the power supply voltage becomes 0.8 V or less, the signal rise time τ sharply increases, and the operation is substantially stopped. That is, when the power supply voltage VCC becomes lower than the threshold voltage VT of the MOS transistor used, the memory cell does not substantially operate due to the increase of the rise time τ.

On the other hand, when the memory cell of FIG. 22 of the present application is used, the operation is performed to a lower power supply voltage. FIG.
The curve shown by This work in FIG. 22 indicates that the threshold voltage of QC1, QC2, QS1, and QS2 constituting the memory cell in the memory cell of FIG. 22 is 0.75V, and the transfer MOS transistor QT1
And the threshold voltage of QT2 is calculated as 0.2V. Further, the boosted voltage VCH is calculated for two cases of 2VCC and 3VCC, and the calculation points are indicated by circles and squares, respectively. In this example, even when the power supply voltage becomes equal to or lower than the threshold voltage of the MOS transistor of the memory cell, the circuit operates at about τ = 10 ns, and operates up to about 0.5V. That is, according to the present application, although the threshold voltage of the MOS transistor of the memory cell cannot be set to a certain value or less (for example, 0.5 V) due to the restriction of the sub-threshold current, the configuration of the SRAM that operates at the threshold voltage or less. Law was shown. In FIG. 22, since the threshold voltages of QT1 and QT2 are set to 0.2 V at which the sub-threshold current becomes a problem, the signal level on the low potential side of the word line is set to −VWB, and QT1 and QT2 are set when the memory cell is in the non-selected state. Sub-threshold current is prevented from flowing. When a MOS transistor having a threshold voltage of, for example, 0.5 V is used so that the subthreshold current does not become a problem in QT1 and QT2, the signal level on the high potential side of the word line is sufficiently increased so that its driving capability is increased. You only need to increase the pressure. Furthermore, if the VT of the load MOS on the data line or the MOS in the read / write circuit RWC shown in FIG. 21 or the like is made sufficiently small (for example, 0.2 V or less), a sufficiently low voltage operation is possible.
Other peripheral drive / logic circuits are described in the book "Ultra L
The use of a subthreshold current low-frequency circuit as described in "SI memory" is effective at a sufficiently low VT, that is, a sufficiently low VCC. Therefore, the chip as a whole operates even at VCC lower than VT of the intra-cell cross-coupled MOS.

The present invention is particularly advantageous in an apparatus operating at a low power supply voltage such as a battery.

That is, although the power supply voltage of the solar cell is about 0.5 V, an SRAM that can operate with this solar cell can be realized for the first time. Further, since the voltage can be reduced, the effect of reducing power consumption is remarkable.

FIG. 24 shows another embodiment in which the area is slightly increased but the power consumption is further reduced. Figure 21 for simplicity
Only the portions of WL11 and PL11 are extracted. FIG.
MOS transistors PL11 to PL for switching VCH of
While n1 is simultaneously controlled by one signal ФP1, FIG.
In No. 4, a switch MOS and a level converter for controlling the gate thereof are added to each divided power supply line. For example, when WL11 is selected and an active pulse is applied, QPL1
Is changed from 0 to VCH and QPL1 is turned off. Therefore, the gate capacitance driven by the high voltage (VCH) becomes one, and the power is reduced. At this time, other switches M
The gate of the OS remains at 0.

[0065]

As is apparent from the embodiments described above, the present invention can realize a semiconductor device incorporating a high-speed static memory cell having a wide voltage margin without increasing current consumption even at a low voltage operation.

[Brief description of the drawings]

FIG. 1 is a diagram showing a concept of the present invention for controlling a feed line voltage of a static memory cell.

FIG. 2 is a conventional static memory cell and its operation waveform diagram.

FIG. 3 is an embodiment applied to a static memory cell array.

FIG. 4 is a timing chart of the read operation of FIG. 3;

FIG. 5 is a timing chart of the write operation of FIG. 3;

FIG. 6 is an embodiment applied to a static memory cell array.

FIG. 7 is an embodiment applied to a static memory cell array.

FIG. 8 is an embodiment in which a power supply power supply circuit is shared.

FIG. 9 is an embodiment applied to a static memory cell array.

FIG. 10 is a timing chart of the read operation of FIG. 9;

FIG. 11 is a write operation timing chart of FIG. 9;

FIG. 12 is a circuit diagram of a voltage drop prevention circuit of a power supply line.

FIG. 13 is an embodiment in which a feeder line and a word line are orthogonal to each other.

FIG. 14 is an example of application to an external dual power supply chip.

FIG. 15 is an example of application to an external single power supply chip.

FIG. 16 is an example of a driving method of a power supply line.

FIG. 17 is a sectional view of an embodiment of the present invention.

FIG. 18 is a sectional view of another embodiment of the present invention.

FIG. 19 is a cross-sectional view of another embodiment of the present invention.

FIG. 20 is a sectional view of another embodiment of the present invention.

FIG. 21 is an embodiment applied to a divided memory cell array.

FIG. 22 is an embodiment of the memory cell internal circuit of FIG. 21;

FIG. 23 is a characteristic diagram of the example of the memory cell of FIG. 22;

FIG. 24 is an embodiment of a driving method of a divided power supply line.

[Explanation of symbols]

QC1, QC2, QT1, QT2, QS1, QS2,. . . . The transistors in the memory cell, N1, N2. . . . Storage nodes in memory cells, DL, / DL, DL11, / DL11, DL12,
/ DL12. . . . Data lines, WL1, WL2, WL11, W
L12, WLn1, WLn2,. . . Word lines, PL1, PL2,
PL1 ', PLm', PL11, PL12, PLn1, PLn
2． . . Feed line, PLC. . . Common feed line, MC, MC1
~ MC4. . . Memory cell, VSS. . . Reference potential, VC
C. . . Power supply voltage, VCH. . . Power supply voltage or boosted power supply voltage, QP1, QP2, QP, QP1 '. . . Switch transistor, CE. . . Chip activation signal, PC. . . Precharge circuit, ΦP, / ΦP ', ФP1, ФP2, ФP
1 '. . . Precharge signal, AMP. . Amplifier, S
P, SN. . . Amplifier drive line, QEQ. . . Transistors for balancing, ΦR1, ΦR2. . . Read selection symbol, ΦW1, Φ
W2. . . Write selection symbol, ΦRW1. . . Read / write selection symbol, AX, AY. . . Row and column addresses,
Din, Dout. . . Data input and data output, / W
E. FIG. . . Write control signals, QR1, QR2. . . Read transistor, QW1, QW2. . . Write transistor, SPG. . . Amplifier drive circuit, XDEC, DR
V. . . Row decoder and driver, YDEC, DR
V. . . Column decoder and driver, I / O, / I /
O. . . Data input / output line, RWC. . . Read / write control circuit, QL1, QL2, QL3, QL4. . . Internal voltage control transistors, ΦX1, ΦXn. . . Feed line selection signal,
INTF. . . Chip input / output interface circuit, C
ORE. . . The main circuit of the chip, VDC. . . Built-in step-down circuit, VCC1, VCC2. . . Power supply voltage, VC1, VC2, VC
3 ,. . . Voltage conversion circuit, PCG. . . Precharge signal generation circuit, LCA, LCB. . . Level converter, R
X1, RX2. . . Control line, GL1, GLn. . . Global word line, ФRY1. . . Column read selection signal, ФWY
1, @ WY1. . . Column write selection signal, QPL1, QPL
2． . . Switch transistor, VWB. . . Word line bias voltages, MA1, MA2. . . Memory array, Фsr1,
Фsr2. . . Memory array selection signal, # sp1, $ sp2. . .
The memory array selection signals TC1, TC2. . . Timing control circuit, GA11, GAn1, GA12, GAn2. . . NAN
D gate.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/8234 H01L 27/08 102C 27/088 27/10 311

Claims (5)

[Claims] 1. A static memory cell having a first MOS interconnected with each other, a data line connected to the static memory cell, and a peripheral circuit having a second MOS and connected to the data line And a threshold voltage of the first MOS is higher than a threshold voltage of the second MOS. 2. The semiconductor device according to claim 1, wherein a plurality of operating voltages are supplied to said peripheral circuit. 3. The insulating film of said second MOS is formed of said first MOS.
3. The semiconductor device according to claim 1, wherein the semiconductor device is thinner than an insulating film of the OS. 4. The device according to claim 1, wherein said peripheral circuit includes a read / write circuit and a processor circuit.
4. The semiconductor device according to any one of claims 3 to 3. 5. The method according to claim 1, wherein said static memory cell is DRA.
2. The semiconductor device according to claim 1, wherein the cell is an M cell.