JP2000021166A - Boosting circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize a boosting circuit such as a word-line selection-voltage generation circuit or the like whose supply efficiency can be enhanced comparatively easily, to realize the low power consumption of a dynamic RAM or the like which contains the word-line selection-voltage generation circuit and to increase an operating margin especially on its low-voltage side. SOLUTION: In a dynamic RAM, a boosting circuit such as a word-line selection-voltage generation circuit VPPG or the like using a pump capacitance C4 is built in. In the dynamic RAM, an electrode on the opposite side of the capacitance C4 by which an electrode on the side of its output node, i.e., on the side of a word-line selection-voltage supply node VPP, is precharged to a positive potential such as, e.g. a power-supply voltage VDD is precharged to a negative potential such as, e.g. an internal voltage VBO generated in the generation process of a substrate voltage. After that, the negative potential is changed into the positive potential such as the power-supply voltage VDD.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a booster circuit,
For example, the present invention relates to a word line selection voltage generation circuit built in a dynamic RAM (random access memory) or the like, and a technique particularly effective for reducing power consumption and improving an operation margin.

[0002]

2. Description of the Related Art A word line and a bit line which are arranged orthogonally, and an information storage capacitor and an address selection MO are arranged in a lattice at intersections of the word line and the bit line.
SFET (metal oxide semiconductor field effect transistor.
In this specification, a memory integrated circuit device such as a dynamic RAM having a memory array including a large number of dynamic memory cells each including a MOSFET and an insulated gate field effect transistor) is described as a basic component. is there. In these dynamic RAMs and the like, the word line selection level is at least the address selection M higher than the high level of the storage data written in the memory cell.
In many cases, a word line selection voltage VPP higher than the threshold voltage of the OSFET is used.
For example, an internal voltage generation circuit including a word line selection voltage generation circuit that generates a word line selection voltage VPP based on an externally supplied power supply voltage VDD is provided.

On the other hand, in recent years, technology for miniaturization and high integration of semiconductor integrated circuits has been remarkably advanced, and dynamic RA
M and the like are also benefiting from these benefits and are in the process of increasing in size and capacity. Further, in order to prevent breakdown voltage breakdown of MOSFETs and the like due to miniaturization and to suppress an increase in power consumption of dynamic RAMs and the like due to the increase in scale, the operating power supply voltage has been reduced, and the power supply voltage VDD has been reduced. The absolute value is
For example, it is being compressed to about 2.5 V (volt). Furthermore, a dynamic RAM in which the operating power supply voltage has been reduced.
For example, a booster circuit using a pump capacitance is known as one means for efficiently generating the word line selection voltage VPP.

[0004]

SUMMARY OF THE INVENTION Dynamic RAM
The word line selection voltage VPP has a potential higher than a high level such as a power supply voltage VDD corresponding to data held in a memory cell, for example, logic “1” by at least a threshold voltage of the address selection MOSFET. Needed. However, as the miniaturization and high integration of dynamic RAMs and the like have advanced and the operating power supply voltage has been reduced, the threshold voltage has not become smaller than expected compared to the scaling of MOSFETs, and the word line Selection voltage V
The potential of PP is, for example, twice the power supply voltage VDD, that is, 2 V
It is approaching DD.

As is well known, in a booster circuit using a pump capacitor, an electrode of the pump capacitor on the word line selection voltage supply node side is precharged to, for example, a power supply voltage VDD. The electrode on the opposite side is precharged to the ground potential VSS, that is, 0 V, and is then changed to the power supply voltage VDD. In response to this, the electrode on the word line selection voltage supply node side is twice the power supply voltage VDD, It is boosted to a high voltage such as 2VDD. The potential of this high voltage is controlled by a level sensor, and thereby the word line selection voltage VP
The potential of P is set to a desired potential VPP. The supply efficiency of the booster circuit is high voltage 2VDD and word line selection voltage VPP.
Of the potential VPP, that is, 2VDD / VPP, increases, and the supply capability also increases.

However, as the operating power supply voltage of the dynamic RAM and the like has been reduced, the threshold voltage of the address selection MOSFET of the memory cell does not become smaller than expected, as described above. The obtained high voltage 2VDD and the potential VP of the word line selection voltage VPP
The ratio of P is decreasing. As a result, the supply efficiency of the booster circuit, that is, the word line selection voltage generation circuit is reduced,
As the power consumption of the dynamic RAM or the like increases, the operating margin of the dynamic RAM decreases particularly when the power supply voltage VDD changes to the allowable minimum voltage side.

An object of the present invention is to realize a boosting circuit such as a word line selection voltage generating circuit which can relatively easily improve the supply efficiency. Another object of the present invention is to reduce the power consumption of a dynamic RAM or the like having a built-in booster circuit such as a word line selection voltage generation circuit, and to increase the operation margin particularly on the low voltage side.

[0008] The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0009]

The following is a brief description of an outline of typical inventions disclosed in the present application. That is, in a dynamic RAM or the like having a built-in booster circuit such as a word line selection voltage generation circuit using a pump capacitor, the electrode on the output node side, that is, the word line selection voltage supply node side is set to a positive potential such as a power supply voltage. The electrode on the opposite side of the pump capacitor to be precharged is precharged to a predetermined negative potential generated in the process of generating the substrate voltage, for example, and then changed to the positive potential.

According to the above means, the absolute value of the high voltage obtained by the boost action of the pump capacity is increased by the absolute value of the negative potential, and the absolute value of the high voltage and the absolute value of the required potential of the word line selection voltage are calculated. , The supply efficiency of the word line selection voltage generation circuit and the like can be increased, and the supply capability thereof can be increased. As a result, it is possible to reduce the power consumption of a dynamic RAM or the like having a built-in word line selection voltage generation circuit, and it is possible to increase the operation margin particularly on the low voltage side.

[0011]

FIG. 1 shows a dynamic RAM incorporating an internal voltage generation circuit VG including a word line selection voltage generation circuit VPPG (boost circuit) to which the present invention is applied.
(Memory integrated circuit device) A block diagram of an embodiment is shown. First, an outline of the configuration and operation of a dynamic RAM including the word line selection voltage generation circuit VPPG and the internal voltage generation circuit VG of this embodiment will be described with reference to FIG. The circuit elements constituting each block in FIG. 1 are formed on a single semiconductor substrate surface such as single crystal silicon by a known MOSFET integrated circuit manufacturing technique.

Referring to FIG. 1, the dynamic RAM of this embodiment has a memory array MARY, which occupies most of the surface of a semiconductor substrate, as a basic component. Memory array MARY includes a predetermined number of word lines arranged in parallel in the vertical direction in the figure, and a predetermined number of sets of complementary bit lines arranged in parallel in the horizontal direction. At the intersections of these word lines and complementary bit lines, a large number of dynamic memory cells composed of information storage capacitors and address selection MOSFETs are arranged in a grid.

The word lines constituting the memory array MARY are connected to an X address decoder XD and are alternatively set to a predetermined selection level. The X address decoder XD is supplied with i + 1-bit internal address signals X0 to Xi from the X address buffer XB, an internal control signal XG from the timing generation circuit TG, and a word line from the internal voltage generation circuit VG. A word line selection voltage VPP (fourth voltage) at the selection level is supplied.
Further, X address signals AX0 to AXi are supplied to the X address buffer XB in a time-division manner from an external access device via address input terminals A0 to Ai.
A predetermined internal control signal XL is supplied from the timing generation circuit TG. Although the word line selection voltage VPP is not particularly limited, it is a positive potential having a relatively large absolute value, such as +3.8 V.

An X address buffer XB is provided with an X address signal AX supplied through address input terminals A0 to Ai.
0 to AXi are captured and held according to the internal control signal XL, and the internal address signals X0 to Xi are formed based on these X address signals and supplied to the X address decoder XD. The X address decoder XD is selectively activated by receiving the high level of the internal control signal XG, and decodes the internal address signals X0 to Xi.
The corresponding word line of the memory array MARY is alternatively set to a selection level such as the word line selection voltage VPP.

Next, the complementary bit lines forming the memory array MARY are coupled to a sense amplifier SA on the left side of the figure, and the complementary common data lines CD0 * to CDj are selectively connected by j + 1 pairs via the sense amplifier SA. *(here,
For example, the non-inverting common data line CD0T and the inverting common data line CD0B are indicated by asterisks like a complementary common data line CD0 *. In addition, a so-called non-inverted signal or the like which is selectively set to a high level when it is made valid is represented by adding a T to the end of its name, and a so-called low level is selectively set to a low level when it is made valid. Inverted signals and the like are indicated by adding a B to the end of their names. Hereinafter the same).

The sense amplifier SA is supplied with a bit line selection signal of a predetermined bit (not shown) from the Y address decoder YD, and is supplied with internal control signals PA and PC (not shown) from the timing generation circuit TG. The Y address decoder YD is supplied with i + 1-bit internal address signals Y0 to Yi from a Y address buffer YB and an internal control signal YG from a timing generation circuit TG. Furthermore, Y address signals AY0 to AYi are supplied to the Y address buffer YB in a time division manner from an external access device via address input terminals A0 to Ai, and an internal control signal YL is supplied from a timing generation circuit TG. .

The Y address buffer YB is provided with a Y address signal AY supplied via address input terminals A0 to Ai.
0 to AYi are captured and held in accordance with the internal control signal YL, and internal address signals Y0 to Yi are formed based on these Y address signals and supplied to the Y address decoder YD. The Y address decoder YD is selectively activated in response to the high level of the internal control signal YG, decodes the internal address signals Y0 to Yi, and
A bit corresponding to the bit line selection signal for the sense amplifier SA is alternatively set to a high selection level.

The sense amplifier SA is connected to the memory array MAR
Y includes a predetermined number of unit circuits provided corresponding to respective complementary bit lines of Y. Each of these unit circuits includes a pair of C
A unit amplifier circuit in which MOS (complementary MOS) inverters are cross-coupled; a bit line precharge circuit in which three N-channel precharge MOSFETs are connected in series / parallel; and a pair of N-channel switch MOSs
And an FET. Among them, the unit amplifier circuit of each unit circuit is selectively and simultaneously operated by the dynamic RAM being selected and the internal control signal PA being set to the high level, and the selected word line of the memory array MARY is selected. The small read signals output from the predetermined number of memory cells coupled via the corresponding complementary bit lines are respectively amplified to produce high-level or low-level binary read signals.

On the other hand, the precharge MOSFETs constituting the bit line precharge circuit of each unit circuit are simultaneously turned on in response to the high level of the internal control signal PC,
The non-inversion and inversion signal lines of the corresponding complementary bit lines of the memory array MARY are precharged to a predetermined intermediate potential.
Further, the switch MOSFET pair of each unit circuit receives the high level of the corresponding bit of the bit line selection signal and receives the j +
One pair is selectively turned on, and the memory array MAR is turned on.
Selective connection is made between j + 1 sets of complementary bit lines corresponding to Y and complementary common data lines CD0 * to CDj *.

The complementary common data lines CD0 * to CDj * are
The data input / output circuit IO is coupled to a corresponding unit circuit. The data input / output circuit IO is supplied with internal control signals WP and OC (not shown) from the timing generation circuit TG.

The data input / output circuit IO includes j + 1 unit circuits provided corresponding to the complementary common data lines CD0 * to CDj *. Each of these unit circuits includes a write amplifier, a main amplifier, and a data input buffer. And a data output buffer. Of these, the output terminals of the write amplifier and the input terminals of the main amplifier that constitute each unit circuit are connected to the corresponding complementary common data lines CD0 * to CD0.
j * are commonly connected. Also, the input terminals of the write amplifier of each unit circuit are respectively coupled to the output terminals of the corresponding data input buffers, and the output terminals of the main amplifier of each unit circuit are coupled to the input terminals of the corresponding data output buffers. The input terminals of the data input buffers and the output terminals of the data output buffers that constitute each unit circuit are commonly coupled to corresponding data input / output terminals D0 to Dj, respectively. The internal control signal WP is commonly supplied to the write amplifier of each unit circuit, and the internal control signal OC is commonly supplied to the data output buffer of each unit circuit.

The data input buffers of the unit circuits of the data input / output circuit IO are provided with data input terminals D0 to D0 when the dynamic RAM is selected in the write mode.
The write data of j + 1 bits supplied via j is taken in and transmitted to the corresponding write amplifier.
At this time, the write amplifier of each unit circuit selectively operates in response to the high level of the internal control signal WP, and sets the write data transmitted from the corresponding data input buffer to a predetermined complementary write signal. Data is written from the common data lines CD0 * to CDj * to the selected j + 1 memory cells of the memory array MARY via the sense amplifier SA.

On the other hand, when the dynamic RAM is selected in the read mode, the main amplifier of each unit circuit of the data input / output circuit IO outputs the complementary common data line from the (j + 1) selected memory cells of the memory array MARY. The binary read signal output via CD0 * to CDj * is further amplified and transmitted to the corresponding data output buffer. At this time, the data output buffer of each unit circuit selectively operates in response to the high level of the internal control signal OC, and outputs these read data from the data input / output terminals D0 to Dj to an external access device.

The timing generation circuit TG generates various internal control signals and the like based on a row address strobe signal RASB, a column address strobe signal CASB, and a write enable signal WEB supplied as an activation control signal from an external access device. It is selectively formed and supplied to each part of the dynamic RAM.

The dynamic RAM is further supplied with a power supply voltage VDD via an external terminal VDD and a ground potential VSS via an external terminal VSS. Also,
The dynamic RAM is based on a power supply voltage VDD and a ground potential VSS supplied through these external terminals.
An internal voltage generation circuit VG for generating a predetermined word line selection voltage VPP and a substrate voltage VBB is provided. The internal control signal CS is supplied to the internal voltage generation circuit VG from the timing generation circuit TG. Although not particularly limited, the power supply voltage VD
D is set to +2.5 V, for example. As described above, the word line selection voltage VPP is set to +3.8 V, and the substrate voltage VBB is set to a negative potential such as -1.0 V. Further, the internal control signal CS is selectively set to a high level at a predetermined timing when the dynamic RAM is set to the selected state.

The internal voltage generating circuit VG determines whether the absolute value of the word line selection voltage VPP is equal to or less than a predetermined value when the dynamic RAM is in the selected state and the internal control signal CS is at the high level, or by the built-in level sensor LS. Is selectively turned on, the word line selection voltage VP
P and the substrate voltage VBB are generated. Among them, the word line selection voltage VPP is supplied to the X address decoder XD as described above, and the substrate voltage VBB is applied to the semiconductor substrate SUB.
And so on. The specific configuration and operation of the internal voltage generation circuit VG will be described in detail below.

FIG. 2 is a block diagram showing one embodiment of the internal voltage generating circuit VG included in the dynamic RAM of FIG. Based on the drawing, an internal voltage generation circuit VG including a word line selection voltage generation circuit VPPG of this embodiment is shown.
An outline of the configuration and operation of the device will be described.

In FIG. 2, an internal voltage generating circuit VG
A word line selection voltage generation circuit VPPG and a substrate voltage generation circuit VBBG are included. Among these, the output signal of the NOR (NO) gate NO0, that is, the internal signal PC is supplied to the word line selection voltage generation circuit VPPG, and the internal voltage VBO is supplied from the substrate voltage generation circuit VBBG. The output voltage is supplied to the X address decoder XD as a word line selection voltage VPP, and is also supplied to one input terminal of the level sensor LS. The substrate voltage generation circuit VBBG includes a word line selection voltage generation circuit VP
Non-inverted internal signal BCT and inverted internal signal BCB from PG
Is supplied to the semiconductor substrate of a dynamic RAM as a substrate voltage VBB.

The other input terminal of the level sensor LS is
A reference voltage VR is supplied from a constant voltage circuit (not shown),
The output signal is supplied to the pulse generation circuit POSC. An output signal of the pulse generating circuit POSC, that is, a pulse signal PS is supplied to one input terminal of the NOR gate NO0, and the other input terminal of the NOR gate NO0 receives a one-shot pulse generating circuit OSPG receiving the internal control signal CS. Is output by the inverter V0.

The one-shot pulse generation circuit OSPG of the internal voltage generation circuit VG operates when the dynamic RAM is selected and the internal control signal CS is at a high level.
In response to the rising edge, a negative one-shot pulse having a predetermined pulse width is generated. The level sensor LS includes a word line selection voltage generation circuit VPPG.
Is compared with a reference voltage VR, and when the potential of the word line selection voltage VPP is lower than the reference voltage VR, the output signal is selectively set to an effective level such as a high level. Further, the pulse generating circuit POSC selectively forms a pulse signal PS having a predetermined cycle when the output signal of the level sensor LS is set to a high level. When the output signal of the level sensor LS is at a low level, the output of the pulse generation circuit POSC is at a low level.

Thus, the output signal of NOR gate NO0, that is, internal signal PC is applied to one-shot pulse generation circuit O
When the one-shot pulse as the output signal of the SPG is set to the low level, or when the pulse signal PS as the output signal of the pulse generation circuit POSC is set to the high level, in other words, the initial state when the dynamic RAM is selected is selected. For a predetermined period or the word line selection voltage VPP
Is lower than the reference voltage VR, it is selectively set to the high level.

As will be described later, the word line selection voltage VPP of the internal voltage generation circuit VG includes a pump capacitor, and selectively operates in response to the output signal of the NOR gate NO0, that is, the high level of the internal signal PC. A predetermined word line selection voltage VPP is generated. Also, the word line selection voltage VP
In the process of generating P, a non-inverted internal signal BCT and an inverted internal signal BCB are formed and supplied to the substrate voltage generation circuit VBBG.

On the other hand, substrate voltage generation circuit VBBG of internal voltage generation circuit VG includes two pump capacitors and is complementary in accordance with non-inverted internal signal BCT and inverted internal signal BCB supplied from word line selection voltage generating circuit VPPG. The substrate voltage VBB is generated by performing a proper pump operation. In the process of generating the substrate voltage VBB, the non-inverted internal signal BCT
A pulse having a period corresponding to the inverted internal signal BCB, that is, the internal signal PC, and having a high level as the ground potential VSS, that is, 0 V, and a low level as a negative potential having the same absolute value as the power supply voltage VDD, that is, -VDD. Internal voltage VBO of word line select voltage generation circuit VPP
Supply G.

In this embodiment, the word line selection voltage V
When the internal signal PC is set to the low level, the electrode of the pump capacitor constituting the PP on the word line selection voltage supply node VPP side is precharged to a high level such as the power supply voltage VDD. The electrode on the opposite side is connected to the internal signal PC.
Is at low level, the substrate voltage generation circuit VBBG
Is precharged to a negative potential such as -VDD, i.e., -VDD, and the internal signal PC is set to a high level, the power supply voltage VDD is supplied at a predetermined timing.
And a high level like As a result, the absolute value of the high voltage obtained by boosting the pump capacity of the word line selection voltage generating circuit VPPG is increased by the absolute value of the internal voltage VBO as compared with the prior art, and the absolute value of the high voltage is correspondingly increased. The ratio between the value and the absolute value of the required potential of the word line selection voltage is increased. As a result, the supply efficiency of the word line selection voltage generation circuit and the like can be increased, and the supply capability thereof can be increased. Therefore, low power consumption of a dynamic RAM or the like including the word line selection voltage generation circuit can be achieved. At the same time, the operation margin particularly on the low voltage side can be increased. Specific configurations and operations of the word line selection voltage generation circuit VPPG and the substrate voltage generation circuit VBBG will be described in detail below.

FIG. 3 is a circuit diagram of one embodiment of the word line selection voltage generation circuit VPPG included in the internal voltage generation circuit VG of FIG. 2, and FIG. 4 is a signal waveform diagram of the embodiment. It is shown. With reference to these drawings, the specific configuration and operation of the word line selection voltage generation circuit VPPG included in the internal voltage generation circuit VG of this embodiment and the features thereof will be described. In the following circuit diagrams, MOSFEs whose channel (back gate) portions are indicated by arrows.
T is a P-channel type, and is distinguished from an N-channel MOSFET without an arrow.

In FIG. 3, the word line selection voltage generation time V
The PPG includes three boost capacities C1 to C3 and one pump capacity C4. Of these, the other electrode of the boost capacitor C1, ie, the internal node n1 as the lower electrode, is coupled to the output terminal of the NOR gate NO1, and one of the electrodes, ie, the internal node n2 as the upper electrode, is connected to an N-channel MOSFET N5 in a diode form. And power supply voltage VDD. Further, the other electrode of boost capacitor C2, that is, internal node n3 as a lower electrode is coupled to the output terminal of NOR gate NO2, and one of the electrodes, that is, the upper electrode, is connected to an internal node n2 whose gate is coupled to internal node n2.
It is coupled to power supply voltage VDD via a channel type precharge MOSFET N6, and is coupled to the other electrode of boost capacitor C3, ie, internal node n4 as a lower electrode, via a P-channel MOSFET P3 receiving power supply voltage VDD at its gate. .

The lower electrode of boost capacitor C3, that is, internal node n4, is coupled to the drain of N-channel MOSFET N3 receiving power supply voltage VDD at its gate. The source of MOSFET N3 receives at its gate an inverted signal of internal signal PC by inverter V1.
Internal voltage supply point V via channel MOSFET N4
Bound to BO. An internal node n5, which is one electrode of the boost capacitor C3, that is, an upper electrode, is connected to an N-channel type precharge M whose gate is coupled to the internal node n2.
An N-channel transfer MOSFET N coupled to the power supply voltage VDD via the OSFET N8.
H is coupled to the gate. As will be described later, the potential of the internal node n5 when the word line selection voltage generation circuit VPPG performs the boosting operation is the fifth voltage, which is a high voltage such as 4VDD.

Internal node n2 is further coupled to power supply voltage VDD via an N-channel MOSFET N7 whose gate is coupled to the upper electrode of boost capacitor C2, and has three N-channel MOSFETs N9 to N9 in diode form. The power supply voltage VDD is coupled via NB.

One input terminal of the NOR gate NO1 has
The output signal of the NOR gate NO0, that is, the internal signal PC is supplied, and the other input terminal is supplied with a delayed signal of the internal signal PC by the inverters V1 to V4. An inverted signal of the internal signal PC by the inverter V1 is supplied to one input terminal of the NOR gate NO2, and a NAND gate NA1 is supplied to the other input terminal.
Are supplied by the inverters V5 and V6. An internal signal PC is supplied to one input terminal of the NAND gate NA1, and a delay signal by the inverters V1 to V4 is supplied to the other input terminal. The output signal of the NAND gate NA1 is the inverter V
7, and becomes an inverted internal signal BCB for the substrate voltage generation circuit VBBG.
It becomes a non-inverted internal signal BCT via an inverter V8 composed of P1 and an N-channel MOSFET N1.

On the other hand, the other electrode of the pump capacitor C4, that is, the internal node n6 as the lower electrode is connected to the inverter V8.
, An inverted signal of the non-inverted internal signal BCT by an inverter V9 comprising a P-channel MOSFET P2 and an N-channel MOSFET N2. One of its electrodes, that is, an internal node n7 which is an upper electrode, has its gate coupled to the internal node n2. Power supply voltage VDD via an N-channel type precharge MOSFET NC.
Is combined with Inverter V9 uses internal voltage VBO as its lower-potential-side operation power supply. Further, the internal node n7 is
An N-channel MOSFET which is coupled to a word-line selection voltage supply node VPP, which is an output node of a word-line selection voltage generation circuit VPPG, via an N-channel transfer MOSFET NH, and is formed in a diode form.
Three N-channel MOSFETs NE coupled to the power supply voltage VDD via the ND and in diode form
Through NG to the power supply voltage VDD.

Here, as shown in FIG. 4, the internal signal PC is normally set to a low level such as the ground potential VSS, for a predetermined period when the dynamic RAM is selected, or a word line selection voltage. When the potential of VPP is lower than the reference voltage VR, it is selectively set to a high level like the power supply voltage VDD.

When the internal signal PC is at a low level,
In the word line selection voltage generation time VPPG, the NOR gate NO
2 or the internal signal n at the internal node n1
1 is at a high level such as the power supply voltage VDD, and the output signal of the NOR gate NO2 receiving the inverted signal of the internal signal PC by the inverter V1, that is, the internal signal n3 at the internal node n3 is at a low level such as the ground potential VSS. The inverted internal signal BCB is set to a low level such as the ground potential VSS in response to the low level of the internal signal PC, and the non-inverted internal signal BCT is set to a high level such as the power supply voltage VDD in response to the low level of the inverted internal signal BCB. Is done. At this time, the potential of internal voltage VBO output from substrate voltage generating circuit VBBG is negative potential -VDD having the same absolute value as power supply voltage VDD, that is, -2.5 V, as described later.

The internal node n2, which is the upper electrode of the boost capacitor C1, is turned on when the internal signal n1 goes high.
The boosting action of the boost capacitor C1 pushes up the potential VP1 close to 2VDD (here, the absolute value of the power supply voltage VDD is referred to as VDD; the same applies hereinafter), but if the potential becomes abnormally high for any reason, the MOSFET
VDD + 3Vthn (where the threshold voltage of one N-channel MOSFET is Vthn
Expressed as Hereinafter the same). In response to the high level of internal node n2, precharge MOSF
ETN6, N8 and NC are turned on, and power supply voltage VDD is transmitted to both the upper electrode of boost capacitor C2, the upper electrode of boost capacitor C3, ie, internal node n5, and the upper electrode of pump capacitor C4, ie, internal node n7.

At this time, the lower electrode of the boost capacitor C2, that is, the internal node n3 is connected to the ground potential VSS as described above.
Is set to a low level. Also, the boost capacity C3
, The internal node n4 is connected to the MOSFET N4 which is in the ON state by receiving the high level of the inverted signal of the internal signal PC by the inverter V1 and the MOSFET N3 which is in the ON state by receiving the power supply voltage VDD at its gate. The negative potential of voltage VBO is transmitted. Further, the negative potential of the internal voltage VBO is transmitted to the lower electrode of the pump capacitor C4, that is, the internal node n6, through the MOSFET N2 which is in the ON state in response to the high level of the non-inverted internal signal BCT.

As a result, the boost capacitor C2 is precharged so that its upper electrode is at the power supply voltage VDD (first voltage) and its lower electrode is at the ground potential VSS, and the boost capacitor C3 and the pump capacitor C4 are at their upper electrodes. The electrode is precharged so as to have the power supply voltage VDD and the lower electrode at the negative potential −VDD (second voltage). At this time, the transfer MOSFET NH is turned off because the internal nodes n5 and n7 are both set to the power supply voltage VDD,
The potential of the word line selection voltage VPP at the word line selection voltage supply node VPP is maintained at a high voltage.

Next, when the internal signal PC is changed to a high level such as the power supply voltage VDD in response to the above condition, the word line selection voltage generating circuit VPPG first sets the NOR gate N.
The output signal of O1, that is, the internal signal n1 is set to a low level such as the ground potential VSS, and the output signal of the NOR gate NO2, that is, the internal signal n3 is changed to the power supply voltage VDD when the delay time of the inverters V1 to V6 and the NAND gate NA1 has elapsed. High level. At almost the same time, the inverted internal signal BCB is set to the high level such as the power supply voltage VDD, and the non-inverted internal signal BCT is set to the ground potential V.
It is set to a low level like SS. Therefore, the internal voltage VBO is changed to a high level such as the ground potential VSS, and the MOSFET N
2 is the low level of the non-inverted internal signal BCT and the internal voltage V
In response to the high level of BO, the transistor is turned off, and the MOSFET P2 is turned on instead. As a result, the lower electrode of the pump capacitor C4, that is, the internal node n6 is connected to the MOSF
It is changed to a high level such as the power supply voltage VDD (third voltage) via the ETP2.

When the internal signal n1 is set to the low level, the potential of the internal node n2 is lowered via the boost capacitor C1, but the internal node n2 and the power supply voltage V
Since a diode-type MOSFET N5 is provided between DD, the low level VP2 is clamped at VDD-Vthn. Therefore, the potential VP1 of the internal node n2 at the time of boosting is 2VDD-Vthn.
Further, in response to the low level of the internal node n2, the precharge MOSFETs N6, N8 and NC are turned off all at once, and the precharge operation for the upper electrodes of the boost capacitors C2 and C3 and the pump capacitor C4 is stopped.

At this time, the lower electrode of the boost capacitor C2 is boosted by receiving the high level of the internal signal n3, and the upper electrode is boosted to 2VDD in response to the boost. Also, a MOSFET receiving the boost potential of the upper electrode of the boost capacitor C2 and receiving the power supply voltage VDD at its gate.
P3 is turned on, and the boost potential of the upper electrode of the boost capacitor C2 is transmitted to the lower electrode of the boost capacitor C3, that is, the internal node n4. At this time, the MOSFET N3 receiving the power supply voltage VDD at its gate potential is turned off by receiving the boost potential of the lower electrode of the boost capacitor C3, and the MOSFET N4 is turned off by the inverter V of the internal signal PC.
It is turned off in response to the low level of the inversion signal due to 1. As described above, the boost capacitor C3 has an upper electrode connected to the power supply voltage VDD and a lower electrode connected to the negative potential −.
It is precharged to VDD and the potential difference between the two electrodes is 2VDD. Therefore, the potential of the upper electrode of boost capacitor C3, that is, internal node n5, is equal to the potential change of its lower electrode, that is, internal node n4, that is, 2VD
The voltage is boosted by the addition of the potential difference between D and the two electrodes, that is, 2VDD, and is boosted to a high voltage of 4VDD.

On the other hand, the pump capacity C4 is equal to the boost capacity C
Similarly to 3, the upper electrode is set to the power supply voltage VDD and the lower electrode is precharged to the negative potential -VDD, and the potential difference between the two electrodes is also set to 2VDD.
Therefore, the potential at the upper electrode of the pump capacitor C4, that is, at the internal node n7, becomes lower than that at the lower electrode, that is, at the internal node n7.
6 is boosted to a high level such as the power supply voltage VDD, thereby being boosted to a high voltage of 3VDD. The high voltage of the internal node n7 is not affected by the threshold voltage of the internal node n5 via the transfer MOSFET NH which is completely turned on by setting the gate potential, that is, the internal node n5 to a high voltage of 4VDD. It is transmitted to line select voltage supply node VPP. But,
Since the potential at the word line selection voltage supply node VPP is monitored and controlled by the level sensor LS as described above, the center potential is actually 3 VD
D, that is, for example, the above-mentioned + 3.8V lower than 7.5V.

As is well known, the supply efficiency of the boosting circuit such as the word line selection voltage generating circuit VPPG depends on the pump capacity C.
4, the higher the ratio between the high voltage obtained by the boosting operation and the potential VPP of the word line selection voltage VPP, the higher the ratio, and the higher its supply capability. As in this example,
The upper electrode of the pump capacitor C4 is precharged to the power supply voltage VDD and the lower electrode is precharged to a negative potential such as -VDD, without increasing the absolute value of the power supply voltage VDD itself, in other words, dynamic. The absolute value of the high voltage obtained by the pump capacity C4 is set to 3
VDD, and the ratio between the absolute value of the high voltage and the absolute value of the required potential of the word line selection voltage can be increased. As a result, the supply efficiency of the word line selection voltage generation circuit and the like can be increased and its supply capability can be increased, so that the power consumption of the dynamic RAM incorporating the word line selection voltage generation circuit can be reduced. In particular, the operation margin on the low voltage side can be increased.

In this embodiment, the transfer MO
The lower electrode of the boost capacitor C3 for applying a high voltage of 4VDD to the gate of the SFETNH is similarly precharged to a negative potential such as -VDD, and the absolute value of the high voltage obtained by the boost capacitor C3 is expanded to 4VDD. You.
As a result, the high voltage obtained by the pump capacitance C4 can be transmitted to the word line selection voltage supply node VPP without being reduced by the threshold voltage of the transfer MOSFET NH.

When the upper electrodes of the boost capacitors C2 and C3 and the pump capacitor C4 are set to a high voltage,
In the word line selection voltage generation time VPPG, the power supply voltage VDD
Further, the MOSFET N7 provided between the internal node n2 is turned on by receiving the boosted potential of the upper electrode of the boost capacitor C2. As described above, diode-type MOSFETs N5 and N9 to NB are provided between the power supply voltage VDD and the internal node n2, and the potential thereof is VDD-Vt.
hn to VDD + 3Vthn. During this time, the potential of the internal node n2 is substantially in a floating state. Therefore, when the potential of the power supply voltage VDD changes due to, for example, a power supply bump or the like, the potential between the potential of the internal node n2 and the latest potential of the power supply voltage VDD is changed. Relationship is unspecified. As described above, the MOSFET N7 is provided between the power supply voltage VDD and the internal node n2.
TN7 is turned on each time the boost operation of VPPG is performed for the generation of the word line selection voltage, so that the internal node n
2 is always set to the latest potential of the power supply voltage VDD, thereby stabilizing the operation of the word line selection voltage generation VPPG and thus the dynamic RAM.

When the internal signal PC is returned to a low level such as the ground potential VSS, the word line selection voltage generation VPP
In G, first, the internal signal n1, which is the output signal of the NOR gate NO1, is set to a high level such as the power supply voltage VDD when the delay time of the inverters V1 to V4 has elapsed. The internal signal n3, which is the output signal of the NOR gate NO2,
In response to the high level of the output signal of the inverter V1, the level is changed to the low level at a relatively early point in time, and the inverted internal signal BCB and the non-inverted internal signal BCT are respectively returned to the low level or the high level with a slight delay. The internal node n2, which is the upper electrode of the boost capacitor C1, receives the low level of the internal signal n1 and is set to the potential VP1. The internal node n4, which is the lower electrode of the boost capacitor C3, is connected to the internal voltage VBO
Is set to a low level, it is precharged to a negative potential such as -VDD, and the internal node n5 as its upper electrode is
Are precharged to the power supply voltage VDD when the internal node n2 is set to the potential VP1. Further, the pump capacity C
4 is also connected to the internal voltage V
When BO is set to low level, it is precharged to a negative potential such as -VDD, and the internal node n serving as its upper electrode is
7 is precharged to the power supply voltage VDD when the internal node n2 is set to the potential VP1.

FIG. 5 is a circuit diagram of one embodiment of the substrate voltage generation circuit VBBG included in the internal voltage generation circuit VG of FIG. 1, and FIG. 6 is a signal waveform diagram of the embodiment. Have been. The specific configuration and operation of the substrate voltage generation circuit VBBG included in the internal voltage generation circuit VG of this embodiment will be described with reference to these drawings. The substrate voltage generation circuit VBBG actually includes a level sensor (not shown), and its substantial voltage generation operation is selectively performed according to the output signal of the level sensor. This is directly related to the present invention. I omitted it because there was no.

In FIG. 5, substrate voltage generating circuit VBBG
Includes two boost capacities CA and CB and pump capacities CC and CD, respectively. Among them, one electrode of the boost capacitor CA and the pump capacitor CC, that is, the left electrode thereof is connected to the inverter VA of the non-inverted internal signal BCT.
Or, an inverted signal by VC is supplied, and the boost capacitance CB
One of the electrodes of the pump capacitor CD, that is, the right electrode thereof is supplied with an inverted signal of the inverted internal signal BCB by the inverter VB or VD.

The other electrode of boost capacitor CA, that is, internal node na as the right electrode thereof is connected to a P-channel type precharge MO having a gate coupled to internal node nd.
P-channel transfer MOSFET PC coupled to ground potential VSS through SFET PA
To the gate. The other electrode of the pump capacitor CC, that is, the internal node nc which is the right electrode thereof is connected to the ground potential V via a P-channel type precharge MOSFET PE whose gate is also coupled to the internal node nd.
SS and the transfer MOSF
It is coupled to the drain of ETPC. Precharge MOS
Between the gates of the FETs PA and PE, that is, the internal node nd, and the ground potential VSS, a P-channel MOS in the form of a diode with the ground potential VSS side as a cathode.
An FET PG is provided.

Similarly, the other electrode of boost capacitor CB, that is, internal node nb as its left electrode is coupled to ground potential VSS via a P-channel type precharge MOSFET PB whose gate is coupled to internal node nc. And P-channel transfer MOSF
Coupled to the gate of the ETPD. Also, pump capacity CD
Of the other electrode, that is, the internal node nd which is the left electrode thereof
Is coupled to ground potential VSS via a P-channel type precharge MOSFET PF whose gate is coupled to internal node nc, and
It is coupled to the drain of ETPD. Precharge MOS
Between the gates of the FETs PB and PF, that is, between the internal node nc and the ground potential VSS, a P-channel MOS in the form of a diode having the ground potential VSS side as a cathode
An FETPH is provided.

The substrate portions of precharge MOSFETs PA and PE are coupled to the output terminals of inverters VB and VD, respectively, and the substrate portions of precharge MOSFETs PB and PF are coupled to the output terminals of inverters VA and VC, respectively. The substrate portions of the transfer MOSFETPC and the diode MOSFETPG are connected to the output terminal of the inverter VC, and
The substrate portions of the PD and the diode MOSFETPH are coupled to the output terminal of the inverter VD. The potential at the internal node nc is supplied to the word line selection voltage generation circuit VPPG as the internal voltage VBO. Further, the sources of the transfer MOSFETs PC and PD are coupled to the output node of the circuit, ie, the substrate voltage supply point VBB.

As exemplified in FIG. 6, the inverted internal signal B
When CB is at a low level such as ground potential VSS and non-inverted internal signal BCT is at a high level such as power supply voltage VDD, substrate voltage generating circuit VBBG receives an inverter VA which receives non-inverted internal signal BCT at its input terminal. , And VC are both at a low level such as the ground potential VSS. For this reason, the internal nodes na and nc on the right electrode side of the capacitance CA or CC become -V due to the boost action of the corresponding boost capacitance CA or pump capacitance CC.
DD, that is, a negative potential such as -2.5 V, for example.

At this time, the output signals of inverters VB and VD receiving inverted internal signal BCB are both supplied with power supply voltage VD.
D and the internal nodes nb and nd
Is about to be boosted to the power supply voltage VDD by the boost action of the corresponding boost capacity CB or pump capacity CD. However, substrate voltage generating circuit VBBG receives low level of internal node nc and receives precharge MOSF
Since ETPB and PF are turned on, internal nodes nb and nd are precharged to ground potential VSS.
Further, the transfer MOSFET PD has an internal node n
b is turned off in response to a high level such as the ground potential VSS, but the transfer MOSFET PC is turned on in response to the low level of the internal node na, and the low level of the internal node na, that is, −VDD is applied to the substrate voltage supply point VBB. introduce.

As described above, the potential at the substrate voltage supply point VBB is monitored and controlled by a level sensor (not shown). As a result, the central potential of the substrate voltage VBB at the substrate voltage supply point VBB is the low level of the internal node na, that is, −1.0 V whose absolute value is smaller than −VDD.
Is set to a negative potential such as

Next, the inverted internal signal BCB is changed to the power supply voltage VD.
D is changed to a high level and the non-inverted internal signal BCT
Is changed to a low level such as the ground potential VSS,
In substrate voltage generating circuit VBBG, output signals of inverters VB and VD receiving inverted internal signal BCB at their input terminals are both at a low level such as ground potential VSS. Therefore, the internal nodes nb and nd on the right electrode side of the capacitance CB or CD are set to -VDD, that is, a negative potential such as -2.5 V, for example, by the boosting action of the corresponding boost capacitance CB or pump capacitance CD.

At this time, the output signals of inverters VA and VC receiving non-inverted internal signal BCT attain a high level like power supply voltage VDD, and internal nodes na and nc become
The boost action of the corresponding boost capacity CA or pump capacity CC tends to boost the power supply voltage VDD. However, the substrate voltage generation circuit VBBG receives the low level of the internal node nd and receives the precharge MOSFET.
Since PA and PE are turned on, internal node na
And nc are precharged to the ground potential VSS. Further, the transfer MOSFETPC is connected to the internal node na.
Is turned off in response to a high level such as the ground potential VSS, but the transfer MOSFET PD is turned on in response to the low level of the internal node nb, and the low level of the internal node nb, that is, −VDD is changed to the substrate voltage supply point V.
Transmit to BB.

As described above, the potential at the substrate voltage supply point VBB is monitored and controlled by the level sensor (not shown). As a result, the center potential of substrate voltage VBB at substrate voltage supply point VBB is at the low level of internal node nb, that is, -1.0 V whose absolute value is smaller than -VDD.
Is set to a negative potential such as Thereafter, the above operation is repeated to obtain predetermined substrate voltage VBB and internal voltage VBO.

Note that the diode MOSFETs PG and P
H acts to prevent the potentials of the internal nodes nc and nd from unnecessarily increasing, for example, when the load on the substrate voltage VBB temporarily increases and its potential rapidly increases.

The operation and effect obtained from the above embodiment are as follows. That is, (1) In a dynamic RAM or the like having a built-in booster circuit such as a word line selection voltage generating circuit using a pump capacitor, the electrode on the output node side, that is, the word line selection voltage supply node side is, for example, a power supply voltage. After the electrode on the opposite side of the pump capacitor that is precharged to a positive potential is precharged to a predetermined negative potential, for example, and then changed to a positive potential such as a power supply voltage, a high voltage obtained by a boost action of the pump capacity Can be expanded by the absolute value of the negative potential. (2) According to the above item (1), the ratio between the absolute value of the high voltage and the absolute value of the required potential of the word line selection voltage is increased to increase the supply efficiency of the word line selection voltage generation circuit and the like, and to supply the same. The effect that the ability can be improved is obtained. (3) According to the above items (1) and (2), it is possible to reduce the power consumption of a dynamic RAM or the like having a built-in word line selection voltage generation circuit, and to increase the operation margin especially on the low voltage side. The effect is obtained.

(4) In the above items (1) to (3), the internal voltage generated in the process of generating the substrate voltage by the substrate voltage generating circuit is used as the negative potential serving as the precharge potential of the pump capacitance. Thus, the above-described effects can be obtained while suppressing an increase in the number of required circuit elements of the internal voltage generation circuit.

Although the invention made by the inventor has been specifically described based on the embodiments, the invention is not limited to the above-described embodiments, and can be variously modified without departing from the gist of the invention. Needless to say, there is. For example, in FIG. 1, the memory array MARY of the dynamic RAM can be divided into an arbitrary number of memory mats including its direct peripheral circuits. Also, the dynamic RAM can have any bit configuration,
It is not a requirement to take address multiplex. Further, the dynamic RAM may have an arbitrary block configuration, and may take various embodiments such as names and effective levels of a start control signal and an internal control signal, and a power supply voltage and a polarity and an absolute value of each internal voltage. .

In FIG. 2, the block configuration of internal voltage generating circuit VG is not restricted by this embodiment. FIG.
5 and FIG. 5, a word line selection voltage generation circuit VPPG
And the specific circuit configuration and MO of the substrate voltage generation circuit VBBG
The conductivity type of the SFET can take various embodiments as long as the basic circuit conditions do not change. 4 and 5, the absolute level and time relationship of each internal control signal, internal signal, internal voltage and the like do not affect the gist of this embodiment.

In the above description, the case where the invention made by the present inventor is mainly applied to the word line selection voltage generation circuit of the internal voltage generation circuit of the dynamic RAM, which is the background of the application, has been described. The present invention is not limited to this, and can be applied to, for example, a substrate voltage generation circuit and various internal voltage generation circuits, and can be applied to various memory integrated circuit devices or logic integrated circuit devices incorporating such an internal voltage generation circuit. Can also be applied. The present invention
The present invention can be widely applied to a booster circuit including at least a pump capacity and an apparatus or a system including such a booster circuit.

[0071]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, in a dynamic RAM or the like having a built-in booster circuit such as a word line selection voltage generation circuit using a pump capacitor, the electrode on the output node side, that is, the word line selection voltage supply node side is set to a positive potential such as a power supply voltage. After the electrode on the opposite side of the pump capacitor to be precharged is precharged to a predetermined negative potential generated in the process of generating the substrate voltage, for example, the voltage is changed to a positive potential such as the power supply voltage to boost the pump capacitance. The absolute value of the high voltage obtained by the operation is increased by the absolute value of the negative potential, and the ratio between the absolute value of the high voltage and the absolute value of the required potential of the word line selection voltage is increased, thereby producing a word line selection voltage generation circuit. Supply efficiency can be increased, and its supply capacity can be increased. As a result, it is possible to reduce the power consumption of a dynamic RAM or the like having a built-in word line selection voltage generation circuit, and it is possible to increase the operation margin particularly on the low voltage side.

[Brief description of the drawings]

FIG. 1 is a dynamic RA including an internal voltage generation circuit including a word line selection voltage generation circuit to which the present invention is applied;
FIG. 3 is a block diagram showing an example of M.

FIG. 2 is a block diagram showing one embodiment of an internal voltage generation circuit included in the dynamic RAM of FIG. 1;

FIG. 3 is a circuit diagram showing one embodiment of a word line selection voltage generation circuit included in the internal voltage generation circuit of FIG. 2;

FIG. 4 is a signal waveform diagram showing one embodiment of the word line selection voltage generation circuit of FIG. 3;

FIG. 5 is a circuit diagram showing one embodiment of a substrate voltage generation circuit included in the internal voltage generation circuit of FIG. 2;

FIG. 6 is a signal waveform diagram showing one embodiment of the substrate voltage generation circuit of FIG. 5;

[Explanation of symbols]

MARY ... memory array, XD ... X address decoder, XB ... X address buffer, SA ... sense amplifier, YD ... Y address decoder, YB ... Y address buffer, IO ... data input / output circuit, TG ... ... Timing generation circuit, VG ... Internal voltage generation circuit, D0 to Dj
...... Input / output data or its input / output terminal, RASB ... Row address strobe signal or its input terminal, CASB
..... column address strobe signal or its input terminal,
WEB: Write enable signal or its input terminal, A
0 to Ai ... address signal or its input terminal, VDD ...
... Power supply voltage or its input terminal, VSS ... Ground potential or its input terminal, VPP ... Word line selection voltage, VBB ...
... Substrate voltage, SUB ... Semiconductor substrate. VPPG: word line selection voltage generation circuit, VBBG: substrate voltage generation circuit, OSPG: one-shot pulse generation circuit, LS:
... Level sensor, VR ... Reference voltage, POSC ... Pulse generation circuit. P1 to P4, PA to PF: P-channel MOSFET, N1 to NH: N-channel MOSFET
T, V0 to V9, VA to VD... Inverter, C1 to C
4, CA-CD ... capacity, NO0-NO2 ... Noah (N
OR) gate, NA1 ... NAND gate,
n1 to n7, na to nd ... Internal nodes.

Claims (4)

[Claims] 1. The method according to claim 1, wherein one of the electrodes is precharged to a first voltage, and the other electrode is precharged to a second voltage having a polarity opposite to the first voltage. And at the output node generating a fourth voltage having an absolute value greater than the first and third voltages and having the same polarity at the output node. Characteristic booster circuit. 2. The transfer capacitor according to claim 1, wherein one electrode of the pump capacitor is a transfer MOSF.
A fifth voltage obtained by a boost capacitance is supplied to a gate of the transfer MOSFET at a predetermined timing, and one of the boost capacitances is provided to the gate of the transfer MOSFET. Wherein the first electrode is precharged to the first voltage and the other electrode is precharged to the second voltage and then to the third voltage. . 3. The method according to claim 1, wherein the first voltage has a predetermined positive potential, and the second voltage has a predetermined negative potential. Wherein the first voltage is used in combination with the first voltage. 4. The booster circuit according to claim 1, wherein the booster circuit is included in a predetermined memory integrated circuit device, and the memory integrated circuit device has a predetermined negative potential substrate voltage. Wherein the first voltage is a high-potential-side operating power supply of the memory integrated circuit device, and the second voltage is a substrate voltage generated by the substrate voltage generating circuit. A booster circuit, which is generated in a voltage generation process, wherein the fourth voltage is used as a word line selection voltage of the memory integrated circuit device.