JP2986939B2 - Dynamic RAM - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a dynamic RAM.
For example, the potential of a bit line pair is
MOSF received at the gate electrode of ET and corresponding to the potential
The present invention relates to a technique effective for a dynamic RAM in which data is transferred to a common data line by an ON resistance of an ET.

[0002]

2. Description of the Related Art FIGS.
5 will be described. FIG. 13 shows a conventional dynamic RA.
FIG. 14 shows a circuit diagram of M, and FIG.
FIG. 15 shows a circuit diagram of the sense amplifier circuit of FIG. 13 and its peripheral parts.

In these figures, Cs is an information storage capacitor, and Qm is an address selection MOS transistor. Each of M-ARY1 to M-ARY4 includes a plurality of memory cells each including an address selection MOS transistor Qm and an information storage capacitor Cs, and bit lines D and / D.
(/ Means an inverted signal) and a plurality of memory arrays arranged in a matrix at intersections of word lines W1 and W2.

A column address decoder YDCR has a bit line selection signal line YS (YS1, YS2). XDCR1 to XDCR4 are row address decoders serving as word line selection circuits for selecting the word lines W1 and W2. PC1 to PC4 are precharge circuits for the bit lines D and / D. SA1 to SA4 are sense amplifier circuits. SW1 to SW4 are selection circuits. LOD1-LO
D4 is the common data line CD1, / CD1, CD2, / CD
2,... Are precharge circuits. C-SW1-CS
W4 is a column selection switch circuit. MA1, MA
2 is a main amplifier circuit.

[0005] PRC1 to PRC4 are precharge circuits P
Control signals for controlling C1 to PC4. C1 to C4 are memory array selection signals. X00, X01, X1
0 and X11 are decode lines. RAS1 and RAS2 are row address strobe signals. rwc is a timing signal. TC is a timing generator.
Q1 to Q3 are switches composed of MOS transistors;
4 to Q11 are MOS transistors. SAD1, S
AD2 is a sense amplifier driver circuit. NS1, N
S2 is a common source line of the N-channel MOS transistor. PS1 and PS2 are common source lines of P-channel MOS transistors. WCL, WCL1, and WCL2 are timing signals.

[0006] WD1, / WD1, WD2, / WD2 are write data lines. CD1, / CD1, CD2, /
CD2 is a common data line. Vcc is a power supply line.
Vss is a ground line. SE, SE1, and SE2 are activation signals. A 1-bit memory cell in the dynamic RAM includes, for example, an information storage capacitor Cs and an address selection MOS transistor Qm, and information of logic “1” and “0” is stored in the information storage capacitor Cs.
It is stored in the form of whether or not s has a charge. Information is read by turning on the address selection MOS transistor Qm to couple the information storage capacitor Cs to the bit lines D and / D, and the potential of the bit line is stored in the information storage capacitor Cs. The change is performed by sensing how the charge changes according to the charge amount.

In recent years, for a RAM having a large storage capacity of, for example, 64 Mbits, which requires high integration and large capacity, each memory cell is reduced in size and each bit line D, / D A very large number of memory cells are coupled. Accordingly, the ratio Cs between the information storage capacitor Cs and the stray capacitance Cb of the bit lines D and / D is determined.
Since / Cb becomes very small, the potential change of the bit lines D and / D becomes a very small value.

In order to solve this problem, the bit lines are divided as shown in FIGS. 13 and 14, in other words, the memory array is divided in multiples in the bit line direction (M-
ARY1, M-ARY2, M-ARY3, M-ARY
4) By reducing the number of memory cells coupled to the bit lines in each memory array, Cs / Cb
Is maintained at a desired value.

At this time, the selection signal lines YS for the bit lines D and / D are so arranged that the peripheral area such as the decoder does not increase due to the multi-division and the chip area does not increase.
1, YS2, that is, each memory array M-ARY1, M-ARY2, M-ARY3, M-ARY divided by one column address decoder YDCR.
Select signal line YS for bit lines D and / D in ARY4
1 and YS2 are commonly formed.

Further, in order to reduce power consumption, the memory arrays M-ARY1, M-ARY2, M-AR
A sense amplifier circuit SAn corresponding to a memory array in which a memory cell to be selected among Y3 and M-ARY4 exists.
The NAND relationship between the memory array selection signals C1 and C2 generated by the selection circuits SL1 and SL2 and the activation signal SE is determined so that only the amplification operation (n is one of 1 to 4 in this example) is performed. The circuits control the sense amplifier driver circuits SAD1 and SAD2.

Recently, a non-addressed multiplex DRAM (reference document 1) and a low-voltage 64 Mbit D
In the RAM (Reference Document 2), besides a cross-coupled flip-flop sense amplifier circuit (MOS transistors Q8, Q9, Q10, Q11 in FIG. 13) which is often used as a conventional DRAM sense amplifier circuit, for example, a bit line In order to electrically separate D and / D from the common data lines CD1 and / CD1, the gate electrodes of the switches (MOS transistors) Q1 and Q2 receive the potentials of the bit lines D and / D, and the switches (MOS transistors) The ground line Vss connected to Q3 and the common data lines CD1, / CD1
Are connected via switches Q1, Q2 and the on-resistance of switch Q3, and a sense amplifier circuit of a type of reading is added.

The background of the introduction of this technology is that the common data line C
While the floating capacitance of D1 and / CD1 increases due to the higher integration of the DRAM, the current driving capability of the MOS transistors Q8, Q9, Q10, and Q11 of the sense amplifier circuit SA1 decreases due to the lower voltage. Therefore, if the bit lines D, / D and the common data lines CD1, / CD1 are connected via the switches before the bit lines D, / D are sufficiently amplified, the data on the bit lines will be crushed. There is a problem. Therefore, it was necessary to electrically separate the bit lines D and / D from the common data lines CD1 and / CD1 for reading.

However, as described above, a plurality of memory arrays M are provided by the common column address decoder YDCR.
-ARY1, M-ARY2, M-ARY3, M-ARY
4, when the selection signal lines YS1 and YS2 of the bit lines D and / D (data lines) are formed, the unselected memory arrays, for example, M-ARY2
Are connected to the respective common data lines CD2, / CD2 and the ground line Vss.

At this time, common data lines CD2, / CD2
Holds a potential equal to or higher than the half precharge level due to the precharge by the precharge circuit LOD2, so that the common data lines CD2, / CD
2 greatly fluctuates. As a result, the precharge circuit LOD2 for the non-selected memory array M-ARY2 to recharge the common data lines CD2 and / CD2 and the switch Q1 of the sense amplifier circuit SA2 for the non-selected memory array M-ARY2 , Q2, and Q3, a through current flows to the ground line Vss, which causes a problem in current consumption.

Reference 1: K. YANAGISAWA
et al. , 1989 ESC IRC, PP. 184
-187 2: Y. NAKAGOME et al. , 1990
SYMPOSIUM ON VLSI CIRCUIT
S, PP. 17-18 Although the order of the description will be changed, the circuit shown in FIG. 13 which is also used in the circuit of the embodiment of the present invention which will be described later will be described.

PC1 and PC2 are precharge circuits for equalizing and precharging the bit lines D and / D.
Half precharge is realized. SW1 and SW2 are connected to the decode lines X00 and X01 based on the row address and RAS.
Is a selection circuit that generates memory array selection signals C1 and C2 determined by the NAND relationship with the internal signal RAS1. SAD1 and SAD2 are sense amplifier circuits SA1 and S
The sense amplifier driver circuit is controlled by an activation signal of a selective sense amplifier determined by a relationship between the activation signal SE of A2 and the NAND of the memory array selection signals C1 and C2.

Sense amplifier driver circuits SAD1, SA
D2 includes sense amplifier circuits SA1, S
A2 also includes a circuit for precharging the common source lines NS1, PS1, NS2, and PS2 of the A2.
It is controlled by the same control signals PRC1 and PRC2 as those of the precharge circuits PC1 and PC2 for equalizing and precharging / D.

Rwc is a main amplifier circuit MA1, MA2
Signal for activating main amplifier circuits MA1 and MA2 to which signals of common data lines CD1, / CD1, CD2 and / CD2 are inputted in a read cycle in the operation of the DRAM. But also. This timing signal 16 is not activated during a write cycle.

WKCT1 and WKCT2 are write circuits, each of which has a common data line CD1, / CD1, CD
1, a write data line WD provided separately from CD2.
1, / WD1, WD2, / WD2 have their outputs connected. The write timing signal WCL is generated by an external signal / WE (write enable signal).

[0020]

However, in the conventional example, as described above, the common column address decoder YD
The plurality of memory arrays M-ARY1 and M-A are determined by CR.
When the selection signals YS1 and YS2 of the bit lines D and / D (data lines) in RY2, M-ARY3, and M-ARY4 are formed, the unselected memory arrays, for example, M-ARY2 are also used in the unselected memory arrays. The respective switches Q1, Q2, Q3 provide respective common data lines CD.
2, / CD2 and the ground line Vss.

At this time, the common data lines CD2, / CD
2 holds the potential of the half precharge level or higher by the precharge circuit LOD2, so that the potential level of the common data lines CD2 and / CD2 greatly fluctuates. As a result, the ground line V via the precharge circuit LOD2 of the unselected memory array for re-precharging the common data line and the transistors Q1, Q2, Q3 of the unselected memory array.
A through current flows through ss, which is a problem in terms of current consumption.

Accordingly, an object of the present invention is to provide a dynamic RAM capable of preventing a through current flowing between a precharge circuit of a common data line of a non-selected memory array and a ground line and reducing power consumption. It is to be.

[0023]

According to a first aspect of the present invention, there is provided a dynamic RAM in which a plurality of memory cells each including an address selection transistor and an information storage capacitor are arranged in a matrix at intersections of bit lines and word lines. There are a plurality of memory arrays, a first precharge circuit for precharging the bit lines to a first precharge potential, and a memory cell to be selected substantially corresponding to an address among the plurality of memory arrays. Line selection circuit that performs a word line selection operation only on a memory array to be connected, and an amplification operation of a signal of a bit line connected to the memory cell connected to the word line selected by the word line selection circuit And a selection circuit that selects the sense amplifier circuit corresponding to the selected word line. A common source line for supplying respectively the power supply voltage and the ground voltage as the operating voltage required for the amplification operation in the selection period of the sense amplifier circuit, wherein the non-selection period of the sense amplifier circuit, the common source line, respectively the second and third A second precharge circuit for precharging to a precharge potential of the plurality of memories;
Output common data line select signal to array
Comprising a column decoder, a first switch controlled by said common data line selection signal, and a second pair of switches connected in series in common with the first switch, the said first switch A common source line of the sense amplifier circuit is connected, a common data line pair is connected to the second switch pair, and the second switch pair is turned on by the potential of the bit line pair of the plurality of memory arrays. The resistance is controlled, and the bit line pair and the common data line pair are connected so as to be always electrically separated from each other.

A dynamic RAM according to claim 2
A plurality of memory arrays each including a plurality of memory cells each including an address selection transistor and an information storage capacitor arranged in a matrix at an intersection of a bit line and a word line; A first precharge circuit for precharging a word line, and a word for performing a word line selecting operation only on a memory array in which a memory cell substantially to be selected corresponding to an address exists among the plurality of memory arrays. It is connected to the line selection circuit, the word line selected by the word line selection circuit
A sense amplifier circuit for amplifying a signal of a bit line to which the selected memory cell is connected, a selection circuit for selecting the sense amplifier circuit corresponding to the selected word line, and a selection of the sense amplifier circuit A common source line for supplying a power supply voltage and a ground voltage as operating voltages necessary for an amplification operation in a period, and a common source line for a second period in a non-selection period of the sense amplifier circuit.
And a second precharge to a third precharge potential
And a precharge circuit for the plurality of memory arrays.
Column decoder that outputs a common data line selection signal
And da, the first controlled by the common data line selection signal
And a second pair of switches respectively connected in series with the first pair of switches. A common source line of the sense amplifier circuit is commonly connected to the second pair of switches. A common data line pair connected to the first switch pair, an ON resistance of each of the second switch pair is controlled by a potential of a bit line pair of the plurality of memory arrays, and The pair and the common data line pair are connected so as to be always electrically separated from each other.

[0025]

According to the present invention, the common source line and the common data line of the sense amplifier circuit provided corresponding to the memory array have the column decode lines (YS1, Y2).
The first switch (Q3), which is turned on by the common data line selection signal in S2), and the bit line are coupled via the second switch (Q1, Q2) connected by a gate.

In the selected memory array, the sense amplifier circuit is activated, and for example, the potential of the common source line (NS1) of the N-channel MOS transistor falls from the half precharge level to the Vss level, so that the common data line The potential of (CD1, / CD1) is also
It falls together while being controlled by the on-resistance of the second switch (Q1, Q2) controlled by the potential of the bit line (D, / D).

On the other hand, in a non-selected memory array,
Since the sense amplifier circuit is not activated, the common source line (NS1) is maintained at the same potential as the precharge level of the common data line, for example, the half precharge level, so that the column decode lines (YS1, YS2)
The first switch (Q3) and the bit lines (D, / D) which are turned on by the gates are connected to the common data lines (CD1, / D2) via the second switches (Q1, Q2) connected by gates.
Even if it is coupled to CD1), since it has the same potential, no through current flows as in the related art.

[0028]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A circuit configuration and operation of a read circuit in a dynamic RAM according to an embodiment of the present invention will be described with reference to FIGS. Since the circuit of this embodiment has basically the same configuration as the circuit of the conventional example shown in FIGS. 13 to 15, the same components are denoted by the same reference numerals and detailed description is omitted.

First Embodiment FIG. 1 is a circuit diagram of a read circuit of a dynamic RAM according to a first embodiment of the present invention and its peripheral portion, and FIG. 2 is a diagram showing the sense amplifier circuit SA1 and its peripheral portion in FIG. FIG. 3 is an enlarged view, and FIG. 3 is a circuit diagram of another example of the sense amplifier circuit SA1 and its peripheral portion in FIG.
FIG. 4 shows a time chart of each part in FIG.

The most characteristic feature of the first embodiment shown in FIGS. 1 to 4 is, for example, a sense amplifier circuit SA.
This is the point where one common source line NS1, PS1 is connected to a first switch (MOS transistor) Q3 controlled by a column decode line (bit line D, / D selection signal line) YS1. In FIG. 2, the switch Q3 is of the N-channel type and is connected to the common source line NS1. In FIG. 3, the switch Q3 is a P-channel type,
Connected to common source line PS1.

As shown in FIG. 1, switch Q3 is a second switch (MOS transistor) Q1 connected to bit lines D and / D by gate electrodes and connected to common data lines CD1 and / CD1 by drain electrodes. , Q2, the common data lines CD1, / CD1 and the common source line NS are controlled by the on-resistances of the switches Q1, Q2 controlled by the potentials of the bit lines D, / D.
1, which functions as a switch for controlling whether or not connection with PS1 is performed.

With the above configuration, this dynamic R
The AM performs the following read operation as shown in FIG. First, for example, the memory arrays M-ARY1, M-ARY
Sense amplifier circuit SA provided corresponding to ARY2
1, SA2 common source lines NS1, PS1, NS2, P
S2 and common data lines CD1, / CD1, CD2, / CD
2 are coupled through switches Q1 and Q2 connected by gates to a switch Q3 turned on by column decode lines YS1 and YS2 and bit lines D and / D. For example, in the M-AR1), the sense amplifier circuit SA1 is activated by the activation signal SE1, and for example, the N-channel MOS
Since the potential of the common source line NS1 of the transistor decreases from the half precharge level to the Vss level, the potential of the common data lines CD1, / CD1 is also controlled by the potential of the bit lines D, / D (M-ARY1). The switches Q1 and Q2 fall together while being controlled by the on-resistance of the switches Q1 and Q2.

On the other hand, a non-selected memory array (for example, M
In -AR2), since the sense amplifier circuit SA2 is not activated by the activation signal SE2, the common source line NS2 is maintained at the same potential as the precharge level of the common data lines CD2, / CD2, for example, the half precharge level. The switch Q3 is turned on by the column decode line YS1, and the bit lines D and / D (M-ARY2)
Means that the common data lines CD2 and / CD2 are coupled via the switches Q1 and Q2 connected by the gate,
Since the potentials are the same, a through current does not flow unlike the related art.

FIG. 4 shows common data lines CD1, / CD
1, CD2, / CD2 and common source lines NS1, PS1,
The precharge potentials of NS2 and PS2 are described as 1/2 Vcc, but this is not a limitation, and the common data lines CD1, / CD1, CD2, / CD2 and the common source lines NS1, PS1, NS2. Any potential may be used as long as PS2 and the precharge potential are substantially the same.

As described above, the second switches Q1 and Q2 are MOS
Although the case of a transistor has been described, the present invention is not limited to a MOS transistor, but may be anything as long as the on-resistance of the switch is controlled by the potential of the bit lines D and / D. FIG. 3 shows an example in which the switches Q1 and Q2 are configured by bipolar transistors. Bit line D, /
By connecting D and the base electrode, the on-resistance of the switch is controlled by the potential of the bit lines D and / D.

Second Embodiment FIG. 5 is a circuit diagram of a sense amplifier circuit and its peripheral portion in a dynamic RAM according to a second embodiment of the present invention, and FIG. 6 is a time chart similar to FIG. Since the circuit is basically the same as the circuit of the first embodiment shown in FIG. 2, only different circuit components will be described.

The difference is that the switches Q1, Q2 connected to the bit lines D, / D and the gate electrode and the switch Q3 controlled by the column decode line YS1 are constituted by NMOSFETs in the first embodiment. Is N
While the common source line PS1 of the PMOS transistor is connected to the common source line NS1 of the sense amplifier circuit SA1 of the MOS transistor in the second embodiment.
And common data lines CD1 and / CD1 are coupled by P-channel switches Q1, Q2 and Q3.

As for the operation, as shown in FIG. 6, the operation is basically the same as that of FIG.
Only different parts will be described. The common data lines CD1, CD1,
As can be seen from the waveforms of / CD1, CD2 and / CD2, the switches Q1 and Q2 receive the data of the bit lines D and / D and the ON resistance is controlled, and the switches Q1 and Q2 are connected to the common data lines CD1 and / CD2.
It can be seen that the potentials of CD1, CD2, / CD2 fluctuate from the 1/2 Vcc precharge level toward the potential of the common source line PS1.

The effects of the second embodiment are as follows. In the selected memory array (for example, M-ARY1) described in the point of the effect of the first embodiment, the sense amplifier circuit SA1 is activated by the activation signal SE1, and the common source of the P-channel MOS transistor, for example. Line PS1 goes from half precharge level to V
Since the potential increases toward the cc level, the potentials of the common data lines CD1 and / CD1 are also changed to the bit lines D and / D (M−
Switches Q1, Q2 controlled by the potential of AR1)
Rise together while being controlled by the on resistance.

On the other hand, unselected memory arrays (for example, M
In (−ARY2), since the sense amplifier circuit SA2 is not activated by the activation signal SE2, the common source line PS2 is maintained at the same potential as the precharge level of the common data lines CD2 and / CD2, for example, the half precharge level. Therefore, it is assumed that the switch Q3 turned on by the column decode line YS1 and the bit lines D and / D are connected to the common data lines CD2 and / CD2 via the switches Q1 and Q2 connected by gates. Since they have the same potential, no through current flows as in the related art.

The effects described above are, of course,
In the second embodiment, the following effects can be further expected. In order to advance the timing at which the memory cell switch Qm is turned on with respect to the rise of the word lines W1 and W2, the precharge level of the bit lines D and / D is set to the normal 1
/ 2Vcc, for example, 1 / 3Vcc, 1 /
When the level is set to 4 Vcc, the operating voltage of the NMOS transistor latch circuit in the CMOS sense amplifier circuits SA1 and SA2 becomes extremely low, and normal operation becomes impossible. Therefore, the function of the PMOS transistor latch circuit is mainly performed.

On the other hand, when the potentials of the bit lines D and / D are low as described above, the PMOS transistors whose switches Q1 and Q2 have a large gate-source voltage are more advantageous in terms of current drivability. The common data line C is connected via the switches Q1, Q2, Q3 of such PMOS transistors.
When transmitting data to D1, / CD1, switch Q3
Is not ground potential, but Vc
The potential change of the common data lines CD1, / CD1 is larger when the potential is c.

Third Embodiment FIG. 7 is a circuit diagram of a sense amplifier circuit of a dynamic RAM according to a third embodiment of the present invention and its peripheral portion. The most characteristic point of the third embodiment shown in FIG.
Common data lines CD1, / CD1 and column decode line YS
This is a point where the switch Q30 and the pair of switches Q31 controlled by the switch 1 are connected.

As shown in FIG. 7, a pair of switches Q30 and Q31 are connected to switches Q1 and Q2 connected to bit lines D and / D by gate electrodes and connected to common data lines CD1 and / CD1 by drain electrodes. As can be seen from the connection in series, the common data lines CD1, / CD1 and the common source line NS1 are connected by the on-resistances of the switches Q1, Q2 controlled by the potentials of the bit lines D, / D. It functions as a switch for controlling whether or not.

With the above configuration, the following read operation is performed. Note that, since it is basically the same as that shown in FIG. 4, a time chart for explanation of the third embodiment is omitted. First, the common source lines NS1, PS1, NS2, PS2 and the common data line CD of the sense amplifier circuits SA1, SA2 provided corresponding to the memory array are provided.
Switches Q30, Q1 which are turned on by column decode lines YS1, YS2
31, and the bit lines D and / D are coupled via switches Q1 and Q2 connected by gates.

As a result, the selected memory array (for example, M
In (−ARY1), the sense amplifier circuit SA1 is activated by the activation signal SE1, for example, N
Since the potential of the common source line NS1 of the channel MOS transistor falls from the half precharge level to the Vss level, the potential of the common data lines CD1 and / CD1 also depends on the potential of the bit lines D and / D (M-ARY1). It falls together while being controlled by the on-resistance of the controlled switches Q1 and Q2.

On the other hand, unselected memory arrays (for example, M
In (−ARY2), since the sense amplifier circuit SA2 is not activated by the activation signal SE2, the common source line NS2 is maintained at the same potential as the precharge level of the common data lines CD1, / CD2, for example, the half precharge level. Even if switches Q30 and Q31 turned on by column decode line YS1 and bit lines D and / D are coupled to common data lines CD2 and / CD2 via switches Q1 and Q2 connected by gates, the same applies. Since it is a potential, a through current does not flow as in the related art.

The case where the switches Q1 and Q2 are MOS transistors has been described above. However, the present invention is not limited to MOSFETs, and any switch may be used as long as the ON resistance of the switches is controlled by the potential of the bit line. It is also possible to use a bipolar transistor because the on-resistance of the switch is controlled by the potential of the bit line by connecting the bit line and the base electrode.

Fourth Embodiment FIG. 8 is a circuit diagram of a sense amplifier circuit and its peripheral portion in a dynamic RAM according to a fourth embodiment of the present invention. This embodiment is basically the same as the circuit of the third embodiment shown in FIG. 7, and therefore only different parts of the circuit configuration will be described. The different parts are a pair of switches Q1 and Q2 connected to the bit lines D and / D by gate electrodes, and switches Q30 and Q31 controlled by a column decode line YS1.
Are configured by NMOS transistors in the first embodiment, and the switches Q30 and Q31 are connected to the common source line NS1 of the sense amplifier circuit SA1 of the NMOS transistors. On the other hand, in the fourth embodiment, PMOS
Transistor common source line PS1 and common data line CD
1 and / CD1 are connected by switches Q1, Q2, Q30, and Q31 each formed of a P-channel MOS transistor.

The operation time chart is basically the same as that shown in FIG. 6 and is therefore omitted, but only different parts will be described. The common data lines CD1, / in FIG.
As can be seen from the waveforms of CD1, CD2, and / CD2, the switches Q1,
The on-resistance of Q2 is controlled, and common data lines CD1, / C
It can be seen that the potentials of D1, CD2, / CD2 vary from the 1/2 Vcc precharge level toward the potential of the common source line PS1.

The effects of the fourth embodiment are as follows. In the selected memory array (for example, M-ARY1) described in the point of the effect of the first embodiment, the sense amplifier circuit SA1 is activated by the activation signal SE1, and the common source of the P-channel MOS transistor, for example. Line PS1 goes from half precharge level to V
Since the potential increases toward the cc level, the potentials of the common data lines CD1 and / CD1 are also changed to the bit lines D and / D (MA).
Switches Q1, Q2 controlled by the potential of RY1)
Rise together while being controlled by the on resistance.

On the other hand, a non-selected memory array (for example, M
In (−ARY2), since the sense amplifier circuit SA2 is not activated by the activation signal SE2, the common source line PS2 is maintained at the same potential as the precharge level of the common data lines CD2 and / CD2, for example, the half precharge level. Therefore, the pair of switches Q30 and Q31 turned on by the column decode line YS1 and the bit lines D and / D are coupled to the common data lines CD2 and / CD2 via the switches Q1 and Q2 connected by gates. Even if it does, the through current does not flow unlike the related art because it has the same potential.

The effects described above are, of course,
In the second embodiment, the following effects can be further expected. In order to advance the timing at which the memory cell switch Qm is turned on with respect to the rise of the word lines W1 and W2, the precharge level of the bit lines D and / D is set to the normal 1
/ 2Vcc, for example, 1 / 3Vcc, 1 /
When the level is set to 4 Vcc level, the CMOS sense amplifier circuit has an extremely low operating voltage of the NMOS transistor latch circuit, and cannot operate normally.
The operation of the OS transistor latch circuit is mainly performed.

On the other hand, when the potentials of the bit lines D and / D are low, the switches Q1 and Q2 are also more advantageous in terms of current drivability by using PMOS transistors having a large gate-source voltage. When data is transmitted to the common data lines CD1, / CD1 via the switches Q1, Q2, Q30, Q31 of the PMOS transistors, the potential of the power supply line connected to the switches Q1, Q2 is not the ground potential, The Vcc potential is applied to the common data line CD.
The potential change of 1, / CD1 is large.

Fifth Embodiment FIG. 5 is a circuit diagram of a precharge circuit of a dynamic RAM according to a fifth embodiment of the present invention and its peripheral portion, and FIG. 10 is a time chart similar to FIGS. Show. Fifth
Since this embodiment is basically the same as the first embodiment, only different parts of the circuit configuration will be described.

The different part is, for example, a common data line CD
1, / CD1 precharge circuit LOD1 and common source lines NS1, PS1 sense amplifier driver circuit SAD1
Of the precharge circuit. As can be seen by comparing the sense amplifier driver circuit SAD1 of FIG. 1 of the first embodiment with the sense amplifier driver circuit SAD1 of FIG. 9 of the fifth embodiment, the sense amplifier driver circuit SAD1 shown in FIG. The common source lines NS1 and PS1 of the NMOS transistor and the PMOS transistor constituting the sense amplifier circuit SA1 are both precharged to the same potential, but the sense amplifier driver circuit SAD1 shown in FIG.
Then, as shown in FIG. 10, the common source line NS1 of the NMOS transistor is precharged to the same potential (for example, 1/2 Vcc level) as the common data lines CD1 and / CD1, and the common source line PS1 of the PMOS transistor is set to the common data line. The precharge is performed to a potential different from that of the lines CD1 and / CD1.

The different potentials are, for example, bit lines D and / D
Is lower than the precharge level (１ ／ Vcc). Here, the method of generating the potential is shown in FIG. 9 in the case of resistance division, but the potential level of, for example, Vss + | Vtp | may be generated using the threshold voltage Vt of the transistor. good. However, 1/2 Vcc>
| Vtp |. Here, Vtp is the threshold voltage of the PMOS transistor.

If the precharge level of the common source line PS1 can be set lower than the potential of the bit lines D and / D as described above, the following effects can be obtained. Future DR
When the operating voltage of the AM is reduced due to device reliability, power consumption, and system requirements, the components of the sense amplifier circuits SA1 and SA2 shown in FIG. Is the MO of the P channel
Threshold voltage | Vts of S transistors Q10 and Q11
p | needs to be very small (| Vtsp | <-0.1
V).

At this time, the common source line P
When S1 is precharged to the same potential as the bit lines D and / D, the MOS transistors Q10 and Q11 become | Vts
Since p | is low, it is turned on. Then, there is a problem that the sense amplifier circuit starts an amplification operation before reading information from the memory cell to the bit lines D and / D, and a normal read operation cannot be performed. This problem is caused by the precharge level of the bit lines D and / D (1/2 V
cc), if the common source line PS1 is precharged to a lower level, the MOS transistors Q10, Q11
Is not turned on even if the threshold voltage Vtsp is low, so it is clear that the circuit of this embodiment shown in FIG. 9 can solve the problem.

Sixth Embodiment FIG. 11 shows a dynamic RAM according to a sixth embodiment of the present invention.
FIG. 1 shows a circuit diagram of a precharge circuit and a peripheral portion thereof.
FIG. 12 shows a time chart similar to FIGS. 4, 6, and 10. Since the sixth embodiment is basically the same as the first embodiment, only different parts of the circuit configuration will be described.

The different parts are the common data lines CD1, / C
D1 precharge circuit LOD1 and common source line NS
1, PS1 is a precharge circuit portion of the sense amplifier driver circuit SAD1. As can be seen by comparing the sense amplifier driver circuit SAD1 of FIG. 1 of the first embodiment with the sense amplifier driver circuit SAD1 of FIG. 11 of the sixth embodiment, the sense amplifier driver circuit SAD1 shown in FIG. NM constituting sense amplifier circuit SA1
Although both the common source lines NS1 and PS1 of the OS transistor and the PMOS transistor are precharged to the same potential, in the sense amplifier driver circuit SAD1 shown in FIG. 11, the common source line PS1 of the PMOS transistor is shared as shown in FIG. Although the data lines CD1 and / CD1 are precharged to the same potential (for example, 1/2 Vcc level), the NMOS transistor common source line NS1 is precharged to a different potential from the common data lines CD1 and / CD1.

The different potentials are, for example, bit lines D and / D
Is higher than the precharge level (１ ／ Vcc). Here, the method of generating the potential is as shown in FIG.
Although the case of resistance division is shown, a potential level of, for example, Vcc + Vtn may be generated using the threshold voltage Vt of the transistor. However, 1/2 Vcc> V
tn. Here, Vtn is a threshold voltage of the NMOS transistor.

If the precharge level of the common source line NS1 can be set higher than the potential of the bit lines D and / D as described above, the following effects can be obtained. Future DR
When the operating voltage of the AM is reduced due to device reliability, power consumption, and system requirements, the components of the sense amplifier circuits SA1 and SA1 shown in FIG. It is necessary to make the threshold voltage Vtsn of the NMOS transistors Q8 and Q9 extremely small (Vtsn <−0.1 V).

At this time, the common source line N
If S1 is precharged to the same potential as bit lines D and / D, MOS transistors Q8 and Q9 are turned on because threshold voltage Vtsn is low. Then, there is a problem in that the sense amplifier circuit starts an amplification operation before reading information from the memory cell to the bit line, and a normal read operation cannot be performed.

The problem is that if the common source line NS1 is precharged to a level higher than the precharge level (1/2 Vcc) of the bit lines D and / D, the MOS transistors Q8 and Q9 will have the threshold voltage Vtsn It is apparent that the circuit can be solved by the circuit of this embodiment shown in FIG.

[0066]

According to the dynamic RAM of the present invention, the first and second switches are connected in series between the common data line and the common source line, so that no extra circuit is added. However, the common column decode line can prevent a through current from flowing between the precharge circuit of the common data line of the non-selected memory array and the ground line or the power supply line, thereby reducing power consumption. In a read circuit of a high-density, high-speed DRAM, the practical effect is great.

[Brief description of the drawings]

FIG. 1 is a dynamic RAM according to a first embodiment of the present invention;
FIG. 2 is a circuit diagram showing a configuration of a readout circuit and peripheral portions thereof.

FIG. 2 is a circuit diagram of a sense amplifier circuit and its peripheral portion in FIG.

FIG. 3 is a circuit diagram of another example of the sense amplifier circuit and its peripheral portion in FIG. 1;

FIG. 4 is a time chart illustrating the operation of the circuit of FIG. 1;

FIG. 5 is a dynamic RAM according to a second embodiment of the present invention;
FIG. 3 is a circuit diagram showing a configuration of a sense amplifier circuit and its peripheral portion in FIG.

FIG. 6 is a time chart showing the operation of the second embodiment.

FIG. 7 is a dynamic RAM according to a third embodiment of the present invention;
FIG. 3 is a circuit diagram showing a configuration of a sense amplifier circuit and its peripheral portion in FIG.

FIG. 8 is a dynamic RAM according to a fourth embodiment of the present invention;
FIG. 3 is a circuit diagram showing a configuration of a sense amplifier circuit and its peripheral portion in FIG.

FIG. 9 is a dynamic RAM according to a fifth embodiment of the present invention;
FIG. 2 is a circuit diagram showing a configuration of a precharge circuit and its peripheral portion in FIG.

FIG. 10 is a time chart showing the operation of the fifth embodiment.

FIG. 11 is a dynamic RA according to a fifth embodiment of the present invention;
FIG. 3 is a circuit diagram illustrating a configuration of a precharge circuit and peripheral portions of the precharge circuit in M.

FIG. 12 is a time chart showing the operation of the sixth embodiment.

FIG. 13 is a circuit diagram of a conventional dynamic RAM.

FIG. 14 is a block diagram of a conventional dynamic RAM.

FIG. 15 is a circuit diagram of the sense amplifier circuit of FIG. 13 and its peripheral portion.

[Explanation of symbols]

Q1, Q2 Second switch Q3 First switch Q30, Q31 First switch M-ARY1 to M-ARY4 Memory array YDCR Column address decoder SW1 to SW4 selection circuit XDCR1 to XDCR4 Row address decoder (word line selection circuit) SA1 ＳＡSA4 Sense amplifier circuit MA1, MA2 Main amplifier circuit LOD1, LOD2 Precharge circuit SAD1, SAD2 Sense amplifier driver circuit (precharge circuit) PC1 to PC4 Precharge circuit Qm Address selection transistor Cm Information storage capacitor D, / D bit Line W1, W2 Word line NS1, PS1, NS2, PS2 Common source line CD1, / CD1, CD2, / CD2 Common data line

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI H01L 27/108 G11C 11/34 311 H01L 27/10 681F

Claims (12)

(57) [Claims] A plurality of memory cells each comprising a plurality of memory cells each including an address selection transistor and an information storage capacitor arranged in a matrix at an intersection of a bit line and a word line; A first precharge circuit for precharging to a precharge potential, and an operation of selecting a word line only for a memory array of the plurality of memory arrays in which a memory cell to be selected substantially exists corresponding to an address. A sense line circuit for amplifying a signal of a bit line connected to the memory cell connected to the word line selected by the word line selection circuit; and a selected word line. A selection circuit that selects the sense amplifier circuit in response to the Each power supply voltage and the ground voltage as Do operating voltage
A common source line for supplying, in a non-selection period of the sense amplifier circuit, the common source line and the second precharge circuit for precharging the second and third precharge potential respectively, to said plurality of memory arrays Common data line selection signal
Comprising a common column decoder for outputting a No., a first switch controlled by said common data line selection signal, and a second pair of switches connected in series in common with the first switch, the second A common source line of the sense amplifier circuit is connected to one switch, a common data line pair is connected to the second switch pair, and the second switch pair is a bit line of the plurality of memory arrays. The on-resistance is controlled by the potential of the pair,
A dynamic RAM, wherein the bit line pair and the common data line pair are connected so as to be always electrically separated from each other. 2. A memory array comprising a plurality of memory cells each comprising an address selection transistor and an information storage capacitor arranged in a matrix at an intersection of a bit line and a word line; A first precharge circuit for precharging to a precharge potential, and a word line selecting operation only for a memory array in which there is a memory cell to be selected substantially corresponding to an address among the plurality of memory arrays A sense line circuit for amplifying a signal of a bit line connected to the memory cell connected to the word line selected by the word line selection circuit; and a selected word line. A selection circuit that selects the sense amplifier circuit in response to the A common source line for supplying a power supply voltage and a ground voltage, respectively, as operating voltages; and a second for precharging the common source line to a second and a third precharge potential during a non-selection period of the sense amplifier circuit. A pair of a precharge circuit, a common column decoder that outputs a common data line selection signal to the plurality of memory arrays, a first switch controlled by the common data line selection signal, and a first switch And a pair of second switches connected in series, respectively. A common source line of the sense amplifier circuit is commonly connected to the pair of second switches, and common to the pair of first switches. A pair of data lines are connected to each other, and an ON resistance of each of the pair of second switches is controlled by a potential of a pair of bit lines of the plurality of memory arrays. It is,
A dynamic RAM, wherein the bit line pair and the common data line pair are connected so as to be always electrically separated from each other. 3. The common data line is connected to an input terminal of a main amplifier circuit for transmitting information from the bit line when selected, and detecting and amplifying the information. 2. A circuit for precharging to the precharge potential of claim 1.
Alternatively, the dynamic RAM according to claim 2. 4. A sense amplifier circuit includes a CMOS inverter circuit in a latch form, wherein the sources of an N-channel MOSFET and a P-channel MOSFET constituting the CMOS inverter circuit are shared, and during the amplification operation period, A ground voltage is supplied to a common source line of the N-channel MOSFET, a power supply voltage is supplied to a common source line of the P-channel MOSFET,
3. The dynamic RAM according to claim 1, wherein the common source line is precharged to the second and third precharge potentials during the non-selection period. 5. The semiconductor device according to claim 1, wherein the second and third precharge potentials are the same, and the potential is substantially the same as a fourth precharge potential which is a precharge potential of the common data line. The dynamic RAM according to claim 1. 6. The second and third precharge potentials are different potentials, and one of the potentials is substantially the same as the fourth precharge potential which is a precharge potential of the common data line, and the potential is the same. 2. The dynamic RAM according to claim 1, wherein the common source line on the side precharged to the first switch is connected to the first switch. 7. The second and third precharge potentials are different potentials, and one of the potentials is substantially the same as a fourth precharge potential which is a precharge potential of a common data line, and the potential is the same. 3. A dynamic RAM according to claim 2, wherein a common source line on the side precharged to said second switch is connected to said second switch. 8. The dynamic RA according to claim 1, wherein a common source line of the N-channel MOSFET forming the sense amplifier circuit is connected to the first switch.
M. 9. The dynamic RA according to claim 2, wherein a common source line of the N-channel MOSFET forming the sense amplifier circuit is connected to the second switch.
M. 10. The dynamic resistor according to claim 1, wherein a common source line of the P-channel MOSFET constituting the sense amplifier circuit is connected to the first switch.
AM. 11. The dynamic resistor according to claim 2, wherein a common source line of the P-channel MOSFET constituting the sense amplifier circuit is connected to the second switch.
AM. 12. The precharge circuit connected to the common data line is turned off only during an activation period of a main amplifier circuit in a memory array selection period. Dynamic R described
AM.