JPH01276486A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To decrease energy consumption by providing two pairs of substrate bias voltage generating circuits and controlling operation in correspondence to a non-selecting condition, etc. CONSTITUTION:Two pairs of substrate bias voltage generating circuits 10 and 20 and for the circuit 10, the oscillation stop of a ring oscillator 11 is stopped through a NOR gate 16, to which a low address strobe RAS is supplied. Then, the circuit 10 is operated only when a semiconductor storage is in the non- selecting condition and the energy consumption can be reduced in a selecting condition. On the other hand, for the circuit 20, the stop of a ring oscillator 21 is samely controlled by a NOR gate 22 to be controlled by a NOR gate 29, to which the strobe RAS is added. Then, the circuit 20 is operated until a substrate voltage arrives at a prescribed value and after the arrival, the operation is stopped in the non-selecting condition. Then, the energy consumption is reduced in the non-selecting condition as well. Thus, the semiconductor storage device of the small energy consumption can be obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and particularly to a semiconductor memory device that can generate a substrate bias voltage with low power consumption in a dynamic semiconductor memory device.

[Prior Art] In recent years, the popularity of personal computers has become remarkable, and in particular, the demand for portable personal computers has increased recently.

Storage devices used in portable personal computers are required to have low power consumption. As such a memory device, a dynamic type semiconductor memory device or a static type semiconductor memory device is usually used. this house,
In a dynamic semiconductor memory device, power consumption in a circuit that generates a substrate bias voltage, especially in a non-selected state, accounts for most of the total power consumption, so it is necessary to reduce this power consumption.

In order to reduce the power consumption in such a bias voltage generation circuit, for example, 5ato.

et al, A 20ns St
aticColumn IMb DRAM
in CMOS Technology,”1
985 1EEE 15SCCDig, Tech
, Pap, 254-255, 2
A method has been devised in which different types of substrate bias generation circuits are provided, one bias circuit with a low bias capacity is operated all the time, and the other bias circuit with a high bias capacity is operated intermittently depending on the substrate potential.

FIG. 4 is an electrical circuit diagram showing an example of the above-mentioned conventional substrate bias voltage generating circuit. In FIG. 4, the first substrate bias voltage generation circuit 1 includes a ring oscillator 11, an inverter 12, a capacitor 13, and n-channel transistors 14 and 15. The output of ring oscillator 11 is inverted by inverter 12 and applied to the gate and drain of n-channel transistor 14 via capacitor 13 as well as to the drain of n-channel transistor 15. The source of n-channel transistor 14 is grounded, and the gate and source of n-channel transistor 15 are connected.

On the other hand, the second substrate bias voltage generation circuit 2 includes a ring oscillator 21, a NOR gate 22, 29, and an inverter 23.
．． 24, capacitor 25, and n-channel transistor 26
．． 27 and a substrate potential detection circuit 28. The output of the ring oscillator 21 is given to one input terminal of the NOR gate 22, and the output of the NOR gate 22 is given to the ring oscillator 21 and the inverter 2.
3.24 and the gate and drain of the n-channel transistor 26 via the capacitor 25, and further n
Applied to the drain of channel transistor 27. n
The source of the channel transistor 26 is grounded, the gate of the n-channel transistor 27 is connected to the source, and further connected to the output of the first substrate bias voltage generation circuit 1. The substrate potential detection circuit 28 detects the potential of a semiconductor substrate (not shown), and its detection output N is NO.
It is applied to one input terminal of the R gate 29. The other input terminal of the NOR gate 29 is supplied with a RAS signal indicating the selected state. The output of this NOR gate 29 is the aforementioned NOR
It is applied to the other input terminal of gate 22.

FIG. 5 is a waveform diagram for explaining the operation of the conventional substrate bias voltage generation circuit shown in FIG. 4.

First, the operation of the first substrate bias voltage generation circuit 1 will be explained with reference to FIGS. 5 and 4. Step 1: The output of the ring oscillator 11 is at the ground potential GND, and the output of the inverter 12 is at the power supply potential Vcc.
At this point, the voltage at node N attempts to rise to power supply potential Vcc due to capacitive coupling by capacitor 13.

However, if the voltage at node NA is n-channel transistor 1
When the voltage rises to the threshold voltage Vτ2 of 4, the n-channel transistor 14 becomes conductive and further voltage rise is suppressed, thereby maintaining the node N at the voltage Vτ2.

Next, in step 2, the output of the ring oscillator 11 rises to the power supply potential Vcc, and the output of the inverter 12 becomes the ground potential GND.
try to become However, the voltage at node NA is the substrate voltage v! When the voltage becomes smaller than the voltage (VBB - VT I ) obtained by subtracting one threshold voltage of the n-channel transistor 15 from lVB, the n-channel transistor 15 becomes conductive and the voltage at the node N^ does not become so low.

When step 1 and step 2 are performed once each, the voltage at node NA and substrate voltage VaB decrease. In addition,
The degree of this is determined by the ratio of the capacitance CA of the capacitor 13 to the load capacitance of the board. Furthermore, when step 1 and step 2 are repeated several times, the voltage at node NA becomes voltage (V7
2-Vc c) and voltage vT2, and the substrate voltage Vaa becomes the final Niha voltage (VT 2 Vc c
+VT + ) I: Getting closer.

Next, the operation of the second substrate bias voltage generation circuit 2 will be explained. In the first substrate bias voltage generation circuit 1, since the ring oscillator 11 is constantly operating,
At the node NA, a voltage vA having the waveform shown in FIG.
1 is controlled. That is, when the voltage at the node Nc is at the "L" level, the output of the NOR gate 22 is at the H level, so the ring oscillator 21 oscillates.
When the voltage at node Nc is at the "H" level, the output of the NOR gate 22 is at the "L" level, so the ring oscillator 21 does not oscillate. Moreover, the voltage of node Nc is
Furthermore, it is also controlled by a NOR gate 29. That is, when RAS is at the "H" level indicating a selected state, the voltage at the node Nc is at the "L" level regardless of the level of the output ND of the substrate potential detection circuit 28. R.A.
When the S signal is at the "L" level indicating a non-selected state, and when the level of the output No of the substrate potential detection circuit 28 is at the "H" level, the node N'. The voltage becomes ``L lebel,''
When the level of the output No is at the II L 11 level, the voltage at the node NC becomes the "H# level. The substrate potential detection circuit 28 constantly monitors the level of the substrate voltage VBa, and 11 Outputs a HII level signal, and when it reaches a predetermined level, outputs an "L" level signal.

Note that the operation when the ring oscillator 21 is oscillating is almost the same as the operation of the first substrate bias voltage generation circuit 1, but since it is configured to have a higher bias capability, it can oscillate more rapidly. Therefore, the substrate voltage Vaa can be lowered.

Node NA in first substrate bias voltage generation circuit 1
FIG. 5 shows the voltage level waveform of node N[1 of second substrate bias voltage generating circuit 2 together with selection control signal RAS of this dynamic semiconductor memory device. That is, since the ring oscillator 11 is always in operation, the node N of the first substrate bias voltage generation circuit 1.

The voltage V^ at is as shown in FIG. 5(b). However, since the ring oscillator 21 stops oscillating when the level of the substrate voltage V6 reaches a predetermined level when the storage bag device is not selected, the node in the second substrate bias voltage generation circuit 2 N[1
The voltage VB becomes as shown in FIGS. 5(c) and 5(d), and the power consumption in the non-selected state is reduced. Note that if the level of the substrate voltage Vaa becomes shallower than the predetermined level for some reason, the ring oscillator 21 oscillates again to rapidly lower the substrate voltage Vaa to the predetermined level.

FIG. 6 is an electric circuit diagram showing an example of the substrate potential detection circuit shown in FIG. 4. In FIG. 6, power supply potential Vcc
A p-channel transistor 281 and n-channel transistors 9282 and 283 are connected in series between V6 and substrate voltage V6[1. That is, p-channel transistor 281
The drain is given the power supply potential VCC, and the source is n
connected to the drain of channel transistor 282, n
The source of channel transistor 282 is connected to the drain and gate of n-channel transistor 283. The source of the n-channel transistor 283 has a substrate voltage Vaa.
is given. The gates of p-channel transistor 281 and n-channel transistor 282 are grounded. Node N, which is the connection point between the source of p-channel transistor 281 and the drain of n-channel transistor 282
1 is connected to the input of an inverter 284, and the output of the inverter 284 is connected to the fourth
It is connected to the other input terminal of the NOR gate 29 shown in the figure.

If the respective threshold voltages of n-channel transistors 282 and 283 are VD 2 + ■03, then v,,
a)-(Vo2+vo3), the n-channel transistor 282 is non-conductive, and the level of the node N1 becomes "H" level because the p-channel transistor 281 is conductive. This node N1
Since the voltage is outputted via the inverters 284 and 285, the output NO becomes "H" level. Next, V[lB
≦-(VD2+V.

, ), the n-channel transistor 282 becomes conductive. At this time, the p-channel transistor 281
By appropriately selecting the ratio between the size of the n-channel transistor 282 and the size of the n-channel transistor 282, the level of the node N1 can be set to the "L" level. That is, the output No becomes "L" level.

[Problems to be Solved by the Invention] As mentioned above, the conventional semiconductor memory device has two types of substrate bias voltage generation circuits 1 and 2, and when the memory device is selected, both of them are activated. Since the substrate bias voltage generating circuit 1.2 operates, there is a problem in that power consumption increases.

Therefore, the main object of the present invention is to develop a semiconductor device that can generate a substrate bias voltage with low power consumption by stopping the operation of one substrate bias voltage generation circuit when a storage device is selected. It is to provide a storage device.

[Means for Solving the Problems] The present invention includes a semiconductor substrate, first and second bias means for applying a bias voltage to the semiconductor substrate,
a substrate potential detection means for detecting a change in bias potential of a semiconductor substrate, the first bias means being activated in a non-selected state and having a higher bias capability than the second bias means; The second bias means supplies a bias voltage to the substrate until the substrate potential detection means detects that the substrate potential has reached a predetermined level, and the second bias means supplies a bias voltage to the substrate until the substrate potential reaches a predetermined level. After that, when the selection signal becomes a non-selected state, the supply of bias voltage is stopped.

[Operation] In the semiconductor memory device according to the present invention, since the operation of one of the bias means is stopped when the memory device is selected, a substrate bias voltage can be generated with less power consumption.

[Embodiment of the Invention] FIG. 1 is a schematic block diagram showing the main parts of a semiconductor memory device to which an embodiment of the invention is applied.

First, with reference to FIG. 1, the configuration of a portion related to substrate bias in a semiconductor memory device will be described. R.A.
The S buffer 3 is supplied with a RAS signal, which is a row address strobe signal and also serves as a memory device selection control signal. Further, the CAS buffer 5 is given a CAS signal as a column address strobe signal. Further, the address buffer 4 receives an address signal A. +AI...Ao
is given. Address buffer 4 takes in a row address and a column address at the falling timing of each of the RAS signal and CAS signal, and this address therefore specifies an address in memory cell array 6 to write or read data. A RAS signal obtained by inverting the RAS signal is output from the RAS buffer 3, and is applied to the substrate bias voltage generation circuit 10.20. Then, the voltage Vaa output from the substrate bias voltage generation port 1O120 is supplied to the semiconductor substrate as a bias voltage.

FIG. 2 is an electrical circuit diagram showing an embodiment of the present invention.

In FIG. 2, the substrate bias voltage generation circuit is composed of a first substrate bias voltage generation circuit 10 and a second substrate bias voltage generation circuit 20, but the second substrate bias voltage generation circuit 20 is It is constructed in the same manner as the second substrate bias voltage generation circuit 2 shown in FIG. The first substrate bias voltage generation circuit 10 is constructed in the same manner as the first substrate bias voltage generation circuit 1 shown in FIG. 4 described above except for the following points. That is, a NOR gate 16 is connected between the ring oscillator 11 and the inverter 12.
and an inverter 17 are connected, one input terminal of the NOR gate 16 is given the output of the ring oscillator 11, and the other input terminal is given the RAS signal. NOR gate 1
The output of 6 is given to the inverter 17 and also to the ring oscillator 11.

FIG. 3 is a waveform diagram for explaining the operation of the substrate bias voltage generation circuit shown in FIG. 2.

Next, the operation shown in FIG. 2 will be explained with reference to FIG. Note that the operation of the second substrate bias voltage generation circuit 20 is the same as that of the second substrate bias voltage generation circuit 2 shown in FIG.
Only the operation will be explained. In Figure 2, RAS
When the signal goes to the "H" level, the output of the NOR gate 16 goes to the "L" level, so the oscillation of the ring oscillator 11 stops. As a result, the ring oscillator 11 oscillates only when in the non-selected state, so power consumption in the selected state is reduced. That is, Fig. 3 (a
), the RAS signal becomes “H” level,
In the non-selected state, the voltage VA of the node NA is as shown in FIG.
As shown in b), the ring oscillator 11 oscillates and the first substrate bias voltage is applied to the semiconductor substrate. R.A.
When the S signal becomes "L" level, as shown in FIG. 3(d), the ring oscillator 21 in the second substrate bias voltage generation circuit 20 performs an oscillation operation until the substrate voltage reaches a predetermined level. Since oscillation is stopped when the non-selected state is reached after reaching a predetermined level, power consumption in the non-selected state can be reduced.

[Effects of the Invention] As described above, according to the present invention, the first bias means operates only in the non-selected state, so power consumption in the selected state can be reduced, and the second bias means operates only in the non-selected state. The bias means operates until the substrate voltage reaches a predetermined level, and after reaching the predetermined level, it stops operating in the non-selected state, reducing power consumption in the non-selected state. Thus, a semiconductor memory device with low power consumption can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a schematic block diagram showing the main parts of a semiconductor memory device to which an embodiment of the present invention is applied. FIG. 2 is an electrical circuit diagram of an embodiment of the present invention. FIG. 3 is a waveform diagram showing changes in the voltage levels of nodes NA and Na of the substrate bias voltage generation circuit in one embodiment of the present invention. FIG. 4 is an electrical circuit diagram showing a conventional substrate bias voltage generation circuit. FIG. 5 is a waveform diagram showing changes in the voltage levels of nodes NA and N in the conventional substrate bias voltage generation circuit shown in FIG. 4. FIG. 6 is an electrical circuit diagram showing a substrate potential detection circuit in the conventional substrate bias voltage generation circuit shown in FIG. 4. In the figure, 10 is a first substrate bias voltage generation circuit;
11.21 is a ring oscillator, 12°17.23.2
4 is the inverter, 13.25 is the capacitor, 14, 15
．． 2'6.27 is an n-channel transistor, 16.22
．． 29 is a NOR gate, 20 is a second substrate bias voltage generation circuit, and 28 is a substrate potential detection circuit.

Claims (1)

[Scope of Claims] A semiconductor substrate comprising a semiconductor substrate, first and second bias means for applying a bias voltage to the semiconductor substrate, and substrate potential detection means for detecting a change in the bias potential of the semiconductor substrate. In the semiconductor memory device, the first bias means is activated in a non-selected state and is configured to have a lower bias ability than the second bias means, and the second bias means: A bias voltage is supplied to the substrate until the substrate potential detecting means detects that the substrate potential has reached a predetermined level, and after reaching the predetermined level, when the selection control signal becomes a non-selected state. What is claimed is: 1. A semiconductor memory device configured to stop supplying a bias voltage at .