JP2544993B2 - Semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a built-in voltage conversion circuit that converts a power supply voltage supplied from the outside into a predetermined voltage and supplies the voltage to an internal circuit. Regarding the device.

[Prior Art] In recent years, a 4 Mbit static random access memory (hereinafter referred to as SR
AM) and 16Mbit dynamic random access memory (hereinafter referred to as DRAM) development examples have been announced. These 4 Mbit SRAMs and 16 Mbit DRAMs have short channel M with a gate length of 0.6 μm or less.
OS transistors are used. On the other hand, conventional 4-bit
For a DRAM or the like, a MOS transistor having a gate length of 1 μm to 0.8 μm and operating at a power supply voltage of 5 V is used.

When the short channel MOS transistor used in the above 4M bit SRAM and 16M bit DRAM is operated with the power supply voltage of 5V, the transistor characteristics will be deteriorated to a non-negligible level, causing a reliability problem. It has been pointed out.

0.5 μm by suppressing such deterioration of transistor characteristics
In order to use a short channel MOS transistor having a level gate length, the power supply voltage is changed from 5V to, for example,
It is possible to change to 3.3V. However, considering the coexistence with the 5V power supply system that has been widely used in the past, there is a problem in changing the power supply voltage.

Therefore, a semiconductor device in which a voltage conversion circuit is integrated is proposed. In this semiconductor device, the power supply voltage applied from the outside is maintained at 5V, and the power supply voltage is stepped down to a constant voltage by the voltage conversion circuit. As a result, the internal circuit is operated at a constant voltage that does not depend on the fluctuation of the power supply voltage.

FIG. 8 is a block diagram showing an example of a conventional semiconductor device incorporating a voltage conversion circuit. In addition, FIG.
It is a figure which shows the concrete circuit structure of the voltage conversion circuit shown by a figure. The voltage conversion circuit shown in FIG.
nal of Solid-State Circuits, Vol.SC-22, No.3, p
Proposed by T. Furuyama et al., p.437-441, June 1987.

The semiconductor device 100 of FIG. 8 includes a voltage conversion circuit 101 and an internal circuit.
Includes 105 and input / output circuit 106. The internal circuit 105 includes a memory such as DRAM.

The voltage conversion circuit 101 includes a reference voltage generation circuit 102 and a differential amplifier.
Includes 103 and switching circuit 104. This semiconductor device
100 is the power supply terminal 10 that receives the power supply voltage Vcc and the ground potential
It has a ground terminal 30 for receiving Vss. The reference voltage generation circuit 102 receives a power supply voltage Vcc given from the outside and generates a reference voltage Vr that hardly depends on the power supply voltage Vcc. The reference voltage Vr is input to the differential amplifier 103, and the differential amplifier 103 and the switching circuit 104 supply the power supply voltage Vc.
Internal voltage Vi that does not depend on changes in c and changes in load current
Is generated and supplied to the internal circuit 105. Power supply voltage Vcc is, for example, 5V, and internal voltage Vi is, for example, 3.5V.

The input / output circuit 106 is often directly driven by a power supply voltage Vcc given from the outside in consideration of connection with a peripheral logic LSI of a 5V power supply system. Therefore, the input / output circuit 106
The device is designed so that the minimum gate length is not used for the transistor. When the internal circuit 105 is a memory such as DRAM, the input / output circuit 106 mainly includes a buffer circuit. The input / output circuit 106 receives an address signal AD from the outside through the address terminal 40 and gives the address signal AD to the internal circuit 105. Further, the input / output circuit 106 outputs the data DQ read from the internal circuit 105 to the outside through the data terminal 50, or gives the DQ externally applied to the data terminal 50 to the internal circuit 105. Further, the input / output circuit 106 provides the internal circuit 105 with a control signal CNT externally provided via the control terminal 60.

In FIG. 9, reference voltage generating circuit 102 includes P-channel MOS transistors 21-25. Transistors 21-23 are connected in series between the power supply terminal 10 and the ground terminal 30. The power supply voltage Vcc is divided by the transistors 21 to 23, and the divided voltage appears at the node N1. Transistor 24 is connected between power supply terminal 10 and node N2, and transistor 25 is connected between node N2 and ground terminal 30.

When the power supply voltage Vcc rises, the voltage of the node N1 also rises and the transistor 24 becomes non-conductive. This allows
The voltage of the node N2 is prevented from rising. Conversely, the power supply voltage Vc
When c decreases, the voltage of the node N1 also decreases and the transistor 24 becomes conductive. This prevents the voltage at node N2 from dropping. In this way, the reference voltage Vr is generated from the node N2 and hardly depends on the fluctuation of the power supply voltage Vcc.

The differential amplifier 103 includes P-channel MOS transistors 31, 32.
And a current mirror circuit including N-channel MOS transistors 33 and 34. The gate of the transistor 31 is connected to the node N2 of the reference voltage generation circuit 102. Between the node N3, which is the connection point of the transistors 31 and 32, and the power supply terminal 10, a large-sized P-channel MOS transistor 3
5 and a small P-channel MOS transistor 36 are connected. These transistors 35 and 36 are added to reduce the power consumption of the current mirror circuit.

While the internal circuit 105 is operating, the clock signal Φ0 supplied to the gate of the transistor 35 becomes low level, and the transistor 35 is turned on. This improves the responsiveness of the current mirror circuit. While the internal circuit 105 is not operating, the clock signal Φ0 goes high and the transistor 35 is turned off. In this case, since only the small-sized transistor 36 through which a minute current flows is turned on, power consumption is suppressed.

The switching circuit 104 is a P-channel MOS transistor
Including 41. The gate of the transistor 32 of the current mirror circuit is connected to the node N4. Transistor 41 is the power supply terminal
Connected between 10 and node N4. The gate of the transistor 41 is connected to a node N5 which is a connection point between the transistor 31 and the transistor 33 of the current mirror circuit.

If the internal voltage Vi output from the node N4 becomes higher than the reference voltage Vr, the value of the current flowing in the transistor 31 becomes larger than the value of the current flowing in the transistor 32. As a result, the potential of the node N5 rises. Therefore, the transistor 41 is in a shallow conductive state or a non-conductive state. As a result, the supply of current from power supply terminal 10 to node N4 is stopped or reduced, and internal voltage Vi drops.

On the contrary, when the internal voltage Vi becomes lower than the reference voltage Vr, the value of the current flowing through the transistor 31 becomes smaller than the value of the current flowing through the transistor 32. As a result, the potential of the node N5 drops. Therefore, the transistor 41 becomes conductive, and a sufficient current is supplied from the power supply terminal 10 to the node N4. As a result, the internal voltage Vi rises.

In this way, a constant internal voltage Vi that does not depend on the fluctuation of the power supply voltage Vcc or the fluctuation of the load can be obtained.

FIG. 10 is a diagram showing the voltage conversion characteristic of the voltage conversion circuit of FIG. In FIG. 10, the circles show the measured values, and the solid line L1 shows the simulated characteristics.

As shown in Fig. 10, externally applied power supply voltage Vc
The internal voltage Vi is the reference voltage Vr in the range where c is about 3.5 V or more.
Is kept constant at about 3.5V set as.

[Problems to be Solved by the Invention] On the other hand, in order to guarantee stable operation of a semiconductor device used in various environments, an operation margin test is performed before shipment to detect an unstable operation element as a defective product. It is being eliminated as. In the operation margin test, a low voltage or a high voltage exceeding the operation guarantee voltage range is supplied to the semiconductor device, and the operation test of the semiconductor device is performed. 5V ± 10%
In case of guaranteeing, for example, the test is conducted in the range of 5V ± 20%.

In addition, in order to screen defective products at the time of shipment and to estimate the service life after long-term use, the power supply voltage Vc
An accelerated life test is performed by applying a high voltage that is not normally used as c to the semiconductor device from the outside. For example, when the normal power supply voltage Vcc is 5V, a high voltage of 7V is applied. Here, the screening of defective products refers to selecting defective products by an accelerated life test in order to guarantee the reliability of semiconductor devices in the market.

When it is attempted to apply such an operation margin test or an accelerated life test to a semiconductor device having a built-in voltage conversion circuit as shown in FIG. 8, as is apparent from FIG. The test cannot be conducted effectively because it does not reach the inside of the chip.

Therefore, FIG. 11 shows a semiconductor integrated circuit device capable of applying a high voltage from the outside during the accelerated life test. The semiconductor integrated circuit device of FIG. 11 is disclosed in JP-A-64-55857.
No.

In FIG. 11, the power supply voltage conversion circuit 111 receives a power supply voltage Vcc from the outside and generates an internal voltage Vi of a level lower than the power supply voltage Vcc. Normally, the power supply voltage conversion circuit 11
The internal voltage Vi generated by 1 is supplied to the integrated circuit block 113 via the internal power supply line 112. In the accelerated life test, the transistor 114 is rendered conductive by the switching signal Φ1, and the high voltage Ve supplied from the outside is supplied to the integrated circuit block 113 via the transistor 114 and the internal power supply line 112.

In the semiconductor integrated circuit device of FIG. 11, various tests can be performed by setting the high voltage Ve externally applied to an arbitrary level.

However, if the switch signal Φ1 is generated for some reason, the semiconductor integrated circuit device may be erroneously set to the operation test mode during normal use. In this case, there is a problem that a high voltage is applied to the integrated circuit block 113 and the integrated circuit block 113 is destroyed.

FIG. 12 shows another example of the conventional power supply voltage conversion circuit. This power supply voltage conversion circuit is disclosed in JP-A-63-181196.

The power supply voltage conversion circuit of FIG. 12 includes a reference voltage signal generator 120 that generates a reference voltage Vr according to the voltage level of a control signal from the control terminal 125, and a power supply voltage Vcc into an internal voltage Vi according to the reference voltage. And a conversion unit 130 for converting.

Control terminal 125 and node N10 in reference voltage signal generator 120
Transistors 121 to 124 are connected between and. If all the threshold voltages of the transistors 121 to 124 are Vt,
When the voltage of the control terminal 125 becomes higher than the voltage of the node N10 by 4 Vt or more, the reference voltage Vr increases and the internal voltage Vi output from the conversion unit 130 also increases. When the voltage of the control terminal 125 is other than that, the reference voltage Vr does not change and the conversion unit
The internal voltage Vi output from the 130 does not change, either.

In the power supply voltage conversion circuit of FIG. 12, by applying a high voltage to the control terminal 125, it is possible to generate an internal voltage Vi of a higher level than in normal use, but an internal voltage of lower level than in normal use is generated. It cannot generate voltage.
Therefore, it is not possible to carry out an operation margin test for applying various internal voltages to the internal circuit.

An object of the present invention is to provide a semiconductor device which can supply power supply voltages of various levels to an internal circuit during an operation test and which is not accidentally set to the operation test mode during normal use. .

[Means for Solving the Problems] A semiconductor device according to the present invention includes first and second power supply terminals, a voltage conversion means, an internal circuit means, a detection means, and a switching means.

The first and second power supply terminals receive the first and second power supply voltages from the outside, respectively. The voltage conversion means is the first
The first power supply voltage is received from the power supply terminal of, and the first power supply voltage is converted into a predetermined voltage. The internal circuit means operates with the predetermined voltage converted by the voltage converting means. The detection means receives the first and second power supply voltages and detects that the voltage difference between the first and second power supply voltages has become a predetermined voltage difference. The switching means supplies one of the first and second power supply voltages to the internal circuit means in place of the predetermined voltage converted by the voltage conversion means when the detection means detects the predetermined voltage difference.

[Operation] During normal use, the first power supply voltage supplied from the outside is converted into a predetermined voltage and supplied to the internal circuit means. When the voltage difference between the first and second power supply voltages applied to the first and second power supply terminals reaches a predetermined voltage difference, the first
The internal circuit means is operated by either one of the second power supply voltage and the second power supply voltage. Therefore, during the operation margin test or the accelerated life test, the internal circuit means is operated at a low voltage or a high voltage which is not normally used by keeping the voltage difference between the first and second power supply voltages at a predetermined voltage difference or more. Can be made.

Embodiments Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing the structure of a semiconductor device according to the first embodiment of the present invention.

The semiconductor device 100 of FIG. 1 has a first power supply terminal 10 that receives a first power supply voltage Vcc1 and a second power supply terminal 10 that receives a second power supply voltage Vcc2.
Power source terminal 20 and ground terminal 30 for receiving ground potential Vss. Further, the semiconductor device 100 has an address terminal 40, a data terminal 50, and a control terminal 60, like the conventional semiconductor device of FIG.

The semiconductor device 100 includes a voltage conversion circuit 101 and internal circuit means 10
5 and input / output circuit 106, and further includes voltage level difference detection circuit 107 and switching circuit 108. Voltage conversion circuit 101,
The internal circuit and input / output circuit 106 are similar to the voltage conversion circuit 101, internal circuit 105, and input / output circuit 106 shown in FIG.

The first power supply voltage Vcc1 from the power supply terminal 10 in FIG. 1 is supplied to the reference voltage generation circuit 102, the differential amplifier 103 and the switching circuit 104 included in the voltage conversion circuit 101, and also to the voltage level difference detection circuit 107. Supplied. Second power terminal 20
The second power supply voltage Vcc2 from is supplied to the input / output circuit 106 and the voltage level difference detection circuit 107.

In normal use, the second power supply voltage Vcc2 is the same voltage as the first power supply voltage Vcc1. In normal use, the first power supply voltage Vcc1 and the second power supply voltage Vcc2 are set to 5V, for example. In this case, switching circuit 108 is set on the side of node N4. Therefore, the internal circuit 105 has an internal voltage Vi (for example, 3.5 V) generated by the voltage conversion circuit 101.
V) is supplied.

The voltage level difference detection circuit 107 switches the switching circuit 108 to the side of the second power supply terminal 20 when the first and second power supply voltages Vcc1 and Vcc2 satisfy the following conditions.

Vcc1> Vcc2 + α (1) Here, α is a constant that can be set arbitrarily, but here is about 1 V, for example.

In the operation margin test, the second power supply voltage Vcc2 is set to a low or high test voltage while satisfying the condition of the expression (1). In addition, during the accelerated life test, the second power supply voltage Vcc2 is set to the accelerated voltage while similarly satisfying the condition of the equation (1). In these cases, the internal circuit 105
The second power supply voltage Vc given through the second power supply terminal 20
c2 is supplied directly.

FIG. 2 is a diagram showing a circuit configuration of a main part of the semiconductor device 100 shown in FIG.

The configurations and operations of reference voltage generating circuit 102, differential amplifier 103 and switching circuit 104 are similar to those of reference voltage generating circuit 102, differential amplifier 103 and switching circuit 104 shown in FIG. However, the transistors 35 and 36 shown in FIG. 9 are not connected between the node N3 of the differential amplifier 103 and the first power supply terminal 10, but the node N3 is directly connected to the power supply terminal 10. The ninth
As in the differential amplifier 103 in the figure, the transistors 35 and 36 may be connected between the node N3 and the first power supply terminal 10.

Voltage level difference detection circuit 107 includes a first inverter formed of P channel MOS transistor 71 and N channel MOS transistor 72, and a second inverter formed of P channel MOS transistor 73 and N channel MOS transistor 74. Transistor 71 is connected between first power supply terminal 10 and node N6, and transistor 72 is connected between node N6 and ground terminal 30. The gates of the transistors 71 and 72 are connected to the second power supply terminal 20. Transistor
73 is connected between the first power supply terminal 10 and the node N7, and the transistor 74 is connected between the node N7 and the ground terminal 30. The gates of the transistors 73 and 74 are connected to the node N6.

Switching circuit 108 includes P-channel MOS transistors 81 and 82. The transistor 81 is a node N4 of the switching circuit 104.
Connected to the internal circuit 105. The transistor 82 is connected between the second power supply terminal 20 and the internal circuit 105.
The gate of the transistor 81 is connected to the node N6 of the voltage level difference detection circuit 107, and the gate of the transistor 82 is connected to the node N7 of the voltage level difference detection circuit 107. Node N6
Is supplied with a control voltage V1 and node N7 is supplied with a control voltage V2.

Next, the operation of the circuit of FIG. 2 will be described with reference to the voltage waveform diagram of FIG.

Here, it is assumed that the first power supply voltage Vcc1 is constant at 5V. When the second power supply voltage Vcc2 is higher than 5V,
The transistor 72 in the voltage level difference detection circuit 107 turns on and the transistor 71 turns off. Therefore, the control voltage V1 of the node N6 becomes "L" level (about 0V). This turns on the transistor 73 and turns off the transistor 74. Therefore, the control voltage V2 of the node N7 becomes "H" level (about 5V). As a result, the transistor 81 of the switching circuit 108 turns on and the transistor 82 turns off. Therefore, the internal voltage Vi is
Supplied to 105.

When the second power supply voltage Vcc2 is 4 V or less, the relation of the expression (1) is satisfied. In this case, the voltage level difference detection circuit 107
Since the transistor 71 therein turns on, the control voltage V1 of the node N6 becomes "H" level (about 5V). This turns on the transistor 74 and turns off the transistor 73. Therefore, the control voltage V2 of the node N7 becomes "L" level (about 0V). As a result, the transistor 81 of the switching circuit 108 turns off and the transistor 82 turns on. Therefore, the second power supply voltage Vcc2 from the second power supply terminal 20 is supplied to the internal circuit 105.

By appropriately selecting the gate lengths and gate widths of the transistors 71 to 74 that form the first and second inverters of the voltage level difference detection circuit 107 and optimizing the threshold value of the inverter characteristics, FIG. The properties shown can be obtained.

When a voltage (eg, 7V) higher than the voltage (5V) during normal use is to be applied to the internal circuit 105, the first power supply voltage Vcc1 is set to a higher voltage (eg, 9V), and the second The power supply voltage Vcc2 of is set to a predetermined voltage (7V). In this case, the condition of Expression (1) is satisfied, so the second power supply voltage Vcc2 is supplied to the internal circuit 105.

Note that the value of α in the equation (1) is the voltage level difference detection circuit 10
It is determined by the size ratio of the N-channel MOS transistor and the P-channel MOS transistor in 7. The larger the size of the N-channel MOS transistor, the larger the value of α.

FIG. 4 is a circuit diagram showing another example of the configuration of the voltage level difference detection circuit 107.

The voltage level difference detection circuit of FIG. 4 includes an N-channel MOS transistor 75, a resistor 76, a differential amplifier 77 and an inverter.
Including 78,79. The transistor 75 is diode-connected between the first power supply terminal 10 and the node N8. The resistor 76 is connected between the node N8 and the ground terminal 30. Differential amplifier 77 includes P-channel MOS transistors 171 and 172 and N-channel MOS transistors 173 and 174. Transistor 171
The connection point between the transistor 172 and the transistor 172 is connected to the first power supply terminal 10. The connection point between the transistor 173 and the transistor 174 is connected to the ground terminal 30. Transistor 17
The gate of 1 is connected to the node N8, and the gate of the transistor 172 is connected to the second power supply terminal 20. A node N9, which is a connection point between the transistors 171 and 173, is connected to the input terminal of the inverter 78. Inverter 78
The output terminal of is connected to the input terminal of the inverter 79. The control voltage V1 is output from the output terminal of the inverter 78, and the control voltage V2 is output from the output terminal of the inverter 79.

The potential of the node N8 becomes the first power supply voltage Vcc1-α.
Here, α becomes 1V when the threshold voltage of the diode-connected N-channel MOS transistor 75 is set to 1V.
If the first and second power supply voltages Vcc1 and Vcc2 satisfy the condition of Expression (1), the value of the current flowing through the transistor 171 becomes smaller than the value of the current flowing through the transistor 172. As a result, the potential of the node N9 drops. Therefore, the control voltage V1 output from the inverter 78 becomes "H" level,
The control voltage V2 output from the inverter 79 becomes "L" level.

If the first and second power supply voltages Vcc1 and Vcc2 do not satisfy the condition of the expression (1), conversely, the control voltage V1 becomes "L".
And the control voltage V2 becomes "H" level.

Thus, the input / output characteristics of the voltage level difference detection circuit of FIG. 4 are similar to the input / output characteristics of FIG.

FIG. 5 is a block diagram showing the structure of a semiconductor device according to the second embodiment of the present invention.

The semiconductor device 100 of FIG. 5 differs from the semiconductor device 100 of FIG. 1 in that the switching circuit 108 is provided between the reference voltage generating circuit 102 and the differential amplifier 103. In the semiconductor device 100 of FIG. 5, the switching circuit 108 is used during normal use.
Are set on the node N2 side of the reference voltage generation circuit 102. When the condition of expression (1) is satisfied, the switching circuit 108 is switched to the second power supply terminal 20 side. In this case, the internal circuit 105 operates with the second power supply voltage Vcc2 externally applied via the differential amplifier 103 and the switching circuit 104.

Therefore, if the second power supply voltage Vcc2 is changed while satisfying the condition of the expression (1), the operation margin test and the accelerated life test can be performed in the same manner as the semiconductor device 100 shown in FIG.

FIG. 6 is a block diagram showing the structure of a semiconductor device according to the embodiment of FIG. 3 of the present invention. Further, FIG. 7 is a diagram showing a circuit configuration of a main part of the semiconductor device 100 of FIG.

The semiconductor device 100 of FIG. 6 differs from the semiconductor device 100 of FIG. 1 in that the switching circuit 108 is connected to the first power supply terminal 10. In the semiconductor device 100 of FIG. 6, the first
When the second power supply voltages Vcc1 and Vcc2 satisfy the condition of Expression (1), the first power supply voltage Vcc1 is supplied to the internal circuit 105.

For example, in order to supply a high voltage of 7V to the internal circuit 105, the first power supply voltage Vcc1 is set to 7V and the second power supply voltage Vcc1 is set to 7V.
Set the power supply voltage Vcc2 of to 5V. When supplying a low voltage of 3.5 V to the internal circuit 105, the first power supply voltage Vc
c1 is set to 3.5V and the second power supply voltage Vcc2 is set to 0V, for example.

As described above, in the semiconductor device 100 of FIG. 6, the internal circuit 105 can be directly operated by the first power supply voltage Vcc1 given from the outside only when the condition of the expression (1) is satisfied.

In FIG. 7, reference voltage generating circuit 102 and differential amplifier 1
03, switching circuit 104 and voltage level difference detection circuit 1
The configuration and operation of 07 are similar to those of the reference voltage generation circuit 102, the differential amplifier 103, the switching circuit 104, and the voltage level difference detection circuit 107 shown in FIG. Switching circuit 108 includes P-channel MOS transistors 83 and 84. The transistor 83 is connected between the node N5 of the differential amplifier 103 and the gate of the transistor 41 of the switching circuit 104. The transistor 84 is the switching circuit 10
It is connected between the gate of the transistor 41 of 4 and the ground terminal 30. The gate of the transistor 83 is connected to the node N7 of the voltage level difference detection circuit 107, and the gate of the transistor 84 is connected to the node N6.

When the first and second power supply voltages Vcc1 and Vcc2 satisfy the condition of the expression (1), the control voltage V1 becomes "L" level and the control voltage V2 becomes "H" level. Thereby, the transistor 84
Turns on and the transistor 83 turns off. As a result, the voltage of the gate of the transistor 41 is set to the ground potential Vss,
The transistor 41 turns on. Therefore, the internal circuit 105
Is supplied with the first power supply voltage Vcc1.

When the first and second power supply voltages Vcc1 and Vcc2 do not satisfy the condition of the expression (1), the control voltage V1 becomes "H" level and the control voltage V2 becomes "L" level. This turns on the transistor 83 and turns off the transistor 84. Therefore, the internal voltage Vi is supplied to the internal circuit 105.

The embodiment shown in FIG. 7 has the advantage that the transistor 41, which is generally large in size, can be shared during normal operation and testing.

In the first, second and third embodiments described above, the formula (1)
An arbitrary voltage can be supplied to the internal circuit 105 by changing the first power supply voltage Vcc1 or the second power supply voltage Vcc2 while satisfying the above condition.

By changing the first power supply voltage Vcc1 or the second power supply voltage Vcc2 while satisfying the condition of Vcc2> Vcc1 + α, the internal circuit 105 is changed to the first power supply voltage Vcc1 or the second power supply voltage Vcc1.
The configuration of operating with the power supply voltage Vcc2 of is also possible.

In the above embodiment, the address signal AD, the data DQ and the control signal CNT are driven by the external power supply voltage, but the address signal AD and the control signal CNT may be driven by the internal voltage Vi.

Furthermore, in the above embodiment, the case where the internal circuit 105 is a memory has been described, but the internal circuit 105 is not limited to a memory and may be another circuit.

[Effects of the Invention] As described above, according to the present invention, when the voltage difference between the first and second power supply voltages applied from the outside becomes a predetermined voltage difference, either of the first and second power supply voltages is obtained. Since one of them is supplied to the internal circuit means, during normal use, the internal circuit means is operated by the predetermined voltage converted by the voltage conversion means, and during operation tests such as an operation margin test and an accelerated life test, an arbitrary voltage is applied. The internal circuit means can be operated.

Further, when the voltage difference between the first and second power supply voltages becomes a predetermined voltage difference, the internal circuit means is operated by the voltage applied from the outside, so that the semiconductor device is erroneously operated in the operation test mode during normal use. Is set, and the internal circuit means is prevented from being destroyed by a high voltage.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing the configuration of a semiconductor device according to a first embodiment of the present invention. FIG. 2 is a diagram showing a circuit configuration of a main part of the semiconductor device of FIG. FIG. 3 is a diagram showing input / output characteristics of the voltage level difference detection circuit shown in FIG. FIG. 4 is a diagram showing another configuration example of the voltage level difference detection circuit. FIG. 5 is a block diagram showing the structure of a semiconductor device according to the second embodiment of the present invention. FIG. 6 is a block diagram showing the structure of a semiconductor device according to the third embodiment of the present invention. FIG. 7 is a diagram showing a circuit configuration of a main part of the semiconductor device of FIG. FIG. 8 is a block diagram showing the configuration of a conventional semiconductor device having a built-in voltage conversion circuit. FIG. 9 is a diagram showing a specific circuit configuration of the voltage conversion circuit included in FIG. FIG. 10 is a diagram showing the output voltage characteristic of the voltage conversion circuit of FIG. FIG. 11 is a block diagram showing an example of a conventional semiconductor integrated circuit device incorporating a power supply voltage conversion circuit. FIG. 12 is a circuit diagram showing another example of the conventional voltage conversion circuit. In the figure, 10 is a first power supply terminal, 20 is a second power supply terminal, 30 is a ground terminal, 100 is a semiconductor device, 101 is a voltage conversion circuit, 102 is a reference voltage generation circuit, 103 is a differential amplifier, and 104 is Switching circuit, 105 is an internal circuit, 106 is an input / output circuit,
107 is a voltage level difference detection circuit, 108 is a switching circuit, Vcc1 is a first power supply voltage, Vcc2 is a second power supply voltage, and Vi is an internal voltage. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (8)

(57) [Claims] 1. A first power supply terminal and a second power supply terminal respectively receiving a first power supply voltage and a second power supply voltage from the outside, respectively. A first power supply voltage is received from the first power supply terminal and the first power supply voltage is predetermined. Voltage converting means for converting into the voltage of the above, internal circuit means operating by the predetermined voltage converted by the voltage converting means, receiving the first and second power supply voltages, and the first and second power supply voltages thereof. Detecting means for detecting that the voltage difference of has become a predetermined voltage difference, and, when the detecting means detects the predetermined voltage difference, instead of the predetermined voltage converted by the voltage converting means, A semiconductor device comprising switching means for supplying one of the first and second power supply voltages to the internal circuit means. 2. The voltage converting means receives a first power supply voltage from the first power supply terminal and generates a reference voltage based on the first power supply voltage, and the internal circuit. Control means for performing voltage control in the form of negative feedback so that the voltage to be supplied to the means is constant, and the switching means is responsive to the output signal of the detection means,
2. The semiconductor device according to claim 1, wherein either one of the output voltage from the control means and the second power supply voltage from the second power supply terminal is selectively supplied to the internal circuit means. 3. The voltage converting means receives a first power supply voltage from the first power supply terminal and generates a reference voltage based on the first power supply voltage, and the internal circuit. Control means for performing voltage control in the form of negative feedback so that the voltage to be supplied to the means is constant, and the switching means is responsive to the output signal of the detection means,
The semiconductor device according to claim 1, wherein either one of the reference voltage from the reference voltage generating means and the second power supply voltage from the second power supply terminal is selectively supplied to the control means. 4. The reference voltage generating means for receiving a first power supply voltage from the first power supply terminal and generating a reference voltage based on the first power supply voltage; and the internal circuit. Control means for performing voltage control in the form of negative feedback so that the voltage to be supplied to the means is constant, and the switching means is responsive to the output signal of the detection means,
The semiconductor device according to claim 1, wherein either one of the output voltage from the control means and the first power supply voltage from the first power supply terminal is selectively supplied to the internal circuit means. 5. The control means is connected between an output node for outputting a signal indicating a detection result, the first power supply terminal and the output node, and is connected to the second power supply terminal. A second conductive channel type electric field having a first conductive channel type field effect transistor means having a terminal and a control terminal connected between the output node and a predetermined potential and connected to the second power supply terminal. 2. A semiconductor device according to claim 1, including effect transistor means. 6. The voltage detecting means includes a voltage shifting means for shifting one of the first and second power supply voltages by the predetermined voltage difference, and a voltage shifted by the voltage shifting means for the first voltage.
The semiconductor device according to claim 1, further comprising: a comparison unit that compares the second power supply voltage with the other. 7. A semiconductor device operating with a plurality of power supply voltages, comprising voltage supply means for supplying a plurality of voltages, first and second terminals respectively receiving a first and a second voltage from the outside, and the voltage. Any one of the plurality of voltages based on the detection result of the detection means for detecting the voltage difference between the first and second voltages, and the internal circuit means operated by the voltage supplied from the supply means. A semiconductor device comprising switch means for providing one to the internal circuit means. 8. A method of operating a semiconductor device including an internal circuit driven by a predetermined voltage, comprising the steps of receiving first and second power supply voltages supplied from the outside, respectively. Converting to a predetermined voltage, supplying the converted predetermined voltage to the internal circuit, detecting that the difference between the first and second voltages has reached a predetermined voltage difference, and When the predetermined voltage difference is detected, in place of the converted predetermined voltage, any one of the first voltage and the second voltage is supplied to the internal circuit means. .