JP2003007835A - Semiconductor device and method of testing semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device, in which an increase of a chip area is restricted, failure of a depression type MOS transistor for output of a step-down circuit is prevented, and is capable of realizing an operation lower limit test of an internal circuit that operates by voltage lower than operating voltage of an external interface circuit, and a method of testing thereof. SOLUTION: The semiconductor device comprises an input/output circuit 1 that operates by power source voltage VCC, an internal circuit 2 that operates by step-down voltage VCL lower than the power source voltage VCC, a step- down circuit 3 that steps down the power source voltage VCC to the step-down voltage VCL, a switching element VCLSW for cutting off the step-down circuit 3 when testing the internal circuit 2, and the like, in which the switching element VCLSW is turned off by setting of a tester to cut off the step-down circuit 3 during the operation lower limit test of the internal circuit 2, test voltage VCLTEST lower than the step-down voltage VCL is applied from outside, and the operation lower limit test of the internal circuit 2 is thus realized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device test technique, and particularly to a semiconductor device suitable for an operation test of an internal circuit operating at a voltage lower than an operation voltage of an external interface circuit, and a test method thereof. Regarding effective technology.

[0002]

2. Description of the Related Art According to a study conducted by the inventor of the present invention, a semiconductor device test technique is disclosed in, for example, Japanese Patent Laid-Open No.
The technique described in Japanese Patent No. 149876 is mentioned. In this publication, a switch circuit that switches the power supply line of the internal circuit between the output of the internal step-down circuit and the external terminal is provided, and during the test, the power supply line of the internal circuit is switched to the external terminal side and the test voltage is applied from the external terminal. There is disclosed a technology of a semiconductor integrated circuit device configured to perform a test.

[0003]

The inventor of the present invention has made clear the following as a result of examining a test technique for a semiconductor device. For example, the technique of the above-mentioned publication relates to an operation test in which a voltage higher than the operation voltage of the internal circuit is applied from an external terminal at the time of test, so-called aging.

As a technique for testing a semiconductor device examined by the present inventor as a premise of the present invention, there is a semiconductor device (LSI) as shown in FIG. 8, for example.
The LSI shown in FIG. 8 includes an input / output circuit 1, an internal circuit 2, a step-down circuit 3 and the like. The input / output circuit 1 is operated at a power supply voltage VCC, and the internal circuit 2 is a step-down circuit 3 as a voltage conversion circuit inside the chip. Step-down voltage V obtained by stepping down the power supply voltage VCC with
It is configured to operate in CL. The following is clear from the configuration of FIG.

(1) In the step-down circuit 3, the depletion type NMOS transistor NDMOS for output of the step-down circuit 3 is sandwiched between the power supply voltage VCC and the step-down voltage VCL, and the gate potential of the depletion type NMOS transistor NDMOS is controlled. Although it is a configuration for obtaining the step-down voltage VCL,
The depletion type NMOS transistor NDMOS needs to have a low resistance value such that the power supply voltage does not drop due to its own resistance value. Therefore, the input / output circuits 1 are dispersedly arranged to form transistors having a substantially large gate width to reduce the resistance value.

(2) L when the step-down voltage VCL drops
To perform an SI operation test, a so-called operation lower limit test, a test voltage VCLTEST lower than the step-down voltage VCL is applied from a power source external to the LSI, but VCL> VCL
In the case of TEST, an overcurrent flows in the depletion type NMOS transistor NDMOS from VCC to VCL, and the depletion type NMOS transistor NDMOS
Will be destroyed. Therefore, lower the power supply voltage VCC,
To cope with this, the power supply voltage VCC is lowered so that VCC = VCLTEST. Therefore, the input / output circuit 1 operating at the power supply voltage VCC operates at an operation voltage outside the specifications lower than the power supply voltage VCC, which causes a transistor to be added for the out-of-specifications operation, which causes a chip area to increase. There is.

Therefore, FIG. 8 examined as a premise of the present invention.
In the LSI configuration shown in,
Power supply voltage VCC so that VCLTEST = VCC
Since the output potential of the power supply applied to the external terminal of is lower than the product specifications, it is necessary to add a transistor to the input / output circuit 1 to operate with a power supply voltage outside the product specifications, which increases the chip area. Further, when VCC> VCLTEST, an overcurrent flows and the depletion type NMOS transistor N
The DMOS may be destroyed.

Therefore, an object of the present invention is to suppress an increase in chip area, prevent destruction of an output depletion type MOS transistor of a step-down circuit as a voltage conversion circuit, and operate at a voltage lower than an operating voltage of an external interface circuit. It is an object of the present invention to provide a semiconductor device capable of realizing an operation test of an internal circuit and a test method thereof.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0010]

Among the inventions disclosed in the present application, a brief description will be given to the outline of typical ones.
It is as follows.

In order to achieve the above object, the present invention provides
A second MOS transistor for electrically separating the first voltage and the second voltage is added between the first voltage and the second voltage in order to cut off the step-down circuit as the voltage conversion circuit at the time of testing the internal circuit. The second MOS transistor is arranged so that its resistance value is sufficiently low so as to suppress the power supply drop. The second MOS transistor is distributed and arranged in the external interface circuit like the first MOS transistor for output of the step-down circuit. In addition, a sufficiently low resistance value is obtained while suppressing an increase in chip area.

That is, the semiconductor device according to the present invention comprises an external interface circuit which operates at a first voltage and an internal circuit which operates at a second voltage lower than the first voltage. It has a first MOS transistor for output of the step-down circuit for stepping down, and a second MOS transistor for shutting off the step-down circuit at the time of testing the internal circuit.
The OS transistors are arranged in a distributed manner corresponding to the distributed arrangement of the first MOS transistors.

In the semiconductor device, the first MO
The S transistor is a depletion type MOS transistor.

In the semiconductor device, the first MO
The S transistor and the second MOS transistor are connected in series between the first voltage and the second voltage. Furthermore, the second MOS transistor is connected to the external terminal side of the first voltage.

Further, the semiconductor device has a mode setting external terminal for setting an operation mode of an internal circuit,
When testing the internal circuit, the test mode is set from a test device connected to the mode setting external terminal. Further, at the time of testing the internal circuit, a third voltage lower than the second voltage is applied to test the lower limit of operation of the internal circuit.

In the semiconductor device, the first MO
The S transistor and the second MOS transistor are distributed and arranged in each cell of the external interface circuit.
Further, the first MOS transistor and the second MOS transistor are arranged on the outer peripheral portion of the semiconductor device.

In the semiconductor device, the internal circuit includes a CPU or a memory circuit.

The semiconductor device testing method according to the present invention comprises an external interface circuit operating at a first voltage,
A method for testing a semiconductor device, comprising: an internal circuit that operates at a second voltage lower than the first voltage; and a MOS transistor for interrupting a step-down circuit that steps down the first voltage to the second voltage. During the circuit test, the step-down circuit is shut off by the MOS transistor, and the third voltage lower than the second voltage is externally applied to test the lower limit of operation of the internal circuit.

Further, in the semiconductor device testing method, when the internal circuit is tested, the test mode is set from a test device connected to a mode setting external terminal for setting the operation mode of the internal circuit.

[0020]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings.

First, an example of a schematic configuration of a semiconductor device according to an embodiment of the present invention will be described with reference to FIG. FIG. 1 is a schematic configuration diagram showing the semiconductor device of the present embodiment.

The semiconductor device (LSI) of this embodiment is
For example, the input / output circuit 1 that is an external interface circuit that operates at the power supply voltage VCC that is the first voltage, and the power supply voltage V
The internal circuit 2 that operates at the step-down voltage VCL that is the second voltage lower than CC, and the power supply voltage VCC that is the step-down voltage VCL
And a switching element VCL for shutting down the step-down circuit 3 when the internal circuit 2 is tested.
It is composed of SW and the like. The step-down circuit 3 can also be regarded as a voltage conversion circuit that converts the power supply voltage VCC into the step-down voltage VCL.

The input / output circuit 1 is a circuit for interfacing with the outside, and is composed of a mode switching circuit 4 for switching the operation mode, an input / output buffer and the like. The mode switching circuit 4 is provided with a switching control circuit 5 for controlling the switching element VCLSW.

Signals are input to and output from the input / output circuit 1 through external input / output signal terminals I / O1 to I / On. External input / output signal external terminals I / O1 to I /
The signal input through On is supplied to the internal circuit 2 through the input / output circuit 1. Further, the signal from the internal circuit 2 passes through the input / output circuit 1 and the input / output signal external terminal I / O.
1 to I / On are output to the outside.

A mode setting signal is externally input to the input / output circuit 1 through the mode setting external terminals MD0 to MD2. External mode setting external terminals MD0
The mode setting signal input through the MD 2 is input to the mode switching circuit 4, and the mode switching circuit 4 generates a setting signal for each operation mode such as a test mode and a user mode. The setting signal for each operation mode is supplied to the internal circuit 2, and the internal circuit 2 can operate in a predetermined operation mode. In addition, according to each operation mode, the switching control signal V in the switching control circuit 5
CLSE is generated, and this switching control signal VCL
Switching element VCLSW ON / OFF by SE
Is controlled.

A power supply voltage VCC is applied to the input / output circuit 1 from the outside through an external terminal for power supply voltage. Further, the input / output circuit 1 has a step-down voltage VCL obtained by stepping down the power supply voltage VCC through the step-down circuit 3 or a test voltage VC externally supplied through an external terminal for test voltage.
LTEST is applied. Test voltage VCLTEST
Is a voltage applied from the outside in a test mode such as an operation lower limit test of the internal circuit 2.

The internal circuit 2 has a circuit configuration including, for example, a central processing unit (CPU) or a memory circuit. The internal circuit 2 operates by receiving the input signal supplied from the input / output circuit 1, and outputs the result of the operation as an output signal to the input / output circuit 1. Further, the internal circuit 2 receives a setting signal of each operation mode supplied from the mode switching circuit 4 of the input / output circuit 1, and operates in a predetermined operation mode such as a test mode or a user mode. Further, the step-down voltage VCL obtained by stepping down the power supply voltage VCC through the step-down circuit 3 or the test voltage VCLTEST supplied from the outside through the test voltage external terminal is applied to the internal circuit 2.

The step-down circuit 3 is a circuit for generating a step-down voltage VCL which is step-down with respect to the power supply voltage VCC, and is a depletion type NMOS transistor NDMOS which is a MOS transistor for outputting the step-down voltage VCL and this depletion type NMOS. It is composed of a step-down control circuit 6 and the like for controlling the gate potential of the transistor NDMOS. ON / OFF of the depletion type NMOS transistor NDMOS is controlled by the step-down control circuit 6, and the step-down voltage VCL obtained by stepping down the power supply voltage VCC is applied to the internal circuit 2. In the present specification, the MOS transistor can be understood as including an insulated gate field effect transistor.

The switching element VCLSW is a switch for shutting off the step-down circuit 3 during the operation lower limit test of the internal circuit 2, and is composed of, for example, a PMOS transistor. The switching element VCLSW composed of the PMOS transistor has its gate potential controlled by the control signal VCLSE of the switching control circuit 5 of the input / output circuit 1 and is turned OFF during the operation lower limit test, and the test voltage VCLTEST is applied to the internal circuit 2 from the outside. It becomes possible to do.

In the semiconductor device configured as described above, during normal operation, the power supply voltage V
CC (including ground voltage GND) is applied, the input / output circuit 1 is operated by this power supply voltage VCC, and the power supply voltage V
The internal circuit 2 is operated by the step-down voltage VCL obtained by stepping down CC through the step-down circuit 3. At this time, the switching element VCLSW including the PMOS transistor is in the ON state.

During the test, a tester, which is a test device, is connected to the external terminal, the power supply voltage VCC (including the ground voltage GND) is applied from the power supply voltage external terminal, and the test voltage VCLTEST is applied from the test voltage external terminal. Is applied. In this test, P
Switching element VCLS consisting of MOS transistors
W is controlled to the OFF state, the step-down circuit 3 is cut off, and the step-down voltage VCL is not applied. Details will be described later.

Next, an example of the configuration of the input / output circuit in the semiconductor device of this embodiment will be described with reference to FIGS. 2 and 3. FIG. 2 is a circuit diagram showing an input / output circuit, FIG.
(B) is a circuit diagram showing the level shifters of the input buffer and the output buffer, respectively.

The input / output circuit 1 is, for example, as shown in FIG. 2, an input / output signal external terminal I / O1 (to I / O).
n), which is composed of an input buffer 7 for shaping the waveform of an input signal from the outside and transmitting it to the internal circuit 2, and a transistor having a small internal operating resistance for transmitting the output signal to the outside to an external terminal having a large load. The output buffer 8 and the like are provided.

The input buffer 7 is connected in series between the external terminal for input / output signals I / O1 (to I / On) and the internal circuit 2 and has a resistance R1 for external environment measures and a CMOS buffer structure. PMOS transistor PM1 and NMOS
It is composed of a transistor NM1 and a level shifter L / S1 for adjusting a voltage level. The PMOS transistor PM1 and the NMOS transistor NM1 of the CMOS buffer structure are connected to the power supply voltage VCC and the ground voltage GND.
Connected between. Further, the power supply voltage VCC and the step-down voltage VCL are applied to the level shifter L / S1. A PMOS transistor of the switching element VCLSW and a depletion type NMOS transistor NDMOS for output of the step-down circuit 3 are connected in series between the power supply voltage VCC and the step-down voltage VCCL, and the PMOS transistor of the switching element VCLSW is on the power supply voltage VCC side. Are connected so that

The output buffer 8 is connected in series between the internal circuit 2 and the input / output signal external terminal I / O1 (to I / On), and is a level shifter L / S2 for adjusting the voltage level.
And a PMOS transistor PM having a CMOS buffer structure
2 and an NMOS transistor NM2, a PMOS transistor PM3 and an NMOS transistor NM3 for external environment countermeasures, and the like. The PMOS transistor PM2 and the NMOS transistor NM2 having the CMOS buffer structure are connected to the power supply voltage VCC and the ground voltage GND.
Connected between. The PMOS transistor PM3 for external environment measures N between the power supply voltage VCC and the signal line.
The gate of the MOS transistor NM3 is commonly connected to the voltage side between the ground voltage GND and the signal line. Further, the level shifter L / S2 has a power supply voltage V
CC and the step-down voltage VCL are applied.

Level shifter L / S1 of input buffer 7
Is, for example, as shown in FIG.
PMOS transistor PM11 and NMOS transistor NM11, and PMOS transistor PM12
And an NMOS transistor NM12 are connected in series. The PMOS transistor PM11 and the NMOS transistor NM1 of the CMOS structure in the previous stage
1 is connected between the power supply voltage VCC and the ground voltage GND. The CMOS transistor PMOS transistor P in the latter stage
The M12 and the NMOS transistor NM12 are connected between the step-down voltage VCL and the ground voltage GND.

Level shifter L / S2 of output buffer 8
Is, for example, as shown in FIG.
PMOS transistor PM21 and NMOS transistor NM21, and PMOS transistor PM22
And the NMOS transistor NM22 and these CMs
A PMOS connected between the OS structure by a combination of a CMOS structure and a gate of this output.
The transistors PM23 to PM26 and the NMOS transistors NM23 and NM24 are connected in series. The PMOS transistor PM21 and the NMOS transistor NM21 of the CMOS structure in the previous stage are connected between the step-down voltage VCL and the ground voltage GND. The PMOS transistor PM22 and the NMOS transistor NM22 having the CMOS structure in the subsequent stage are connected between the power supply voltage VCC and the ground voltage GND. Further, the PMOS transistors PM23 to PM26 and the NMOS transistors NM23 and NM24 having the combined configuration are connected between the power supply voltage VCC and the ground voltage GND.

Next, referring to FIG. 4, an example of the configuration of the mode switching circuit including the switching control circuit in the semiconductor device of the present embodiment will be described. FIG. 4 is a circuit diagram showing a mode switching circuit including a switching control circuit.

The mode switching circuit 4 is, for example, as shown in FIG. 4, an external terminal for mode setting MD0 to MD0.
One input is connected to each of 2 and the standby signal STBY-H (5V signal) is input to the other input NO
R gates NOR31 to NOR33, inverters IV31 to IV33 connected to the NOR gates NOR31 to NOR33, and inverters IV31 to I, respectively.
Level shifters L / S31 to respectively connected to V33
L / S33, NA connected between the inverters IV31, IV33 and the level shifters L / S31, L / S33
ND gate NAND31, NAND32, inverter I
It is composed of V34, IV35, noise canceller NC31 and the like. Two-stage inverters IV36 and IV37 are connected to the output signal line of the noise canceller NC31. Of these, NAND gate NAND3
1, the NAND 32, the inverters IV34 and IV35, the noise canceller NC31 and the like constitute the switching control circuit 5.

The mode switching circuit 4 includes NOR gates NOR31 to NOR33 and inverters IV31 to IV.
33, NAND gates NAND31 and NAND32 that form the switching control circuit 5, and an inverter IV3
4, IV35, noise canceller NC31, etc. are configured in the voltage system circuit of the power supply voltage VCC, and the level shifter L /
S31 to L / S33 and the like are configured in the voltage system circuit of the step-down voltage VCL. Regarding the standby signal, when the test voltage VCLTEST is externally applied, the step-down voltage VCL
When the circuit operation of the system becomes unstable and enters the standby state, the switching element VCLSW may be turned on and the semiconductor device may be destroyed.
System standby signal STBY-H to NOR gate NOR
31 to NOR33 to control the standby state.

Further, in the mode switching circuit 4, the mode setting signals MDA0 to MDA2 and the switching control signal V
CLSE is generated and the switching control signal VCLSE is generated.
Is the power supply voltage VCC that is not affected by the step-down voltage VCL
It is made in the voltage system circuit. Mode setting signals MDA0
MDA2 is NOR gates NOR31 to NOR, respectively.
The signal is output from the level shifters L / S31 to L / S33 through the inverter 33, the inverters IV31 to IV33, the NAND gate NAND31, and the inverter IV34, and is supplied to the internal circuit 2. In addition, the switching control signal VCLSE
Is an inverter IV35 and a NAND gate NAND3
2. Inverter IV via noise canceller NC31
36, output from IV37, switching element VCL
Controls ON / OFF of SW. When the switching control signal VCLSE is "0", the switching element VC
LSW is turned on, and when it is "1", it is turned off. The operation mode based on the combination of the mode setting signals MDA0 to MDA2 and the switching control signal VCLSE will be described later.

Next, an example of the configuration of the step-down circuit including the step-down control circuit in the semiconductor device of the present embodiment will be described with reference to FIG. FIG. 5 is a circuit diagram showing a step-down circuit including a step-down control circuit.

For example, as shown in FIG. 5, the step-down control circuit 6 includes an inverter IV41 to which a standby signal STBY is input, and a PMOS transistor PM4 whose gate potential is controlled by the output of the inverter IV41.
1 and PMOS transistors PM42, PM whose gate potential is controlled by the PMOS transistor PM41
43, the depletion type NM connected between the PMOS transistors PM42 and PM43 and the power supply voltage VCC.
OS transistors NDM41 and NDM42, and a PMOS whose gate potential is controlled by a standby signal STBY
Transistor PM44 and NMOS transistor NM
41, NM42 and this PMOS transistor PM44
And an NMOS transistor NM43 whose gate potential is controlled by the NMOS transistor NM41,
A PMOS transistor PM45 whose gate potential is controlled by the MOS transistor NM43, an NMOS transistor NM44 connected between the PMOS transistor PM45 and the test voltage VCLTEST, and a PMO.
The NMOS transistors NM45 and NM46 whose gate potential is controlled by the S transistor PM45, and the gate potential which is controlled by the standby signal STBY are
NMO connected to signal line from transistor PM43
It is composed of an S transistor NM47 and the like.

Outside the step-down control circuit 6, the PMO of the switching control element VCLSW is provided between the power supply line of the power supply voltage VCC and the power supply line of the test voltage VCLTEST.
An S transistor and a depletion type NMOS transistor NDMOS for output of the step-down circuit 3 are connected in series, and the depletion type NMOS transistor NDMOS has its gate potential controlled by the node voltage VG of the signal line from the PMOS transistor PM43. . Further, the step-down control circuit 6 is controlled by the standby signal STBY supplied from the internal circuit 2. The standby signal STBY is a signal for stopping the operation of the step-down circuit 3 when the chip enters the low power consumption mode.

Next, referring to FIG. 6, an example of each operation mode by the mode switching circuit in the semiconductor device of the present embodiment will be described. FIG. 6 is an explanatory diagram for explaining each operation mode by the mode switching circuit.

As the operation modes, as shown in an example in FIG. 6, a test mode (mode 0) for performing a normal test including aging and a test mode (mode 1) for performing an operation lower limit test. , A single-chip mode user mode (mode 4) corresponding to the specifications of each user, and an external memory expansion mode user mode (mode 5).

In the test mode, the mode setting external terminal MD2 is set to "0" by the setting of the external tester, and the switching control signal VCLSE is determined by the state of the mode setting external terminal MD0. For example, when the mode setting external terminal MD0 is set to "0", the switching control signal VCLSE becomes "0", and the switching element VC
LSW is turned on. As a result, the internal circuit 2 and the step-down circuit 3 are connected, and the internal step-down effective state, that is, the test voltage VCLTEST cannot be forcibly applied (mode 0). This mode 0 is a normal test mode including aging, and at this time, the mode setting signals MDA0 to MDA
DA2 = “0”.

For example, the operation during aging in this mode 0 is as follows. Regarding the voltage setting during this aging, the input / output circuit 1 to which the power supply voltage VCC is directly applied is approximately 7 V, and the internal circuit 2 to which the step-down voltage VCL is applied.
It is necessary to apply a voltage of about 4.6 V to the device and perform an acceleration test. The internal circuit 2 uses the step-down voltage VCL that is clamped at about 3.2 V even when the power supply voltage VCC becomes high, so that even if the power supply voltage VCC is increased, about 4.
6V cannot be applied. Therefore, in the configuration shown in FIGS. 1 and 5, about 4.6 V is directly applied from the external terminal of the test voltage VCLTEST to perform the acceleration test.

At this time, the power supply voltage VCC and the step-down voltage VC
Although a potential difference occurs between L and (V−VCL) with respect to the step-down voltage VCL and the node voltage VG, the threshold voltage Vth of the depletion type NMOS transistor NDMOS is
Since it is larger than the absolute value of, the gate-source potential relationship does not satisfy the ON condition of the MOS transistor. Therefore, the depletion type NMOS transistor NDMOS is automatically turned off, an overcurrent does not flow between VCC and VCL, and the depletion type NMOS transistor NDMOS is
Will not destroy.

The reason why the depletion type NMOS transistor NDMOS is not turned on will be described below. MOS
The ON condition of the transistor is gate potential−source potential ≧ Vth. If this relationship is applied to the depletion type NMOS transistor NDMOS, then VG−VCL ≧ VthND. VthND is the threshold voltage Vth of the depletion type NMOS transistor NDMOS, and this VthND is about -3.0 V under standard conditions.

The step-down voltage VCL is VCL during aging.
= 4.6V, the voltage is higher than the normal clamp potential, and therefore the step-down circuit 3 lowers the node voltage VG so that the resistance of the depletion type NMOS transistor NDMOS becomes the highest in order to reduce the step-down voltage VCL. The minimum value of this node voltage VG is about 0V. Therefore, the step-down voltage V
Considering that the node voltage VG = 0V when CL = 4.6V, it becomes VG-VCL = 0-4.6 = -4.6V, which is a depletion type NMOS transistor NDM.
It is smaller than the threshold voltage VthND of the OS = −3.0V. Therefore, the depletion type NMOS transistor N
DMOS does not turn on.

Further, in the test mode, when the mode setting external terminal MD0 is set to "1" by the setting of the tester, the switching control signal VCLSE becomes "1" and the switching element VCLSW becomes OFF. As a result, the step-down circuit 3 is cut off from the internal circuit 2, and the internal step-down invalid state is set, that is, the test voltage VCLTEST can be forcibly applied (mode 1). This mode 1 is test voltage V
This is a mode of the operation lower limit test that permits the external application test of CLTEST, and at this time, the mode setting signals MDA0 to
MDA2 = “0”. This mode setting signal MDA0
~ MDA2 is designed so that the value does not change in both mode 0 and mode 1, so that switching element VCLSW
The internal circuit 2 can transit to the conventional test mode without changing the design.

The operation in the operation lower limit test in mode 1 is as follows. At the time of this operation lower limit test, the voltage of the operation lower limit of the internal circuit 2 is applied. In normal operation, a voltage of about 5 V is applied to the input / output circuit 1 to which the power supply voltage VCC is directly applied, and a voltage of about 3.2 V is applied to the internal circuit 2 to which the step-down voltage VCL is applied.
The guaranteed range of CC is about 4.5 to 5.5 V, and the swing range of the step-down voltage VCL is about 3 to 5 including process variations.
It is 3.5V. Therefore, in the configuration shown in FIG. 1 and FIG. 5, an operation lower limit test is performed by directly applying an electric potential of about 2.9 V lower than about 3 V from the external terminal of the test voltage VCLTEST.

In the user mode, the mode setting external terminal MD2 is set to "1". At this time, the switching control signal VCLSE is set to "0" and the switching element VCLSW is turned on. In this state, the internal circuit 2 and the step-down circuit 3 are connected and the internal step-down effective state, that is, the test voltage VCLTEST cannot be forcibly applied.
For example, when the mode setting external terminal MD0 is set to "0", the mode setting signal MDA0 = "0", the single chip mode is set (mode 4), and when the mode setting external terminal MD0 is set to "1", the mode setting is set. Signal MDA
0 = “1”, and the external memory expansion mode is set (mode 5).

Next, an example of the layout of the semiconductor device of this embodiment will be described with reference to FIG. 7 (a),
(B) is a schematic diagram showing a layout of a semiconductor device and a schematic circuit diagram of an input / output cell.

The layout of the semiconductor device is shown in FIG.
As shown in (a), the input / output circuit 1 is arranged on the outer peripheral portion of the chip, and the internal circuit 2 is arranged on the central portion. The input / output circuit 1 is composed of a plurality of input / output cells 9 and is arranged around the internal circuit 2 in a frame shape. Each of the input / output cells 9 has a circuit configuration as shown in FIG.

Particularly, in each of the input / output cells 9, for example, as schematically shown in FIG. 7B, the power supply voltage VCC and the step-down voltage V that are arranged in the input / output cells 9 by the peripheral wiring of the chip.
Switching element VC connected in series with CL
An LSW PMOS transistor and a depletion type NMOS transistor NDMOS for output of the step-down circuit 3 are arranged. Further, the PMOS transistor of the switching element VCLSW is on the power supply voltage VCC side, and the depletion type NMOS transistor NDMOS is the step-down voltage VC.
They are arranged so as to be on the L side, and these are dispersed and arranged in the input / output cells 9.

For example, as an example, the switching element V
CLSW PMOS transistor and depletion type N
The gate length of the MOS transistor NDMOS is about 100.
However, by arranging them in the frame-shaped input / output cells 9, the total chip size is about 10,000 μm for 120-pin products without affecting the layout area of the internal circuit 2.
The above can be arranged. Further, since the number of input / output cells 9 in which the PMOS transistors of the switching elements VCLSW are arranged is large and the load is large, for example, buffers are arranged on four sides and buffering is performed to control the switching elements VCLSW. Is also possible.

Therefore, according to the semiconductor device of the present embodiment, the switching element VCLSW for electrically separating the power supply voltage VCC and the step-down voltage VCL is connected to the power supply voltage VC.
It is connected between C and the step-down voltage VCL, and the switching element V
CLSW is a depletion type NM for the output of the step-down circuit 3.
By disposing the OS transistors NDMOS in the input / output circuit 1 in a distributed manner, it is possible to obtain a sufficiently low resistance value while suppressing an increase in the chip area.
It is possible to prevent destruction of the MOS transistor NDMOS.

Thus, the switching element VCLSW
Since the operation lower limit test of the internal circuit 2 can be performed with the step-down voltage VCL> the test voltage VCLTEST by arranging, the chip size can be reduced because it is not necessary to add a circuit outside the product specifications to the input / output circuit 1. Is possible. Further, by disposing the switching elements VCLSW in the input / output circuit 1 in a distributed manner, it becomes possible to arrange the low resistance switching elements VCLSW while suppressing an increase in the number of chip circuits. As a result, since the switching element VCLSW can be arranged without deleting a circuit that operates outside the product specifications and increasing the area, it is possible to design a semiconductor device that has the same area and is easy to test.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. It goes without saying that it is possible.

For example, in the above embodiment, C
Although the semiconductor device having an internal circuit including a PU or a memory circuit has been described as an example, the present invention relates to a semiconductor device in which it is necessary to apply different potentials to the power source of the internal circuit and the power source of the input / output circuit at the time of testing. It can be favorably applied to a semiconductor device in which a low resistance power supply control MOS transistor needs to be arranged on a chip.

[0063]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.
It is as follows.

(1) By placing a MOS transistor for shutting down the step-down circuit for stepping down the power supply voltage to the step-down voltage at the time of testing the internal circuit, an operation lower limit test is applied from the outside, and a potential lower than the step-down voltage is applied. Since the test can be performed with the test voltage, it is not necessary to add a circuit outside the product specifications to the external interface circuit. As a result, the chip size can be reduced.

(2) By disposing MOS transistors for shutting down the step-down circuit in the external interface circuit,
It is possible to dispose a low-resistance MOS transistor for shutting down the step-down circuit while suppressing an increase in the number of chip circuits.

(3) According to the above (1) and (2), it is possible to arrange the MOS transistor for shutting down the step-down circuit while suppressing the addition of the circuit which operates outside the product specifications and suppressing the increase of the area. It is possible to design a semiconductor device that is easy to test in the same area.

[Brief description of drawings]

FIG. 1 is a schematic configuration diagram showing a semiconductor device according to an embodiment of the present invention.

FIG. 2 shows a semiconductor device according to an embodiment of the present invention,
It is a circuit diagram which shows an input / output circuit.

3A and 3B are circuit diagrams showing level shifters of an input buffer and an output buffer of an input / output circuit in a semiconductor device according to an embodiment of the present invention.

FIG. 4 shows a semiconductor device according to an embodiment of the present invention,
It is a circuit diagram which shows the mode switching circuit containing a switching control circuit.

FIG. 5 shows a semiconductor device according to an embodiment of the present invention,
It is a circuit diagram showing a step-down circuit including a step-down control circuit.

FIG. 6 shows a semiconductor device according to an embodiment of the present invention,
It is an explanatory view for explaining each operation mode by a mode switching circuit.

7A and 7B are a schematic diagram showing a layout of a semiconductor device according to one embodiment of the present invention and a schematic circuit diagram of an input / output cell.

FIG. 8 is a schematic configuration diagram showing a semiconductor device examined as a premise of the present invention.

[Explanation of symbols]

1 Input / output circuit 2 Internal circuit 3 Step-down circuit 4 Mode switching circuit 5 Switching control circuit 6 Step-down control circuit 7 Input buffer 8 Output buffer 9 Input / output cell VCC Power supply voltage VCL Step-down voltage VCLSW Switching elements I / O1 to I / On Input / output Signal external terminal MD0 to MD2 Mode setting external terminal VCLSE Switching control signal VCLTEST Test voltage NDMOS Depletion type NMOS transistor R1 Resistance PM1 to PM3 PMOS transistors NM1 to NM3 NMOS transistors L / S1, L / S2 Level shifters PM11, PM12 PMOS transistor NM11 , NM12 NMOS transistors PM21 to PM26 PMOS transistors NM21 to NM24 NMOS transistors NOR31 to NOR33 NOR gate I 31~IV37 Inverter L / S31~L / S33 shifter NAND31, NAND32 NAND gate NC31 noise canceller IV41 inverter PM41～PM45 PMOS transistor NDM41, NDM42 depletion type NMOS transistor NM41～NM47 NMOS transistor

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G11C 29/00 651 G01R 31/28 B H01L 27/04 H01L 27/04 B G11C 11/34 341D (72) Inventor Yoshimi Nakane, 145 Nakajima, Nanae-cho, Kameda-gun, Hokkaido F-term inside Hitachi North Sea Semiconductor Co., Ltd. (reference) 2G132 AA08 AB01 AG09 AK07 AK15 5B015 HH00 JJ31 JJ44 KB74 PP02 RR02 RR07 5F038 BB04 CA07 DF01 DF04 DF05 510602 DD02 EZ20 DD21 DD36 GG05

Claims (14)

[Claims] 1. An external interface circuit that operates at a first voltage, an internal circuit that operates at a second voltage that is lower than the first voltage, and a voltage converter for converting the first voltage into the second voltage. A first MOS transistor for outputting a circuit, and a second MOS transistor for shutting off the voltage conversion circuit at the time of testing the internal circuit, wherein the first MOS transistor is distributed and arranged.
A semiconductor device, wherein the MOS transistors are arranged in a distributed manner corresponding to the distributed arrangement of the first MOS transistors. 2. The semiconductor device according to claim 1, wherein the first MOS transistor is a depletion type MO transistor.
A semiconductor device comprising an S transistor. 3. The semiconductor device according to claim 1, wherein the first MOS transistor and the second MOS transistor are connected in series between the first voltage and the second voltage. apparatus. 4. The semiconductor device according to claim 3, wherein the second MOS transistor is connected to the external terminal side of the first voltage. 5. The semiconductor device according to claim 1, further comprising a mode setting external terminal supplied with a mode signal for setting an operation mode of the internal circuit, wherein the mode setting external terminal is used during a test of the internal circuit. A semiconductor device, wherein a test mode of the internal circuit is set by a mode signal output from a test device connected to an external terminal. 6. The semiconductor device according to claim 5, wherein at the time of testing the internal circuit, an operation of the internal circuit is tested by applying a third voltage lower than the second voltage. Semiconductor device. 7. The semiconductor device according to claim 1, wherein the first MOS transistor and the second MOS transistor are dispersedly arranged in each cell of the external interface circuit. 8. The semiconductor device according to claim 7, wherein the first MOS transistor and the second MOS transistor are arranged on an outer peripheral portion of the semiconductor device. 9. The semiconductor device according to claim 1, wherein the internal circuit includes a CPU or a memory circuit. 10. A step-down circuit configured by an external interface circuit operating at a first voltage and an internal circuit operating at a second voltage lower than the first voltage, the step-down circuit for stepping down the first voltage to the second voltage. A method for testing a semiconductor device having a MOS transistor for shutting off a voltage, wherein the step-down circuit is shut off by the MOS transistor during a test of the internal circuit, and a third voltage lower than the second voltage is externally applied. A method for testing a semiconductor device, which comprises applying the voltage to test the operation of the internal circuit. 11. The method for testing a semiconductor device according to claim 10, wherein during the test of the internal circuit, a test mode is set from a test device connected to a mode setting external terminal for setting an operation mode of the internal circuit. A method for testing a semiconductor device, comprising: 12. The semiconductor device according to claim 5, wherein at the time of testing the internal circuit, a fourth voltage higher than the second voltage is applied to test the operation of the internal circuit. Semiconductor device. 13. A step-down circuit configured by an external interface circuit operating at a first voltage and an internal circuit operating at a second voltage lower than the first voltage, the step-down circuit for stepping down the first voltage to the second voltage. A method for testing a semiconductor device having a MOS transistor for shutting off a voltage, wherein the step-down circuit is shut off by the MOS transistor during a test of the internal circuit, and a fourth voltage higher than the second voltage is externally applied. A method for testing a semiconductor device, which comprises applying the voltage to test the operation of the internal circuit. 14. The test method for a semiconductor device according to claim 13, wherein during the test of the internal circuit, a test mode is set from a test device connected to a mode setting external terminal for setting an operation mode of the internal circuit. A method for testing a semiconductor device, comprising: