JPH06334010A - Logical circuit - Google Patents
Logical circuitInfo
- Publication number
- JPH06334010A JPH06334010A JP5122407A JP12240793A JPH06334010A JP H06334010 A JPH06334010 A JP H06334010A JP 5122407 A JP5122407 A JP 5122407A JP 12240793 A JP12240793 A JP 12240793A JP H06334010 A JPH06334010 A JP H06334010A
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- supply line
- field effect
- threshold voltage
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Tests Of Electronic Circuits (AREA)
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Semiconductor Integrated Circuits (AREA)
- Dram (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は低しきい値と高しきい値
の２レベルのしきい値を有するＭＯＳ型電界効果トラン
ジスタで構成した論理回路に係り、特に欠陥素子の有無
の判別が容易にできる論理回路に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic circuit composed of a MOS field effect transistor having a low threshold value and a high threshold value, and particularly, it is easy to determine the presence or absence of a defective element. Related to a logic circuit that can be.
【０００２】[0002]
【従来の技術】ＣＭＯＳ ＬＳＩの製造工程において、
ゲートリーク等の欠陥がＬＳＩを構成する素子（トラン
ジスタ等）に生じた場合には、その欠陥素子を含んだＬ
ＳＩチップを何らかの試験により選別し、不良品と判別
しなければならない。何故なら、そのような不良チップ
は、たとえ一次的に所望の入出力特性を実現できたとし
ても、寿命が著しく短い可能性が高いためである。はじ
めに欠陥素子の有無を判別し、ＬＳＩチップの良品／不
良品を見分けるための一般的な判別試験法について説明
する。ＭＯＳ型電界効果トランジスタのゲートに欠陥が
生じ、微小な電流が流れる（ゲートリーク）場合を図５
に示す。ＭＨ１、ＭＨ３はｐチャネルの電界効果トラン
ジスタ、ＭＨ２、ＭＨ４はｎチャネルの電界効果トラン
ジスタ、ＰＬ１は高電位の電源線、ＰＬ２は低電位の電
源線である。ＥＸ１はＰＬ１に設けられたパッドで、高
電位（ＶＤＤ）電源が接続される。ＥＸ２はＰＬ２に設
けられたパッドで、接地される（ＧＮＤ）。また、論理
回路の例としてＩＮＶ１、ＩＮＶ２はそれぞれインバー
タ回路を示す。Ｎ１、Ｎ２はＩＮＶ１、ＩＮＶ２の入力
端子である。ここで、ＩＮＶ２を構成するＭＨ４に欠陥
が存在し、ゲート電極（Ｎ２と同電位）とソース間（Ｇ
ＮＤに接続）に電流が流れ、また、Ｎ１が低電位（ＧＮ
Ｄレベル）、Ｎ２が高電位（ＶＤＤレベル）の場合を例
として、一般的な判別試験法の説明を行う。上記のごと
き欠陥が存在すると、各ノードの入力端子の電位が変わ
らない時、即ち回路が動作していない時にも、Ｉｇで示
すようにＰＬ１とＰＬ２との間に大きなリーク電流１ｇ
（例えば、１マイクロアンペア以上）が流れる。したが
って、ＥＸ１に接続されたＶＤＤ電源から流れる電流を
測定することにより、欠陥の有無を知り、不良チップを
判別することができる。なお、スタンバイ時には、欠陥
によるリーク電流の他にも、サブスレッショルドリーク
電流（Ｉｓ）が流れる。この電流の大きさはトランジス
タのしきい値電圧に依存する。しきい値電圧の絶対値が
極端に小さくなければ、サブスレッショルドリーク電流
は欠陥による電流に比べて十分に小さく（例えば１０ナ
ノアンペア）、チップの不良品選別には影響しない。2. Description of the Related Art In the process of manufacturing a CMOS LSI,
When a defect such as a gate leak occurs in an element (transistor or the like) that constitutes an LSI, L including the defective element is included.
It is necessary to sort the SI chips by some kind of test to discriminate them as defective products. This is because such a defective chip is likely to have a remarkably short life even if the desired input / output characteristics can be realized temporarily. First, a general discrimination test method for discriminating the presence / absence of a defective element and discriminating a good product / a defective product of an LSI chip will be described. FIG. 5 shows a case where a defect occurs in the gate of the MOS field effect transistor and a minute current flows (gate leak).
Shown in. MH1 and MH3 are p-channel field effect transistors, MH2 and MH4 are n-channel field effect transistors, PL1 is a high potential power supply line, and PL2 is a low potential power supply line. EX1 is a pad provided in PL1 to which a high potential (VDD) power supply is connected. EX2 is a pad provided on PL2 and is grounded (GND). Further, INV1 and INV2 represent inverter circuits as examples of logic circuits. N1 and N2 are input terminals of INV1 and INV2. Here, there is a defect in MH4 forming INV2, and there is a defect between the gate electrode (the same potential as N2) and the source (G
Current flows to the ND) and N1 is at a low potential (GN
A general discrimination test method will be described by taking as an example the case where D level) and N2 are at high potential (VDD level). If there is such a defect as described above, even when the potential of the input terminal of each node does not change, that is, even when the circuit is not operating, a large leakage current 1g is generated between PL1 and PL2 as indicated by Ig.
(Eg 1 microamp or more) flows. Therefore, by measuring the current flowing from the VDD power supply connected to EX1, it is possible to know the presence or absence of a defect and to determine the defective chip. In the standby mode, a subthreshold leak current (Is) flows in addition to the leak current due to the defect. The magnitude of this current depends on the threshold voltage of the transistor. If the absolute value of the threshold voltage is not extremely small, the subthreshold leakage current is sufficiently smaller than the current due to the defect (for example, 10 nanoamperes), and does not affect the defective product selection of the chip.
【０００３】しかしながら、近年、電池駆動可能な各種
機器のために、回路の低電圧動作化が進められており、
しきい値を非常に低い値に設定したトランジスタを用い
る回路が提案されている。一例を図６に示す。低しきい
値電圧ＭＯＳ型電界効果トランジスタは記号Ｍ１〜Ｍ４
で表す。また、高しきい値電圧ＭＯＳ型電界効果トラン
ジスタは記号ＭＨ１、ＭＨ２で表す。低しきい値電圧ト
ランジスタ（Ｍ１〜Ｍ４）で構成された論理回路例とし
て、インバータ回路をＩＮＶ１、ＩＮＶ２で表す。Ｎ
１、Ｎ２はそれぞれＩＮＶ１、ＩＮＶ２の入力端子であ
る。ＰＬ１は高電位の電源線、ＰＬ２は低電位の電源線
である。ＥＸ１はＰＬ１に設けられたパッドで、高電位
（ＶＤＤ）電源が接続される。ＥＸ２はＰＬ２に設けら
れたパッドで、通常接地される（ＧＮＤ）。ＩＮＶ１、
ＩＮＶ２は共通の疑似電源線ＱＬ１、ＱＬ２に接続され
ている。疑似電源線ＱＬ１は高しきい値電圧トランジス
タＭＨ１の出力電極を介して電源線ＰＬ１に接続され、
疑似電源線ＱＬ２はトランジスタＭＨ２の出力電極を介
して電源線ＰＬ２に接続されている。ｐチャネル型トラ
ンジスタＭＨ１は、電源電圧ＶＤＤが供給される電源線
ＰＬ１と疑似電源線ＱＬ１との接続をオン／オフし、ｎ
チャネル型トランジスタＭＨ２は接地された電源線ＰＬ
２と、疑似電源線ＱＬ２との接続をオン／オフする機能
を有する。ＮＣ１、ＮＣ２はそれぞれＭＨ１、ＭＨ２の
オン／オフを制御するための信号線を接続する端子であ
る。判別試験中は制御信号ＮＣ１を低電位、ＮＣ２を高
電位にして、ＭＨ１とＭＨ２をオン状態にする。ＰＬ１
とＱＬ１、ＰＬ２とＱＬ２はそれぞれ同電位になり、各
トランジスタに電源が供給される。ここで、ＩＮＶ２を
構成するＭ４に欠陥が存在し、ゲート電極（Ｎ２と同電
位）とソース間（ＧＮＤに接続）に電流が流れ得るもの
とする。また、Ｎ１が低電位（ＧＮＤレベル）、Ｎ２が
高電位（ＶＤＤレベル）として、従来の問題点について
説明する。上記の欠陥が存在すると、Ｉｇで示すような
貫通電流パスが形成され、ＰＬ１とＰＬ２との間に欠陥
によるリーク電流１ｇ（例えば、１マイクロアンペア以
上）が流れる。さらには、トランジスタＭ１〜Ｍ４のし
きい値電圧が低いために、著しく大きいサブスレッショ
ルドリーク電流Ｉｓ（例えば１０マイクロアンペア）も
流れる。この値は欠陥によるリーク電流に比べて大き
い。したがって、ＥＸ１に接続されたＶＤＤ電源から流
れる電流を測定しても、それが、素子の欠陥によるリー
ク電流なのか、それとも欠陥に関係のないサブスレッシ
ョルドリーク電流なのかを判別できないことになる。However, in recent years, low voltage operation of circuits has been promoted for various battery-operable devices,
A circuit using a transistor having a threshold value set to a very low value has been proposed. An example is shown in FIG. The low threshold voltage MOS field effect transistors have the symbols M1 to M4.
It is represented by. The high threshold voltage MOS field effect transistor is represented by symbols MH1 and MH2. As an example of a logic circuit including low threshold voltage transistors (M1 to M4), inverter circuits are represented by INV1 and INV2. N
Reference numerals 1 and N2 are input terminals of INV1 and INV2, respectively. PL1 is a high potential power supply line, and PL2 is a low potential power supply line. EX1 is a pad provided in PL1 to which a high potential (VDD) power supply is connected. EX2 is a pad provided in PL2 and is normally grounded (GND). INV1,
INV2 is connected to the common pseudo power supply lines QL1 and QL2. The pseudo power supply line QL1 is connected to the power supply line PL1 via the output electrode of the high threshold voltage transistor MH1.
The pseudo power line QL2 is connected to the power line PL2 via the output electrode of the transistor MH2. The p-channel transistor MH1 turns on / off the connection between the power supply line PL1 to which the power supply voltage VDD is supplied and the pseudo power supply line QL1,
The channel type transistor MH2 is a grounded power line PL
2 and the pseudo power supply line QL2. NC1 and NC2 are terminals for connecting signal lines for controlling ON / OFF of MH1 and MH2, respectively. During the discrimination test, the control signal NC1 is set to low potential and NC2 is set to high potential to turn on MH1 and MH2. PL1
And QL1 and PL2 and QL2 have the same potential, and power is supplied to each transistor. Here, it is assumed that there is a defect in M4 forming INV2 and a current can flow between the gate electrode (the same potential as N2) and the source (connected to GND). Further, the conventional problems will be described assuming that N1 is a low potential (GND level) and N2 is a high potential (VDD level). When the above defect exists, a through current path as indicated by Ig is formed, and a leak current 1g (for example, 1 microampere or more) due to the defect flows between PL1 and PL2. Further, since the threshold voltages of the transistors M1 to M4 are low, a remarkably large subthreshold leakage current Is (for example, 10 microamperes) also flows. This value is larger than the leak current due to the defect. Therefore, even if the current flowing from the VDD power supply connected to EX1 is measured, it is not possible to determine whether it is the leak current due to the defect of the element or the subthreshold leak current unrelated to the defect.
【０００４】[0004]
【発明が解決しようとする課題】以上のように、しきい
値を低い値に設定し、サブスレッショルドリーク電流の
大きいトランジスタを用いたＬＳＩにおいては、ＬＳＩ
を構成する素子（トランジスタ等）に欠陥が生じた場合
にも、欠陥の有無を知り、欠陥を含んだチップを選別す
ることができないという問題があった。本発明はこのよ
うな状況に鑑みなされたもので、低しきい値電圧トラン
ジスタによる大きなサブスレッショルドリーク電流の影
響を排除し、欠陥素子の有無を容易に判別できる論理回
路を提供することを目的とする。As described above, in the LSI using the transistor with the threshold value set to a low value and the large subthreshold leakage current,
Even if a defect occurs in the element (transistor or the like) constituting the device, there is a problem that it is not possible to know the presence or absence of the defect and select the chip including the defect. The present invention has been made in view of such circumstances, and an object of the present invention is to provide a logic circuit that eliminates the influence of a large subthreshold leakage current due to a low threshold voltage transistor and can easily determine the presence or absence of a defective element. To do.
【０００５】[0005]
【課題を解決するための手段】上記目的を達成するた
め、本発明では、例えば図１に示すように、第１の擬似
電源線例えばＱＬ１と第２の擬似電源線例えばＱＬ２と
の間に低いしきい値電圧のＭＯＳ型電界効果トランジス
タ例えばＭ１〜Ｍ４から成る論理回路群を有し、第１の
擬似電源線ＱＬ１と第１の電源線ＰＬ１との間、および
第２の擬似電源線ＱＬ２と第２の電源線ＰＬ２との間に
それぞれ高いしきい値電圧のＭＯＳ型電界効果トランジ
スタＭＨ１およびＭＨ２を有する論理回路において、上
記論理回路群を構成する低いしきい値電圧の電界効果ト
ランジスタＭ１〜Ｍ４のうち、ＰチャネルＭＯＳ型電界
効果トランジスタＭ１、Ｍ３の基板ノードを第１の電源
線ＰＬ１に接続し、ＮチャネルＭＯＳ型電界効果トラン
ジスタＭ２、Ｍ４の基板ノードを第２の電源線ＰＬ２に
接続し、かつ、上記第１および第２の擬似電源線にパッ
ドＥＸＱ１、ＥＸＱ２を設け、該パッドを試験用端子と
する構成を備えることとする。In order to achieve the above object, in the present invention, for example, as shown in FIG. 1, a low voltage is provided between a first pseudo power supply line such as QL1 and a second pseudo power supply line such as QL2. It has a logic circuit group composed of MOS field effect transistors of threshold voltage, for example, M1 to M4, and is provided between the first pseudo power supply line QL1 and the first power supply line PL1 and the second pseudo power supply line QL2. In a logic circuit having high threshold voltage MOS field effect transistors MH1 and MH2 respectively between the second power supply line PL2 and low threshold voltage field effect transistors M1 to M4 constituting the logic circuit group. Of these, the substrate nodes of the P-channel MOS field effect transistors M1 and M3 are connected to the first power supply line PL1, and the N-channel MOS field effect transistors M2 and M4 are connected. Connect the plate node to the second power supply line PL2, and the pad EXQ1, EXQ2 provided in the first and second dummy power line, and further comprising a structure for the test terminal the pad.
【０００６】あるいは上記目的を達成するため、本発明
では、例えば図３に示すように、第１の擬似電源線例え
ばＱＬ１と第２の擬似電源線例えばＱＬ２との間に低い
しきい値電圧のＭＯＳ型電界効果トランジスタ例えばＭ
１〜Ｍ４から成る論理回路群を有し、第１の擬似電源線
ＱＬ１と第１の電源線ＰＬ１との間、および第２の擬似
電源線ＱＬ２と第２の電源線ＰＬ２との間にそれぞれ高
いしきい値電圧のＭＯＳ型電界効果トランジスタＭＨ１
およびＭＨ２を有する論理回路において、上記論理回路
群を構成する低いしきい値電圧の電界効果トランジスタ
Ｍ１〜Ｍ４のうち、ＰチャネルＭＯＳ型電界効果トラン
ジスタＭ１、Ｍ３の基板ノードを第１の電源線ＰＬ１に
接続し、ＮチャネルＭＯＳ型電界効果トランジスタＭ
２、Ｍ４の基板ノードを第２の電源線ＰＬ２に接続し、
かつ、上記第１の擬似電源線ＱＬ１を第１の電源変換回
路ＶＧ１を介して第１の電源線ＰＬ１に接続し、上記第
２の擬似電源線ＱＬ２を第２の電源変換回路ＶＧ２を介
して第２の電源線ＰＬ２に接続する構成を備えることと
する。そして試験実施時には、電源変換回路を動作さ
せ、この回路を介して擬似電源線への電圧を与えるよう
にすればよい。To achieve the above object, in the present invention, as shown in FIG. 3, for example, a low threshold voltage is applied between the first pseudo power supply line QL1 and the second pseudo power supply line QL2. MOS field effect transistor, eg M
1-M4 logic circuit group, and between the first pseudo power supply line QL1 and the first power supply line PL1, and between the second pseudo power supply line QL2 and the second power supply line PL2, respectively. High threshold voltage MOS field effect transistor MH1
And MH2, the P-channel MOS type field effect transistors M1 and M3 among the low threshold voltage field effect transistors M1 to M4 forming the logic circuit group are connected to the first power supply line PL1. Connected to the N-channel MOS field effect transistor M
2, connect the substrate node of M4 to the second power supply line PL2,
Moreover, the first pseudo power supply line QL1 is connected to the first power supply line PL1 via the first power supply conversion circuit VG1, and the second pseudo power supply line QL2 is connected via the second power supply conversion circuit VG2. A structure for connecting to the second power supply line PL2 is provided. Then, at the time of performing the test, the power supply conversion circuit may be operated and a voltage may be applied to the pseudo power supply line via this circuit.
【０００７】[0007]
【作用】本発明で、擬似電源線に接続した論理回路群を
構成する低いしきい値電圧の電界効果トランジスタの基
板ノードを電源線に接続し、またその擬似電源線を高い
しきい値電圧の電界効果トランジスタを介して電源線に
接続する構成により、通常動作時は、高いしきい値電圧
の電界効果トランジスタをオン状態にすれば、これによ
り、基板ノードを電源線に接続した上記トランジスタは
低いしきい値電圧を有する状態において通常の動作をす
ることができる。またその一方、試験期間中は、上記の
高いしきい値電圧の電界効果トランジスタをオフ状態に
し、擬似電源線の試験用端子を通じて、または電源線に
接続した電源変換回路を介して擬似電源線に試験用電圧
を与えるようにすることにより、上記の低いしきい値電
圧の電界効果トランジスタを一時的に高いしきい値電圧
を有するようにすることが可能になる。このため、試験
に際して上記の低いしきい値電圧の電界効果トランジス
タに流れるサブスレッショルドリーク電流を著しく低減
できるようになり、その結果、トランジスタの欠陥によ
るリーク電流の判別が容易になる。In the present invention, the substrate node of the low threshold voltage field effect transistor forming the logic circuit group connected to the pseudo power supply line is connected to the power supply line, and the pseudo power supply line is connected to the high threshold voltage. With the configuration in which the field effect transistor is connected to the power supply line, the field effect transistor having a high threshold voltage is turned on in the normal operation, whereby the transistor connecting the substrate node to the power supply line is low. Normal operation can be performed in a state having a threshold voltage. On the other hand, during the test period, the field effect transistor with the high threshold voltage is turned off, and the pseudo power supply line is connected to the pseudo power supply line through the test terminal of the pseudo power supply line or the power conversion circuit connected to the power supply line. By applying the test voltage, it becomes possible to temporarily make the field effect transistor having the above low threshold voltage have the high threshold voltage. Therefore, the subthreshold leak current flowing through the field effect transistor having the low threshold voltage during the test can be remarkably reduced, and as a result, the leak current due to the defect of the transistor can be easily identified.
【０００８】[0008]
【実施例】図１に第１の発明の第１の実施例を示す。低
しきい値電圧を有するＭＯＳ型電界効果トランジスタは
記号Ｍ１〜Ｍ４で表す。また、高しきい値電圧を有する
ＭＯＳ型電界効果トランジスタは記号ＭＨ１、ＭＨ２で
表す。論理回路の例としてＩＮＶ１、ＩＮＶ２はそれぞ
れインバータ回路を示す。Ｎ１、Ｎ２はＩＮＶ１、ＩＮ
Ｖ２の入力端子である。ＰＬ１は高電位の電源線、ＰＬ
２は低電位の電源線である。ＥＸ１はＰＬ１に設けられ
たパッドで、高電位（ＶＤＤ）電源が接続される。ＥＸ
２はＰＬ２に設けられたパッドで、通常接地される（Ｇ
ＮＤ）。ｐチャネル型トランジスタＭＨ１は、電源電圧
ＶＤＤが供給される電源線ＰＬ１と擬似電源線ＱＬ１と
の接続をオン／オフし、ｎチャネル型トランジスタＭＨ
２は接地された電源線ＰＬ２と、擬似電源線ＱＬ２との
接続をオン／オフする機能を有する。ＮＣ１、ＮＣ２は
それぞれＭＨ１、ＭＨ２のオン／オフ状態を制御するた
めの信号線を接続する端子である。低しきい値電圧トラ
ンジスタ（Ｍ１〜Ｍ４）で構成された論理回路は共通の
擬似電源線ＱＬ１、ＱＬ２に接続されている。擬似電源
線ＱＬ１及びＱＬ２にはパッドＥＸＱ１、ＥＸＱ２が設
けられている。擬似電源線ＱＬ１は高しきい値電圧トラ
ンジスタＭＨ１の出力電極を介して電源線ＰＬ１に接続
される。また擬似電源線ＱＬ２は高しきい値電圧トラン
ジスタＭＨ２の出力電極を介して電源線ＰＬ２に接続さ
れる。低しきい値のｐチャネルトランジスタＭ１とＭ3
の基板ノードは電源線ＰＬ１に接続される。また、低し
きい値のｎチャネルトランジスタＭ２とＭ４の基板ノー
ドは電源線ＰＬ２に接続される。ＥＸＱ１とＥＸＱ２を
試験用端子として用いた試験法について、以下に説明す
る。試験期間中においては、各部を以下に示す状態に保
つ。制御信号ＮＣ１を高電位、ＮＣ２を低電位にして、
ＭＨ１とＭＨ２をオフ状態に保つ。パッドＥＸＱ１、Ｅ
ＸＱ２に電源を接続し、ＰＬ１の電位（例えば３Ｖ）＞
ＱＬ１電位（例えば２Ｖ）＞ＱＬ２電位（例えば１Ｖ）
＞ＰＬ２電位（例えば０Ｖ）となるように擬似電源線Ｑ
Ｌ１、ＱＬ２の電位を固定する。ｐチャネルトランジス
タＭ１に注目する。基板の電位（即ちＰＬ１電位）がソ
ースの電位（即ちＱＬ１電位）より高くなるようにＱＬ
１の電位を設定しているため、Ｍ１のしきい値電圧（絶
対値）はその差分だけ大きくなる。また、ｎチャネルト
ランジスタＭ２に注目する。基板の電位（即ちＰＬ２電
位）がソースの電位（即ちＱＬ２電位）より低くなるよ
うにＱＬ２の電位を設定しているため、Ｍ２のしきい値
電圧はその差分だけ高くなる。Ｍ３、Ｍ４についても同
様である。このように、低しきい値トランジスタのしき
い値電圧を一時的に高くすることにより、サブスレッシ
ョルド電流を著しく（例えば１０nＡ以下に）低減する
ことが可能となる。ここで、素子の欠陥により、Ｉｇで
示すような大きな欠陥リーク電流（例えば１マイクロア
ンペア以上）が流れた場合を想定する。ＥＸＱ１に接続
した電源からは、欠陥によるリーク電流（１ｇ）とサブ
スレッショルドリーク電流（１ｓ）の和の分の電流が流
れるが、サブスレッショルドリーク電流を強制的に低減
させ、十分小さな値となっているため、欠陥による電流
の有無を判別することが可能となる。即ち、測定対象と
なるＬＳＩチップ内の素子の欠陥の有無を確かめること
ができる。なお、判別試験中はＮＣ１を高電位に、また
ＮＣ２を低電位にし、ＭＨ１及びＭＨ２をカットオフ状
態にする。ＭＨ１とＭＨ２のしきい値電圧は十分に大き
いため、ＰＬ１からＱＬ１へ、また、ＰＬ２からＱＬ２
へのサブスレッショルド電流は十分に小さく、その影響
は無視できる。FIG. 1 shows a first embodiment of the first invention. MOS field effect transistors having a low threshold voltage are represented by the symbols M1 to M4. Further, MOS field effect transistors having a high threshold voltage are represented by symbols MH1 and MH2. INV1 and INV2 each represent an inverter circuit as an example of a logic circuit. N1 and N2 are INV1 and IN
This is an input terminal for V2. PL1 is a high-potential power line, PL
Reference numeral 2 is a low-potential power supply line. EX1 is a pad provided in PL1 to which a high potential (VDD) power supply is connected. EX
2 is a pad provided on PL2, which is normally grounded (G
ND). The p-channel transistor MH1 turns on / off the connection between the power supply line PL1 to which the power supply voltage VDD is supplied and the pseudo power supply line QL1, and the n-channel transistor MH1.
2 has a function of turning on / off the connection between the grounded power supply line PL2 and the pseudo power supply line QL2. NC1 and NC2 are terminals for connecting signal lines for controlling ON / OFF states of MH1 and MH2, respectively. A logic circuit composed of low threshold voltage transistors (M1 to M4) is connected to common pseudo power supply lines QL1 and QL2. Pads EXQ1 and EXQ2 are provided on the pseudo power supply lines QL1 and QL2. The pseudo power supply line QL1 is connected to the power supply line PL1 via the output electrode of the high threshold voltage transistor MH1. The pseudo power supply line QL2 is connected to the power supply line PL2 via the output electrode of the high threshold voltage transistor MH2. Low threshold p-channel transistors M1 and M3
The substrate node of is connected to the power supply line PL1. The substrate nodes of the low threshold n-channel transistors M2 and M4 are connected to the power supply line PL2. A test method using EXQ1 and EXQ2 as test terminals will be described below. During the test period, keep each part in the following condition. The control signal NC1 is set to high potential and NC2 is set to low potential,
Keep MH1 and MH2 off. Pad EXQ1, E
Connect a power supply to XQ2, and the potential of PL1 (eg 3V)>
QL1 potential (eg 2V)> QL2 potential (eg 1V)
> Pseudo power supply line Q so that it becomes PL2 potential (for example, 0V)
The potentials of L1 and QL2 are fixed. Attention is paid to the p-channel transistor M1. QL so that the potential of the substrate (that is, the PL1 potential) becomes higher than the potential of the source (that is, the QL1 potential).
Since the potential of 1 is set, the threshold voltage (absolute value) of M1 increases by the difference. Also, pay attention to the n-channel transistor M2. Since the potential of QL2 is set so that the potential of the substrate (that is, the PL2 potential) becomes lower than the potential of the source (that is, the QL2 potential), the threshold voltage of M2 increases by the difference. The same applies to M3 and M4. Thus, by temporarily increasing the threshold voltage of the low threshold transistor, the subthreshold current can be significantly reduced (for example, 10 nA or less). Here, it is assumed that a large defect leak current (eg, 1 microamperes or more) as indicated by Ig flows due to a defect in the device. From the power supply connected to EXQ1, a current corresponding to the sum of the leak current (1 g) due to the defect and the subthreshold leak current (1 s) flows, but the subthreshold leak current is forcibly reduced to a sufficiently small value. Therefore, it is possible to determine the presence or absence of a current due to a defect. That is, it is possible to confirm whether or not there is a defect in the element in the LSI chip to be measured. During the discrimination test, NC1 is set to a high potential, NC2 is set to a low potential, and MH1 and MH2 are cut off. Since the threshold voltage of MH1 and MH2 is sufficiently large, PL1 to QL1 and PL2 to QL2
The sub-threshold current to is sufficiently small and its effect is negligible.
【０００９】図２に第１の発明の第２の実施例を示す。
ＳＥＬはセレクタで、ＣＳＥＬはセレクタを制御する信
号を接続する端子である。他の接続関係、記号について
は第１の実施例と同じである。例えば、ＬＳＩの通常動
作時にはＣＳＥＬによりセレクタを制御し、ＱＬ１とＥ
ＸＱ１、ＱＬ２とＥＸＱ２がそれぞれ電気的に切り離さ
れている状態にする。不良チップ判別試験時には、ＣＳ
ＥＬによりセレクタを制御し、ＱＬ１とＥＸＱ１、ＱＬ
２とＥＸＱ２がそれぞれ電気的に接続されている状態に
する。試験の手法については第１の実施例に記載のとお
りである。第１の実施例とはセレクタを介しＱＬ１とＥ
ＸＱ１、ＱＬ２とＥＸＱ２を各々接続することが異な
る。試験期間でない、すなわち通常の動作期間におい
て、擬似電源線をパッドから電気的に切り離すことによ
り、パッドを介する試験回路系の影響が論理回路の動作
に及ばないようにすることが可能になる利点がある。な
お本実施例にはスイッチの部分については具体的に記載
されていないが、それが電界効果型トランジスタの単体
で構成されるスイッチであっても、複数のトランジスタ
から構成されるスイッチであっても、また、他のスイッ
チ素子であっても、上記の機能を有するものであれば、
本実施例に適用できることは勿論である。FIG. 2 shows a second embodiment of the first invention.
SEL is a selector, and CSEL is a terminal for connecting a signal for controlling the selector. Other connection relations and symbols are the same as those in the first embodiment. For example, during normal operation of the LSI, the selector is controlled by CSEL so that QL1 and E
The XQ1, QL2 and EXQ2 are electrically disconnected from each other. At the time of defective chip discrimination test, CS
Selector is controlled by EL, QL1 and EXQ1, QL
2 and EXQ2 are electrically connected to each other. The test method is as described in the first example. In the first embodiment, QL1 and E are connected via a selector.
It is different in connecting XQ1, QL2 and EXQ2. By electrically disconnecting the pseudo power supply line from the pad during the non-test period, that is, during the normal operation period, it is possible to prevent the influence of the test circuit system via the pad from affecting the operation of the logic circuit. is there. Although the switch part is not specifically described in this embodiment, it may be a switch composed of a single field effect transistor or a switch composed of a plurality of transistors. , And other switch elements as long as they have the above functions,
Of course, it can be applied to this embodiment.
【００１０】図３に第２の発明の実施例を示す。ＶＧ１
とＶＧ２は電源変換回路、ＣＶＧは電源変換回路の動作
を制御するための信号線を接続する端子である。他の接
続関係、記号については第１の実施例と同じである。Ｖ
Ｇ１はＱＬ１をＰＬ１より低い電位に決める機能を有す
る。また、ＶＧ２はＰＬ２をＱＬ２より低い電位に決め
る機能を有する。ＬＳＩの通常動作時にはＮＣ１を低電
位に、またＮＣ２を高電位にしてＭＨ１及びＭＨ２をオ
ン状態にしている。その際にはＶＧ１、ＶＧ２が機能し
ないようにし、ＶＧ１、ＶＧ２内ではＰＬ１とＱＬ１、
ＰＬ２とＱＬ２がそれぞれ電気的に切り離されている状
態にする。不良チップ判別試験時にはＮＣ１を高電位
に、またＮＣ２を低電位にし、ＭＨ１及びＭＨ２をカッ
トオフ状態にする。同時にＣＶＧにより電源変換回路を
機能させ、ＰＬ１の電位（例えば３Ｖ）＞ＱＬ１電位
（例えば２Ｖ）＞ＱＬ２電位（例えば１Ｖ）＞ＰＬ２電
位（例えば０Ｖ）となるように擬似電源線ＱＬ１、ＱＬ
２の電位を定める。試験の手法については電流を測定す
る端子がＥＸ１になることを除き、第１の発明の第１の
実施例に記載のとおりである。FIG. 3 shows an embodiment of the second invention. VG1
And VG2 are power supply conversion circuits, and CVG is a terminal for connecting a signal line for controlling the operation of the power supply conversion circuit. Other connection relations and symbols are the same as those in the first embodiment. V
G1 has a function of setting QL1 to a potential lower than PL1. Further, VG2 has a function of determining PL2 at a potential lower than QL2. During normal operation of the LSI, NC1 is set to a low potential and NC2 is set to a high potential to turn on MH1 and MH2. At that time, VG1 and VG2 are prevented from functioning, and PL1 and QL1 in VG1 and VG2 are
PL2 and QL2 are electrically disconnected from each other. At the time of the defective chip discrimination test, NC1 is set to a high potential, NC2 is set to a low potential, and MH1 and MH2 are cut off. Simultaneously, the power supply conversion circuit is made to function by CVG, and the pseudo power supply lines QL1 and QL are set so that the potential of PL1 (for example, 3V)> QL1 potential (for example, 2V)> QL2 potential (for example, 1V)> PL2 potential (for example, 0V).
Determine the potential of 2. The test method is as described in the first embodiment of the first invention except that the terminal for measuring the current is EX1.
【００１１】ＶＧ１及びＶＧ２の実際の回路構成例を図
４に示す。図４においてＤ１、Ｄ２はダイオード、ＭＨ
５は高しきい値電圧のｐチャネル型電界効果トランジス
タ、ＭＨ6は高しきい値電圧のｎチャネル型電界効果ト
ランジスタ、ＩＮＶ３はインバータ回路である。ＬＳＩ
の通常動作時にはＣＶＧを高電位にすることによりＭＨ
５とＭＨ６とオフ状態に保ち、ＰＬ１とＱＬ１、ＰＬ２
とＱＬ２をそれぞれ電気的に切り離した状態にする。不
良チップ判別試験時には、ＣＶＧを低電位にし、ＭＨ５
とＭＨ６をオン状態に保つ。ダイオードはそれ自身の入
力電位からしきい値電圧分を減じた値を出力するため、
ＱＬ１の電位をＰＬ１の電位より低く、また、ＰＬ２の
電位をＱＬ２より低くすることが可能となる。なお、本
回路例は単なる一例に過ぎず、以上のような電源変換機
能を有する回路であれば、いずれも第２の発明の実施例
に適用可能である。FIG. 4 shows an example of the actual circuit configuration of VG1 and VG2. In FIG. 4, D1 and D2 are diodes and MH
Reference numeral 5 is a high threshold voltage p-channel field effect transistor, MH6 is a high threshold voltage n-channel field effect transistor, and INV3 is an inverter circuit. LSI
During normal operation of MH, by setting CVG to high potential, MH
5 and MH6 are kept off, PL1 and QL1, PL2
And QL2 are electrically disconnected. At the time of the defective chip discrimination test, CVG is set to a low potential and MH5
And keep MH6 on. Since the diode outputs the value obtained by subtracting the threshold voltage from the input potential of itself,
It is possible to make the potential of QL1 lower than the potential of PL1 and the potential of PL2 lower than QL2. Note that this circuit example is merely an example, and any circuit having the power conversion function as described above can be applied to the embodiment of the second invention.
【００１２】[0012]
【発明の効果】以上説明したように本発明の論理回路で
は、低しきい値トランジスタのしきい値を試験期間中に
限って大きくするように擬似電源線の電位を固定するこ
とにより、サブスレッショルドリーク電流が抑えられ、
欠陥によるリーク電流の測定が可能となる。したがっ
て、ＬＳＩチップ内の欠陥素子の有無を容易に判別でき
るという効果がある。特に擬似電源線と電源線との間に
電源変換回路を接続する実施例の場合、試験用の特別な
パッドは電源変換回路を制御する信号の入力端子用の一
つで済む。これはＬＳＩの外部ピン数低減につながり、
ＬＳＩチップの面積低減、安価化の効果がある。As described above, in the logic circuit of the present invention, the subthreshold voltage is fixed by fixing the potential of the pseudo power supply line so that the threshold value of the low threshold transistor is increased only during the test period. Leak current is suppressed,
It is possible to measure the leak current due to the defect. Therefore, the presence or absence of the defective element in the LSI chip can be easily determined. Particularly in the case of the embodiment in which the power supply conversion circuit is connected between the pseudo power supply line and the power supply line, the special pad for the test is only one for the input terminal of the signal for controlling the power supply conversion circuit. This leads to a reduction in the number of external pins on the LSI,
The area of the LSI chip is reduced and the cost is reduced.
【図面の簡単な説明】[Brief description of drawings]
【図１】第１の発明の第１の実施例を示す図。FIG. 1 is a diagram showing a first embodiment of the first invention.
【図２】第１の発明の第２の実施例を示す図。FIG. 2 is a diagram showing a second embodiment of the first invention.
【図３】第２の発明の実施例を示す図。FIG. 3 is a diagram showing an embodiment of the second invention.
【図４】図３におけるＶＧの実際構成例を示す図。4 is a diagram showing an example of the actual configuration of a VG in FIG.
【図５】チップ不良判別の一般的な方法を説明するため
の図。FIG. 5 is a diagram for explaining a general method for determining a chip defect.
【図６】従来例を示す図。FIG. 6 is a diagram showing a conventional example.
ＰＬ１、ＰＬ２…電源線 ＱＬ１、ＰＬ２…擬似電源線 ＥＸ１、ＥＸ２…電源線用パッド ＥＸＱ１、ＥＸＱ２…擬似電源線用パッド ＶＤＤ…高電位電源 ＧＮＤ…接地電位（低電位電源） Ｍ１、Ｍ３…低しきい値Ｐ−ch ＭＯＳ型電界効果トラ
ンジスタ Ｍ２、Ｍ４…低しきい値Ｎ−ch ＭＯＳ型電界効果トラ
ンジスタ ＭＨ１、ＭＨ３、ＭＨ５…高しきい値Ｐ−ch ＭＯＳ型
電界効果トランジスタ ＭＨ２、ＭＨ４、ＭＨ６…高しきい値Ｎ−ch ＭＯＳ型
電界効果トランジスタ Ｎ１、Ｎ２、ＮＣ１、ＮＣ２、ＣＳＥＬ、ＣＶＧ…信号
入力端子 ＩＮＶ１、ＩＮＶ２、ＩＮＶ３…インバータ回路 ＳＥＬ…セレクタ回路 ＶＧ１、ＶＧ２…電源変換回路 Ｉｇ…欠陥によるリーク電流 Ｉｓ…サブスレッショルドリーク電流PL1, PL2 ... Power supply lines QL1, PL2 ... Pseudo power supply lines EX1, EX2 ... Power supply line pads EXQ1, EXQ2 ... Pseudo power supply line pads VDD ... High potential power supply GND ... Ground potential (low potential power supply) M1, M3 ... Low Threshold value P-ch MOS field effect transistor M2, M4 ... Low threshold N-ch MOS field effect transistor MH1, MH3, MH5 ... High threshold P-ch MOS field effect transistor MH2, MH4, MH6 ... High threshold N-ch MOS type field effect transistor N1, N2, NC1, NC2, CSEL, CVG ... Signal input terminal INV1, INV2, INV3 ... Inverter circuit SEL ... Selector circuit VG1, VG2 ... Power supply conversion circuit Ig ... Due to defects Leakage current Is ... Subthreshold leakage current
───────────────────────────────────────────────────── フロントページの続き (72)発明者 山田 順三 東京都千代田区内幸町１丁目１番６号 日 本電信電話株式会社内 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Junzo Yamada 1-1-6 Uchisaiwaicho, Chiyoda-ku, Tokyo Nihon Telegraph and Telephone Corporation
Claims (2)
とＮチャネルＭＯＳ型電界効果トランジスタのそれぞれ
の中で低いしきい値電圧のトランジスタと高いしきい値
電圧のトランジスタとを備え、上記低いしきい値電圧の
トランジスタで論理回路群を構成し、該論理回路群の第
１の電源端子部を共通の第１の擬似電源線に接続し、該
第１の擬似電源線は高いしきい値電圧のトランジスタを
介して第１の電源線に接続し、上記論理回路群の第２の
電源端子部を共通の第２の擬似電源線に接続し、該第２
の擬似電源線は高いしきい値電圧のトランジスタを介し
て第２の電源線に接続した論理回路において、 上記論理回路群を構成する低いしきい値電圧の電界効果
トランジスタのうち、ＰチャネルＭＯＳ型電界効果トラ
ンジスタの基板ノードを第１の電源線に接続し、Ｎチャ
ネルＭＯＳ型電界効果トランジスタの基板ノードを第２
の電源線に接続し、かつ、上記第１および第２の擬似電
源線にパッドを設け、該パッドを試験用端子とする構成
を特徴とする論理回路。1. A P-channel MOS type field effect transistor and an N-channel MOS type field effect transistor each having a low threshold voltage transistor and a high threshold voltage transistor, wherein said low threshold voltage is used. Of the logic circuit group and the first power supply terminal portion of the logic circuit group is connected to a common first pseudo power supply line, and the first pseudo power supply line is a transistor having a high threshold voltage. To the first power supply line, the second power supply terminal portion of the logic circuit group is connected to a common second pseudo power supply line, and
In the logic circuit in which the pseudo power supply line is connected to the second power supply line through the transistor having the high threshold voltage, the P-channel MOS type among the field effect transistors having the low threshold voltage forming the logic circuit group is used. The substrate node of the field effect transistor is connected to the first power supply line, and the substrate node of the N-channel MOS field effect transistor is connected to the second power line.
And a pad provided on the first and second pseudo power supply lines, and the pad is used as a test terminal.
とＮチャネルＭＯＳ型電界効果トランジスタのそれぞれ
の中で低いしきい値電圧のトランジスタと高いしきい値
電圧のトランジスタとを備え、上記低いしきい値電圧の
トランジスタで論理回路群を構成し、該論理回路群の第
１の電源端子部を共通の第１の擬似電源線に接続し、該
第１の擬似電源線は高いしきい値電圧のトランジスタを
介して第１の電源線に接続し、上記論理回路群の第２の
電源端子部を共通の第２の擬似電源線に接続し、該第２
の擬似電源線は高いしきい値電圧のトランジスタを介し
て第２の電源線に接続した論理回路において、 上記論理回路群を構成する低いしきい値電圧の電界効果
トランジスタのうち、ＰチャネルＭＯＳ型電界効果トラ
ンジスタの基板ノードを第１の電源線に接続し、Ｎチャ
ネルＭＯＳ型電界効果トランジスタの基板ノードを第２
の電源線に接続し、かつ、上記第１の擬似電源線を第１
の電源変換回路を介して第１の電源線に接続し、上記第
２の擬似電源線を第２の電源変換回路を介して第２の電
源線に接続する構成を特徴とする論理回路。2. A P-channel MOS field effect transistor and an N-channel MOS field effect transistor each having a low threshold voltage transistor and a high threshold voltage transistor. Of the logic circuit group and the first power supply terminal portion of the logic circuit group is connected to a common first pseudo power supply line, and the first pseudo power supply line is a transistor having a high threshold voltage. To the first power supply line, the second power supply terminal portion of the logic circuit group is connected to a common second pseudo power supply line, and
In the logic circuit in which the pseudo power supply line is connected to the second power supply line through the transistor having the high threshold voltage, the P-channel MOS type among the field effect transistors having the low threshold voltage forming the logic circuit group is used. The substrate node of the field effect transistor is connected to the first power supply line, and the substrate node of the N-channel MOS field effect transistor is connected to the second power line.
Connected to the power supply line of the
A logic circuit characterized in that it is connected to the first power supply line via the power supply conversion circuit and the second pseudo power supply line is connected to the second power supply line via the second power supply conversion circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12240793A JP3157649B2 (en) | 1993-05-25 | 1993-05-25 | Logic circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP12240793A JP3157649B2 (en) | 1993-05-25 | 1993-05-25 | Logic circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH06334010A true JPH06334010A (en) | 1994-12-02 |
| JP3157649B2 JP3157649B2 (en) | 2001-04-16 |
Family
ID=14835039
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP12240793A Expired - Lifetime JP3157649B2 (en) | 1993-05-25 | 1993-05-25 | Logic circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3157649B2 (en) |
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- 1993-05-25 JP JP12240793A patent/JP3157649B2/en not_active Expired - Lifetime
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| Publication number | Publication date |
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| JP3157649B2 (en) | 2001-04-16 |
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