JP3060617B2 - Output buffer circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an output buffer circuit, and more particularly to an output buffer circuit having a CMOS transistor structure.

[0002]

2. Description of the Related Art FIG. 3 is a circuit diagram showing an example of a conventional output buffer circuit of this type. Referring to FIG. 3, this output buffer circuit is connected between a power terminal 1 and a ground terminal 2.
P-channel MOS field effect transistor (hereinafter PM
OS transistor hereinafter) referred to as P ₁ and N-channel MOS field effect transistor (hereafter NMOS transistor) N ₁ and is in series connected to each by a drain electrode in common.

The two MOS transistors have their gate electrodes connected in common, and this is the input terminal 3 of the output buffer circuit. The common drain electrode is the output terminal 4 of the output buffer circuit.

The above circuit configuration is the same as that of a CMOS inverter, but in an output buffer circuit,
To have a large driving ability to operate at a sufficiently fast load circuit connected to the output terminal 4, and in order to avoid being destroyed by static electricity, PMOS transistors P ₁ and NMOS transistor N ₁ is greater dimension It is common to keep.

[0005]

The above-described conventional output buffer circuit has a configuration in which _one PMOS transistor P ₁ and _one NMOS transistor N ₁ are combined and connected by an inverter. And these two MOs
The S transistor usually has a larger size than a MOS transistor used for an LSI logic circuit or the like. This is to prevent the output buffer circuit from being destroyed by static electricity and to have a sufficiently large driving capability. Therefore, when the conduction state of each MOS transistor switches and the potential level of the output signal changes, a large transient current flows instantaneously.

When this output buffer circuit is built in, for example, an LSI, the transient current is generated by the action of the inductance and resistance of the LSI package and the inductance and capacitance of the wiring inside the LSI. Inducing voltage on wiring and ground wiring,
Noise which causes malfunctions and deterioration of characteristics.

Since the magnitude of the generated noise is proportional to the magnitude of the transient current, that is, the dimensions of the PMOS transistor P ₁ and the NMOS transistor N ₁ constituting the output buffer circuit, in order to reduce the influence of the noise,
It is necessary to keep the dimensions of the PMOS transistor P ₁ and the NMOS transistor N ₁ constituting the output buffer small.

However, the PMOS transistors P ₁ and NM
In a conventional output buffer circuit in which _one OS transistor N1 is combined with each of the OS transistors N1 and connected by an inverter, in order to achieve the driving capability, the dimensions of the two MOS transistors forming the output buffer circuit must be reduced. As a result, it is very difficult to reduce the above-described switching noise.

[0009]

According to an output buffer circuit of the present invention, a first P-channel MOS field-effect transistor and a first N-channel MOS field-effect transistor are connected in series between a power supply terminal and a ground terminal. A CMOS inverter in which an external input signal is input to a common gate electrode, and a first P-channel M
A second P-channel MOS field-effect transistor connected in parallel to the OS field-effect transistor; a second N-channel MOS field-effect transistor connected in parallel to the first N-channel MOS field-effect transistor; , An output noise detection circuit for controlling the conduction state of the second P-channel MOS field effect transistor, and a second N-channel M
A ground noise detection circuit that controls a conduction state of the OS field-effect transistor. The power supply noise detection circuit receives the potential of the power supply terminal of the output buffer and an external input signal as inputs, and When the potential drops, this potential drop is detected, and the second P-channel MOS field-effect transistor operates so as to be in a cut-off state during the potential drop. The ground noise detecting circuit operates the ground terminal of the output buffer. The potential and the above-mentioned external input signal are input, and when the potential of the ground terminal rises, this potential rise is detected, and the second N-channel MOS field effect transistor is turned off during this potential rise. It operates as follows.

[0010]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram of an output buffer circuit according to one embodiment of the present invention.

Referring to FIG. 1, this embodiment includes an output buffer 5, a timing control circuit 6, a power supply noise detection circuit 7,
And a ground noise detection circuit 8.

The output buffer 5 is an inverter having a CMOS transistor configuration, but unlike the conventional output buffer circuit shown in FIG. 3, the PMOS transistors P ₁ and P ₂
Are connected in parallel, the NMOS transistors N ₁ and N ₂ are connected in parallel, and the two parallel circuits are connected in series between the output power terminal 1 a and the output ground terminal 2 a. . The common drain electrode of the four MOS transistors is the output terminal 4 of the present embodiment. The gate electrodes of the PMOS transistor P ₁ and the NMOS transistor N ₁ are commonly connected, and this is the signal input terminal of the output buffer 5. An input signal IN from the outside is input to this signal input terminal via the timing control circuit 6.

In this embodiment, the output power supply terminal 1a and the output ground terminal 2a are dedicated to the output buffer 5, and other circuits (the timing control circuit 6,
The power supply line and the ground line of the power supply noise detection circuit 7 and the ground noise detection circuit 8) are connected to a different system from the output power supply terminal 1a and the output ground terminal 2a.

The timing control circuit 6 includes an output buffer 5
A signal IN ₂ is input to a power supply noise control signal C _V output from the power source noise detection circuit 7, ground noise control signal C _G output from the ground noise detector circuit 8
In order to ensure that the operation of the entire output buffer circuit is performed more reliably. This circuit has a configuration in which two inverters 9 and 10 are connected in cascade.

The power supply noise detection circuit 7 includes an output buffer 5
A controls the conduction state of the PMOS transistor P _2, and when the potential of the output power supply terminal 1a is lowered, detects this, temporarily PMOS transistor P
₂ is controlled to be in the cutoff state. This circuit comprises an inverter 11, a two-input NOR circuit 12, and an inverter 13
Are connected in cascade, and the inverter 11
Is supplied with the potential of the output power supply terminal 1a. The two-input NOR circuit 12 receives an output of the inverter 11 and an external input signal IN as inputs. And this NOR
Is input to the gate electrode of the PMOS transistor P ₂ output circuit 12 via the inverter 13.

The inverter 11 is set so as to output a high level when the input level is about 94 to 95% of the power supply voltage. Such a setting is performed by the PMOS transistor and NMO constituting inverter 11.
It can be easily realized by appropriately designing the dimensions of the channel portion of the S transistor.

The ground noise detection circuit 8 controls the conduction state of the NMOS transistor N ₂ of the output buffer 5. When the potential of the output ground terminal 2 a rises, the ground noise detection circuit 8 detects this and temporarily stops the rise. NMOS transistor N ₂ is controlled to be in cut-off state. This circuit has a configuration in which an inverter 14, a two-input NAND circuit 15 and an inverter 16 are connected in cascade, and the potential of the output ground terminal 2a is input to the inverter 14. The two-input NAND circuit 15 includes the inverter 1
4 and an input signal IN are input. And
The output of the NAND circuit 15 is supplied to the N
It is input to the gate electrode of the MOS transistor N _2.

The inverter 14 is set to output a low level at an input level of about 5 to 6% of the power supply voltage.

The circuit operation of this embodiment will be described below with reference to FIG. FIG. 2 is a timing chart showing the waveform of each signal in the present embodiment shown in FIG. In FIG. 2, first, the potential of the input signal IN is at a high level, so that both the PMOS transistors P ₁ and P ₂ are in the cutoff state, while the NMOS transistors N ₁ and N ₂
Are both conductive and stable.

Here, when the potential of the input signal IN changes from a high level to a low level as shown in FIG.
Both MOS transistors P ₁ and P ₂ change from the cut-off state to the conductive state. On the other hand, the NMOS transistor N
₁ and N ₂ is changed to the blocking state from both conductive. Therefore, the potential of the output signal OUT output to the output terminal 4 changes from a low level to a high level. At this time,
From the output power supply terminal 1a to the output terminal 4, momentarily charging current flows through the PMOS transistor P ₁ and P _2. As a result, a potential drop occurs at the output power supply terminal 1a. This is because the large transient charging current flows through the resistance and the inductance existing between the output power terminal 1a and the output terminal 4.

When a potential drop occurs at the output power supply terminal 1a as described above, the output potential of the inverter 11 which receives the potential drop changes from a low level to a high level. Therefore, in the two-input NOR circuit 12 having the output of the inverter 11 as one input, the output potential is equal to the input signal I
It goes low regardless of the level of N. As a result, the output of the inverter 13, that is, the power supply noise control signal C
The potential of _V changes from low level to high level, and PMO
Only S transistor P ₂ is changed to the blocking state again from the conductive state. For this reason, the charging current temporarily decreases, and the potential drop of the output power supply terminal 1a is reduced. Thereafter, when the potential of the output power supply terminal 1a becomes high level and stabilizes, the potential of the power supply noise control signal C _V changes from high level to low level again.
₂ changes from the cutoff state to the conduction state again.

Next, when the potential of the input signal IN changes from a low level to a high level as shown in FIG.
OS transistors P ₁ and P ₂ both change from the conductive state to the cut-off state. On the other hand, the NMOS transistor N ₁
And N ₂ both change from the blocking state to the conducting state.
Therefore, the potential of the output signal OUT output to the output terminal 4 changes from the high level to the low level. At this time, from the output terminal 4 to the output ground terminals 2a, instantaneously a discharge current flows through the NMOS transistor N ₁ and N _2. As a result, the potential of the output ground terminal 2a increases. This is because the large transient discharge current flows through the resistance and inductance existing between the output ground terminal 2a and the output terminal 4.

When the potential of the output ground terminal 2a rises as described above, the inverter 1 having the input as an input.
4 changes from the high level to the low level.
Therefore, the output potential of the two-input NAND circuit 15 having the output of the inverter 14 as one input is high regardless of the level of the input signal IN. As a result, the output of the inverter 16, i.e., the potential of the ground noise control signal C _G is changed from the high level to the low level, only the NMOS transistor N ₂ is changed to the blocking state again from the conductive state. Therefore, the discharge current temporarily decreases, and the rise in the potential of the output ground terminal 2a is moderated. Thereafter, when the potential of the output ground terminal 2a becomes low level and becomes stable, the ground noise control signal C
Since the potential of _G changes from the low level again to a high level, NMOS transistor N ₂ is conductive again from the cutoff state.

[0024]

As described above, according to the present invention,
The switching between the conduction state and the interruption state of the PMOS transistors connected in parallel is detected and controlled by the power supply noise detection circuit in response to the change in the power supply potential, and the conduction state and the interruption state of the NMOS transistors connected in parallel are controlled. The switching of the output buffer is detected and controlled by the ground noise detection circuit in response to the change in the ground potential, so that the driving capability of the output buffer is reduced only during the change in the power supply potential and the ground potential. The circuit can be prevented from malfunctioning. Moreover, since the output buffer circuit of the present invention does not require a special control signal from the outside, it is not necessary to take measures such as increasing the number of LSI terminals or pulling wires from other circuits.
This is a very great advantage as an output buffer circuit used for an LSI.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of one embodiment of the present invention.

FIG. 2 is a timing chart of each signal when the output buffer circuit shown in FIG. 1 operates.

FIG. 3 is a circuit diagram of a conventional output buffer circuit.

[Explanation of symbols]

 1, 1a power supply terminal 2, 2a ground terminal 3 input terminal 4 output terminal 5 output buffer 6 timing control circuit 7 power supply noise detection circuit 8 ground noise detection circuit 9, 10, 11, 13, 14, 16 inverter 12 NOR circuit 15 NAND circuit

Claims (1)

(57) [Claims] 1. A first P-channel MOS field-effect transistor and a first N-channel transistor between a power supply terminal and a ground terminal.
A CMOS inverter in which a channel MOS field-effect transistor is connected in series and an external input signal is inputted to a common gate electrode; and a CMOS inverter connected in parallel to the first P-channel MOS field-effect transistor. Two P-channel MOS field-effect transistors;
An output buffer having a second N-channel MOS field-effect transistor connected in parallel with the first N-channel MOS field-effect transistor; and controlling a conduction state of the second P-channel MOS field-effect transistor. And a ground noise detection circuit that controls a conduction state of the second N-channel MOS field-effect transistor, wherein the power supply noise detection circuit is configured to control a potential of a power supply terminal of the output buffer and the external circuit. When the potential of the power supply terminal drops, this potential drop is detected, and during the period of the potential drop, the second P-channel MOS
The field-effect transistor operates so as to be in a cutoff state, wherein the ground noise detection circuit receives the potential of the ground terminal of the output buffer and the input signal from the outside as inputs, and when the potential of the ground terminal rises An output buffer circuit operable to detect this potential rise and to shut off the second N-channel MOS field effect transistor during the potential rise.