JP3074906B2 - Semiconductor circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor circuit, and more particularly to a digital integrated circuit such as a microcomputer using a CMOS transfer gate.

[0002]

2. Description of the Related Art A digital integrated circuit such as a microcomputer has a pMOST 31 and an n
A transfer gate in which MOSTs 32 are connected in parallel is used. One of the source / drain regions of the pMOST 31 and the nMOST 32 is used as the input terminal 1, the other source / drain region is used as the output terminal 2, and the pMOST 3
1 gate electrode 11 and nMOST 32 gate electrode 12
Are applied with control signals having phases substantially opposite to each other. The normal control signal terminal 10 is connected to the gate electrode 1 of the nMOST 32.
2 and is connected to the gate electrode 11 of the pMOST 31 via the inverter 41.

This transfer gate is a gate electrode 11
Is low and the potential of the gate electrode 12 is high, the pMOST 31 and the nMOST 32 are both turned on to transmit the potential level of the input terminal 1 to the output terminal 2. When the potential of the gate electrode 11 is at a high level and the potential of the gate electrode 12 is at a low level, the pMOST 31 and nM
Since both the OSTs 32 are turned off, the potential level of the output terminal 2 is maintained regardless of the potential level of the input terminal 1. This will be described with reference to the signal waveform diagram of FIG.

The initial state (before time t1) is input terminal 1,
The potential of the gate electrode 12 and the output terminal 2 is set to a high level, and the potential of the gate electrode 11 is set to a low level. When the potential of the input terminal switches to low level at time t1, pMOST3
1. Since both the nMOST 32 are conducting, the potential of the output terminal 2 switches to a low level at time t2.
The time t2 depends on the current driving capability of the pMOST31 and the nMOST32 and the load capacitance of the output terminal 2. Next, at time t3, the potential of the gate electrode 11 is simultaneously switched to the high level and the potential of the gate electrode 12 is simultaneously switched to the low level, so that pMO
ST31 and nMOST32 are turned off. At this time, the potential of the output terminal 2 should keep the low level, but the switching of the potential of the gate electrode 11 causes the potential level of the output terminal 2 to rise.

Here, this phenomenon will be described. FIG. 6 is a sectional view of the MOST. Normally MOST is gate electrode 1
05 and the source / drain diffusion layers 102 and 103 overlap as shown. The length of this overlap is defined as gate-drain-overlap length Δ.

Here, boron is used as the impurity in the source / drain diffusion layers of the pMOST. Since boron has a larger diffusion coefficient than the arsenic impurity in the source / drain diffusion layers of the nMOST, it is apparent that the gate-drain overlap length Δ of the pMOST becomes larger than that of the nMOST. In fact, pMOST has a gate-drain overlap length that is about twice that of nMOST.

[0007] In general, the design is about twice as large as that of pMOST. Gate-drain capacitance of pMOST From this 21 gate-drain of nMOST
Since the potential of the gate electrode 11 is about four times larger than the inter-in capacitance 22, the switching of the potential of the gate electrode 11 from a low level to a high level increases the potential level of the output terminal 2. This level rise depends on the ratio between the load capacitance of the output terminal 2 and the gate-drain capacitance.

As the switching time per gate stage is faster, that is, as a transistor having a higher current driving capability is used, the amplitude of noise generated in the GND wiring increases and the noise margin becomes tighter. In recent years, the voltage has been reduced, and the noise margin has been decreasing. For these reasons, coupling due to the gate-source capacitance of the transfer gate, which has not been a problem in the past, has recently become a problem.

[0009]

In the operation of the conventional transfer gate, when the potential of the input terminal 1 and the output terminal 2 is low, the potential of the gate electrodes 11 and 12 is changed to switch the transfer gate to a non-conductive state. If switching is performed at the same time, the potential level of the output terminal 2 rises due to the gate-drain capacitance of the pMOST 31, and a low level of the potential of the output terminal 2 cannot be maintained, causing a malfunction.

[0010]

SUMMARY OF THE INVENTION The present invention provides a first pMO
ST, a second pMOST, a second nMOST, and a first nMOST are connected in series in this order, and the first pMOST
T and the gate electrode of the first nMOST are connected to the input terminal, the drains of the second pMOST and the second nMOST are connected to the output terminal, and the first control signal is connected to the gate electrode of the second pMOST. The second pMOST controls the conduction / non-conduction of the second pMOST by inputting the second pMOST, and outputs the second control signal delayed by a predetermined time from the first control signal to the second nM
By inputting to the gate electrode of the OST, the second nM
Equipped with an inverter circuit that controls conduction / non-conduction of OST
The inverter circuit inputs the first control signal.
Invert the barter through at least three stages and
It is a circuit that serves as a control signal.

[0011]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram of a transfer gate according to a technology related to the present invention , and FIG. 2 is a signal waveform diagram used for explaining the operation thereof.

[0012] In FIG. 1, PMOST31 a controlled conduction / non-conduction by the first control signal, a CMOS gates with the nMOST32 controlled conduction / non-conduction by the second control signals in parallel A semiconductor circuit provided with means for changing the second control signal with a delay of a predetermined time from the first control signal. That is,
The first control signal is a signal applied to the control signal terminal 10, and the second control signal (signal applied to the gate electrode 12) is a signal applied to the control signal terminal 10 by the delay circuit 4 (inverter 4).
1, 42 and 43).

As an initial state, an input terminal 1 and a gate electrode 1
When the potential of the input terminal 1 is switched to the low level at time t1 when the potential of the output terminal 2 and the output terminal 2 are at the high level and the potential of the gate electrode 11 is the low level, the pMOSTs 31 and n
Since the MOST 32 is conducting, the potential of the output terminal 2 switches to the low level at time t2. Next, at time t
At 3, the potential of the gate electrode 11 is switched to a high level, and the pMOST 31 is turned off. At this time, pMO
The potential level of the output terminal 2 rises due to the gate-drain capacitance 21 of ST31. At this time, the potential of the output terminal 2 falls to a low level because the nMOST 32 is conducting. After the pMOST 31 is turned off, at time t
In step 4, the potential of the gate electrode 12 is switched to a low level, and the transfer gate is turned off. Then n
Although the low level of the output terminal 2 is further reduced by the gate-drain capacitance 22 of the MOST 32, there is no problem in the circuit operation. As described above, the potential of the output terminal 2 can be completely maintained at a low level, and malfunction due to the gate-drain capacitance 21 can be prevented.

Next, at time t5, the potential of the gate electrode 11 becomes low, at time t6, the potential of the gate electrode 12 becomes high,
When the potential of the input terminal 1 is switched to a high level at time t7, the pMOST 31 and the nMOST 32 are turned on, so that the potential of the output terminal 2 is switched to a high level at time t8. When the gate electrode 11 is switched to a high level at time t9 from this state, the potential of the output terminal 2 rises due to the gate-drain capacitance 21 of the pMOST, but there is no problem in circuit operation. Here, in the waveform diagram of FIG. 2, since the gate-drain capacitance 22 of the nMOST 32 is small, the level fluctuation of the potential of the output terminal 2 due to the gate-drain capacitance 22 is omitted.

FIG. 3 is a circuit diagram used for describing an embodiment of the present invention, and is an example in which the present invention is applied to a CMOS clock inverter.

Between the power supply terminal V _DD and the ground terminal GND, pM
The OSTs 31a and 31b and the nMOSTs 32a and 32b are connected in series and inserted, and the pMOST 31a and the nMOSTs 32a and 32b are inserted.
The gate of ST32b is connected to input terminal 1 and pMOST
31b to the control signal terminal 10 by the nMO
Inverters 41, 42 and 43 are inserted between the gate electrode of ST32b and the control signal terminal 10, and the pMOST 31b
And the output terminal 2 of the drain of the nMOST 32a.

In this embodiment, since the operation is the same as that of the transfer gate except that the inverted level of the potential level of the input terminal 1 is output to the output terminal 2, the waveform diagram is omitted.

In this embodiment, when the potential of the input terminal 1 is high and the potential of the control signal terminal 10 is low, the output terminal
The potential of the child 2 becomes low. At this time, the control signal terminal 1
When 0 is switched to a high level, the gate electrode 11
Switch to a high level, after which the gate electrode 12
Since the switching to the low level is performed, the low level holding state can be maintained without increasing the low level of the potential of the output terminal 2.

[0019]

As described above, the present invention provides a CMOS
PMO with large gate-drain capacitance at the gate
By setting ST to a non-conductive state first, and then to a non-conductive state of an nMOST having a small gate-drain capacitance, it is possible to suppress a rise in the potential of the output terminal when a low level is maintained, thereby preventing a malfunction of the semiconductor circuit. There is an effect that can be done.

[Brief description of the drawings]

FIG. 1 is a CM used to explain a technology related to the present invention.
FIG. 3 is a circuit diagram of an OS transfer gate.

FIG. 2 is a signal waveform diagram used for describing the operation of the circuit shown in FIG.

FIG. 3 is a circuit diagram of a CMOS clocked inverter used for explaining the embodiment of the present invention.

FIG. 4 is a circuit diagram of a CMOS transfer gate used for explaining a conventional technique.

FIG. 5 is a signal waveform diagram used for describing the operation of the circuit shown in FIG. 4;

FIG. 6 is a sectional view of a MOST.

[Explanation of symbols]

 Reference Signs List 1 input terminal 2 output terminal 11 gate electrode of pMOST 31 12 gate electrode of nMOST 32 21 gate-drain capacitance of pMOST 22 gate-drain capacitance of nMOST 32, 32a, 32b nMOST 4 delay circuit 41, 42, 43 inverter 101 one conductivity -Type silicon substrate 102, 103 Source / drain region 104 Gate oxide film 105 Gate electrode 106 Gate-drain capacitance L Gate length Δ Overlap capacitance

Claims (1)

(57) [Claims] A first pMOST, a second pMOST,
The second nMOST and the first nMOST are connected in series in this order, the gate electrodes of the first pMOST and the first nMOST are connected to an input terminal, and the second pMOST is connected to the input terminal.
And the drain of the second nMOST is connected to the output terminal,
The first control signal is input to the gate electrode of the second pMOST to control the conduction / non-conduction of the second pMOST, and the second control signal is delayed by a predetermined time from the first control signal.
The control signals have a inverter circuit for controlling conduction / non-conduction of the second nMOST by inputting to the gate electrode of the second nMOST, said inverter circuit,
Passing the first control signal through at least three inverters
A semiconductor circuit, which is a circuit which is inverted and used as the second control signal .