JPH05252015A - Semiconductor circuit - Google Patents

Abstract

PURPOSE:To prevent malfunction by making a pMOS transistor(TR) forming a CMOS gate nonconductive and then making an nMOSTR nonconductive resulting in causing the gate to be nonconductive. CONSTITUTION:A transfer gate consists of CMOS TRs being a pMOSTR31 and an nMOSTR32. The TRs 31, 32 are controlled respectively by a control signal from a control terminal 10 and a control signal via a delay circuit 4 to make the TR 31 whose gate-drain capacitance is large nonconductive and to make the TR 32 whose gate-drain capacitance is small nonconductive and then the transfer gate is made nonconductive. Thus, a level increase when a low potential level is kept for an output terminal is suppressed to prevent occurrence of malfunction.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor circuit, and more particularly to a digital integrated circuit such as a microcomputer using a CMOS transfer gate.

[0002]

2. Description of the Related Art In a digital integrated circuit such as a microcomputer, as shown in FIG.
A transfer gate in which MOSTs 32 are connected in parallel is used. One of the source / drain regions of pMOST31 and nMOST32 is used as an input terminal 1, the other source / drain region is used as an output terminal 2, and pMOST3
1 gate electrode 11 and nMOST 32 gate electrode 12
The control signals having substantially opposite phases to each other are applied to. The normal control signal terminal 10 is the gate electrode 1 of the nMOST 32.
2 is directly connected to the gate electrode 11 of the pMOST 31 via an inverter 41.

This transfer gate has a gate electrode 11
When the potential of the gate electrode 12 is low and the potential of the gate electrode 12 is high, both the pMOST 31 and the nMOST 32 become conductive, and the potential level of the input terminal 1 is transmitted to the output terminal 2. Further, when the potential of the gate electrode 11 is at a high level and the potential of the gate electrode 12 is at a low level, pMOST31 and nM
Since both OSTs 32 are in the non-conducting state, the potential level of the output terminal 2 continues to be held regardless of the potential level of the input terminal 1. This situation will be described with reference to the signal waveform diagram of FIG.

In the initial state (before time t1), the input terminal 1,
The potentials of the gate electrode 12 and the output terminal 2 are set to high level, and the potential of the gate electrode 11 is set to low level. When the potential of the input terminal switches to a low level at time t1, pMOST3
Since both 1 and nMOST 32 are conductive, the potential of the output terminal 2 switches to a low level at time t2.
This time t2 depends on the current driving capability of the pMOST31 and nMOST32 and the load capacitance of the output terminal 2. Next, at time t3, the potentials of the gate electrode 11 and the gate electrode 12 are simultaneously switched to the low level, and pMOST31 and nMO are switched.
ST32 is turned off. At this time, the potential of the output terminal 2 should continue to maintain a low level, but the gate electrode 1
The potential level of the output terminal 2 rises under the influence of the switching of the potential of 1.

Here, this phenomenon will be described. FIG. 6 is a sectional view of the MOST. Normally MOST is gate electrode 1
05 and the source / drain diffusion layers 102 and 103 overlap each other as shown in the drawing. The length of this overlap is defined as the gate / drain overlap length Δ.

Boron is used as the impurity in the source / drain diffusion layer of the pMOST. Since boron has a larger diffusion coefficient than arsenic, which is an impurity in the source / drain diffusion layer of the nMOST, it is clear that the gate / drain overlap length Δ of the pMOST is larger than that of the nMOST. In fact, pMOST has a gate-drain-overlap length that is about twice that of nMOST.

Further, it is generally designed to be about twice as large as that of pMOST. As a result, the gate-drain capacitance 21 of the pMOST is about four times larger than that 22 of the nMOST, so that the potential of the gate electrode 11 is switched from the low level to the high level to output the output terminal 2
The potential level of will rise. This rise in level depends on the ratio of the load capacitance of the output terminal 2 to the gate-drain capacitance.

A product having a faster switching time per one stage of a gate, that is, a transistor having a larger current driving capability is used, the amplitude of noise generated in the GND wiring becomes larger and the noise margin becomes more severe. Further, in recent years, as the voltage has been lowered, the noise margin tends to decrease. For these reasons, the coupling due to the gate-source capacitance of the transfer gate, which has not been a problem in the past, has become a problem in recent years.

[0009]

In the operation of this conventional transfer gate, when the potentials of the input terminal 1 and the output terminal 2 are at a low level, the potentials of the gate electrodes 11 and 12 are switched in order to switch the transfer gate to the non-conducting state. Simultaneous switching raises the potential level of the output terminal 2 due to the gate-drain capacitance of the pMOST 31, which makes it impossible to maintain the low level of the potential of the output terminal 2 and causes a malfunction.

[0010]

The present invention includes a gate including a pMOST whose conduction / non-conduction is controlled by a first control signal and an nMOST whose conduction / non-conduction is controlled by a second control signal. The semiconductor circuit comprises a means for changing the second control signal with a delay of a predetermined time from the first control signal.

[0011]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a circuit diagram of a transfer gate used to explain the first embodiment of the present invention, and FIG. 2 is a signal waveform diagram used to explain its operation.

This embodiment has a CMOS gate in which a pMOST 31 whose conduction / non-conduction is controlled by a first control signal and an nMOST 32 whose conduction / non-conduction is controlled by a second control signal are connected in parallel. The semiconductor circuit has means for changing the second control signal after a delay of a predetermined time from the first control signal. That is,
The first control signal is the signal applied to the control signal terminal 10, and the second control signal (the signal applied to the gate electrode 12) is the signal applied to the control signal terminal 10 in the delay circuit 4 (inverter 4).
1, 42 and 43 are connected in cascade).

As an initial state, the input terminal 1 and the gate electrode 1
2 and the potential of the output terminal 2 are at a high level and the potential of the gate electrode 11 is at a low level, when the potential of the input terminal 1 is switched to the low level at time t1, the pMOSTs 31 and n
Since the MOST 32 is conductive, the potential of the output terminal 2 switches to the low level at time t2. Then at time t
At 3, the potential of the gate electrode 11 is switched to a high level to make the pMOST 31 non-conductive. At this time pMO
The potential level of the output terminal 2 rises due to the gate-drain capacitance 21 of ST31, but at this time the nMOST 32 is in the conductive state, so that the potential of the output terminal 2 falls to a low level. After turning off pMOST31, time t
At 4, the potential of the gate electrode 12 is switched to a low level to make the transfer gate non-conductive. At this time n
Although the low level of the output terminal 2 is further lowered by the gate-drain capacitance 22 of the MOST 32, there is no problem in the circuit operation. In this way, the potential of the output terminal 2 can be kept at a completely low level, and malfunction due to the gate-drain capacitance 21 can be prevented.

Next, at time t5, the potential of the gate electrode 11 is low, and at time t6 the potential of the gate electrode 12 is high.
When the potential of the input terminal 1 is switched to the high level at the time t7, the pMOST31 and the nMOST32 are brought into the conductive state, and the potential of the output terminal 2 is switched to the high level at the time t8. When the electrode of the gate electrode 11 is switched to a high level at this time t9 from this state, the potential of the output terminal 2 rises due to the gate-drain capacitance 21 of the pMOST, but there is no problem in the circuit operation. Here, in the waveform diagram of FIG. 2, since the gate-drain capacitance 22 of the nMOST 32 is small, the level fluctuation of the potential of the output terminal 2 due to the gate-drain capacitance 22 is omitted.

FIG. 3 is a circuit diagram used to explain the second embodiment of the present invention, which is an example in which the present invention is applied to a CMOS clock inverter.

Between the power supply terminal V _DD and the ground terminal GND, pM
The OSTs 31a and 31b and the nMOSTs 32a and 32b are connected in series and inserted, and the pMOSTs 31a and nMOS are inserted.
The gate of ST32b is connected to the input terminal 1, and the pMOST
The gate electrode 11 of 31b to the control signal terminal 10
Inverters 41, 42, 43 are inserted between the gate electrode of ST32b and the control signal terminal 10, and pMOST31b
And the output terminal 2 of the drain of the nMOST 32a.

In this embodiment, the waveform diagram is omitted because it is the same as the operation of the transfer gate except that the inverted level of the potential level of the input terminal 1 is output to the output terminal 2.

In the case of this embodiment, the potentials of the input terminal 1 and the gate electrode 12 are at a high level, the gate electrode 11 and the output terminal 2 are high.
When the potential of the gate electrode 11 is low level, the potential of the gate electrode 11 is switched to the high level and then to the low level, so that the low level holding state can be maintained without increasing the low level of the potential of the output terminal 2. ..

[0019]

As described above, according to the present invention, the CMOS
PMO with large gate-drain capacitance at the gate
By making ST non-conducting first and then making nMOST with a small gate-drain capacitance non-conducting, it is possible to suppress the level rise when the potential of the output terminal is kept at a low level and prevent malfunction of the semiconductor circuit. There is an effect that can be.

[Brief description of drawings]

FIG. 1 is a CMO used to describe a first embodiment of the present invention.
It is a circuit diagram of an S transfer gate.

FIG. 2 is a signal waveform diagram used for explaining the operation of the circuit shown in FIG.

FIG. 3 is a CMO used to describe a second embodiment of the present invention.
It is a circuit diagram of an S clocked inverter.

FIG. 4 is a circuit diagram of a CMOS transfer gate used for explaining a conventional technique.

5 is a signal waveform diagram used to describe an operation of the circuit shown in FIG.

FIG. 6 is a cross-sectional view of a MOST.

[Explanation of symbols]

 1 Input Terminal 2 Output Terminal 11 Gate Electrode of pMOST 31 12 Gate Electrode of nMOST 32 21 Gate-Drain Capacitance of pMOST 22 Gate-Drain Capacitance of nMOST 32, 32a, 32b nMOST 4 Delay Circuit 41, 42, 43 Inverter 101 One Conduction Type silicon substrate 102, 103 Source / drain region 104 Gate oxide film 105 Gate electrode 106 Gate-drain capacitance L Gate length Δ Overlap capacitance

Claims (2)

[Claims] 1. A semiconductor circuit comprising a gate including a pMOST whose conduction / non-conduction is controlled by a first control signal and an nMOST whose conduction / non-conduction is controlled by a second control signal. Second after a predetermined time from the control signal of
2. A semiconductor circuit having means for changing the control signal of. 2. The semiconductor circuit according to claim 1, wherein the first control signal is inverted through at least three stages through an inverter to generate a second control signal.