JP2800336B2 - Semiconductor analog switch - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an analog switch, and more particularly, to a semiconductor analog switch including a semiconductor transistor formed on a monolithic integrated circuit.

[Conventional technology]

Conventionally, switch circuits formed on a monolithic integrated circuit to control the conduction and non-conduction of analog signals have been implemented using complementary MOs so that the input voltage range of analog signal inputs can be widened.
For example, as shown in FIG. 5, an N-channel MOS transistor 4 and a P-channel MOS transistor 5 connected in parallel between analog signal input / output terminals IN / OUT1 and OUT / IN2 using an S (hereinafter referred to as CMOS) structure. And the conduction / non-conduction of the transfer gate is controlled by the control signal input CONT3. That is, the control signal CO
When a low logic level "L" is given to NT3, the gate terminal of the N-channel MOS transistor 4 is _{supplied with} the potential of the low logic level substantially the low power supply potential VSS through the inverters 8 and 9, and The gate terminal of the P-channel MOS transistor 5 is further supplied with a potential of a substantially high power supply potential V _DD , which is a high logic level, via an inverter 10.
When the signal level V _IN of the analog input signal is located between the high-side power supply potential V _DD and the low-side power supply voltage V _SS , both of the OS transistors 4 and 5 have the gate-source voltage V _GS of the P-channel MOS transistor 5 and The absolute value of each of the threshold voltages V _THP and V _{THN of the} N-channel MOS transistor 4 cannot be larger than the threshold voltage V _THP and V _THN, and the N-channel MOS transistor 4 is in a non-conductive state. On the other hand, the control signal CO
When the high logical level "H" is applied to NT3, the gate terminal of the N-channel MOS transistor 4 is supplied with the high power supply potential V _DD which is a high logical level, and the signal level V _{IN of the} analog input signal is substantially The conduction state is established in the range of V _IN <V _DD −V _THN , and the gate terminal of the P-channel MOS transistor 5 has a low logic level of the low-side power supply potential V
Given the potential of _SS , the signal level V of the analog input signal
_IN becomes conductive in the range of almost V _SS + V _THP <V _IN , and the analog I / O pin at that time
The ON resistance R _ON between 1 and 2 is a parallel connection of the ON resistance of each of the N-channel MOS transistor 4 and the P-channel MOS transistor as shown in FIG.

Incidentally, in the conventional example shown in FIG.
The substrate on which the S transistor 4 is formed has a low power supply potential V
_The substrate on which the P-channel MOS transistor 5 is formed is connected to the high-side power supply potential _VDD .

Further, in a conventional CMOS analog switch, in order to reduce its on-resistance, for example, μ
Since the CMOS analog switch called PD4066 has a structure in which a P-well is formed on an N-type substrate, as shown in FIG. Without connecting to potential V _SS
It is connected to a potential depending on the signal level of the analog input signal generated by the circuit constituted by the P-channel MOS transistor 16 and the N-channel MOS transistors 17 and 18.
Therefore, the dependence of the on-resistance of the N-channel MOS transistor 4 on the signal level of the analog input signal is improved, and the on-resistance is reduced as shown in FIG.

[Problems to be solved by the invention]

In the conventional semiconductor analog switch described above,
As shown in FIG. 6, what is originally desired to have a uniform resistance value between the analog signal input / output terminals 1 and 2 with respect to the signal level of the analog input signal, such as a mechanical switch, By using semiconductor transistors,
There is a drawback that it fluctuates greatly depending on the input signal level. This has a direct effect on the time constant of CR due to, for example, resistance and capacitance, and is often fatal to the entire circuit.

In the second conventional example shown in FIGS. 7 and 8, although the overall on-resistance value is reduced and the fluctuation width of the on-resistance with respect to the signal level of the analog input signal is reduced, the transfer gate The substrate of the N-channel MOS transistor 4 acting as
The analog switch must be separated from the transistor substrate and independently applied to a potential that depends on the signal level of the analog input signal, deviating from the normal structure, and further weakening against latch-up phenomena. However, there is a disadvantage that the required area to be used also increases. Further, in a P-type substrate and an N-well structure which are currently dominant in a CMOS structure, it is possible to fluctuate depending on the potential of the substrate and the signal level of an analog input signal as described above. It does not contribute much to the reduction of the on-resistance of the entire analog switch.

SUMMARY OF THE INVENTION It is an object of the present invention to provide an integrated analog switch in which the on-resistance has a reduced dependence on the signal level of the analog input signal.

[Means for solving the problem]

In the semiconductor analog switch according to the present invention, a plurality of transfer gates are connected in parallel, and when the analog switches are turned on, at least one of the plurality of transfer gates is turned on regardless of the signal level of the input analog signal. The remaining transfer gates are always in a conductive state within the range of possible input signals, and the other transfer gates are configured to have a control circuit capable of controlling conduction / non-conduction by the signal level of the input analog signal.

〔Example〕

Next, the present invention will be described in more detail with reference to the drawings.

FIG. 1 is a circuit diagram of a first embodiment of the present invention. The same parts as those in the conventional example are given the same numbers. A transfer gate constituted by an N-channel MOS transistor 4 whose substrate is connected to the lower power supply potential V _SS between the input / output terminals IN / OUT1 and OUT / IN2 of the analog signal, and the same N
A transfer gate constituted by a channel MOS transistor 6, a transfer gate constituted by a P-channel MOS transistor 5 and a transfer gate constituted by a P-channel MOS transistor 7, both of which have their substrates connected to a high power supply potential _VDD. Are connected in parallel. Of these transfer gates, the gate terminals of the N-channel MOS transistor 4 and the P-channel MOS transistor 5 pass signals passed through inverters 8, 9 and inverters 8, 9, 10, respectively, from the control signal CONT3 as in the conventional analog switch. The applied signals are respectively applied. On the other hand, the gate terminal of the N-channel MOS transistor 6 has two inputs having the output signal of the inverter 9 applied to the gate terminal of the N-channel MOS transistor 4 and the input signal of the analog signal input / output terminal IN / OUT1. The output signal of the AND circuit 11 is applied. Also, P-channel MO
The inverter 10 applied to the gate terminal of the P-channel MOS transistor 5 has a gate terminal of the S transistor 7.
And an output signal of a two-input OR circuit 12 having the input signal of the analog signal input / output IN / OUT1 as an input.

The semiconductor analog switch of the present invention having such a configuration operates as follows.

That is, as shown in the time chart of FIG. 2, when the control signal CONT3 is at the low logic level "L", the inverter 9, AND
And outputs a substantially low side power supply potential V _SS output are both a low logic level regardless of the signal level of the analog input signal of the circuit 11. In addition, the outputs of the inverter 10 and the OR circuit 12 both output a substantially high power supply potential V _DD which is a high logic level regardless of the signal level of the analog input signal. Therefore, the N-channel MOS transistors 4, 6 and the P-channel MOS transistors 5, 7 are all non-conductive. Next, when the control signal CONT3 goes to the high logic level "H", the inverters 9 and 10 are always at the high logic level and the low logic level, respectively, regardless of the signal level of the analog input signal, and the N-channel MOS transistor 4 and the P-channel MOS
The transistor 5 is turned on. N channel
The MOS transistor 6 is non-conductive when the signal level of the analog input signal is lower than the threshold level of the AND circuit 11, and is conductive when the signal level exceeds the threshold level. On the other hand, P-channel MOS transistor 7 is turned on when the signal level of the analog input signal is lower than the threshold level of OR circuit 12, and turned off when the signal level exceeds the threshold level.

When the above-described operation is performed, as can be understood from the graph of the on-resistance in FIG. 3, in the N-channel MOS transistors 4 and 6, when the on-resistance of the N-channel MOS transistors is low, the analog input signal is low. Indicates that only the N-channel MOS transistor 4 is conductive and the N-channel MOS transistors 4 and 6 are both conductive in the signal level range of the analog input signal whose on-resistance increases to some extent.
The on-resistances of the OS transistors 4 and 6 are connected in parallel, so that the overall on-resistance value can be reduced. Also, P-channel MO
In the low level analog input signal in which the on-resistance of the P-channel MOS transistor is large in the S-transistors 5 and 7, both the P-channel MOS transistors 5 and 7 are conducting, and the on-resistance of the two P-channel MOS transistors is low. The P-channel MOS transistor 7 becomes non-conductive in the signal level range of the analog input signal in which the on-resistance is reduced in parallel and the on-resistance of the P-channel MOS transistors 5 and 7 is reduced to some extent.

For this reason, the on-resistance between the analog signal input / output terminals IN / OUT1 and OUT / IN2 is as shown in FIG. 3, and there is no large variation in the signal level of the analog input signal.

Here, the threshold levels of the AND circuit 11 and the OR circuit 12 can be easily changed by adjusting the ratio of the channel width W to the channel length L of the MOS transistors constituting each circuit.

FIG. 4 is a circuit diagram of a second embodiment of the present invention. This embodiment shares the transfer gate section with the first embodiment described above, but comprises the inverters 8, 9, 10, the AND circuit 11, and the OR circuit 12 in the first embodiment shown in FIG. 5 shows another embodiment of the control circuit described.

That is, the gate terminals of the N-channel MOS transistor 4 and the P-channel MOS transistor 5 are applied with a signal passed through the inverters 8, 9 and a signal passed through the inverters 8, 9, 10 from the control signal CONT3, respectively, as in the conventional analog switch. Have been. The gate terminal is commonly connected to the output terminal of the inverter 8, the source terminal is connected to the P-channel MOS transistor 13 connected to the analog signal input / output terminal IN / OUT1, and the source terminal is connected to the lower power supply potential V _SS . A signal passed through the buffer circuit 15 from the common drain terminal of the series circuit with the connected N-channel MOS transistor 14 is applied to the gate terminal of the transfer gate constituted by the N-channel MOS transistor 6. Furthermore, P-channel MO
The common drain terminal of the S transistor 13 and the N-channel MOS transistor 14 is connected to an OR circuit 16 having one input as an output signal of the inverter 10, and the output of the OR circuit 16 is formed by a P-channel MOS transistor 7. It is connected to the gate terminal of the gate.

With such a configuration, when the control signal CONT3 is at a low logic level "L", the outputs of the inverter 9 and the buffer circuit 15 are at a low logic level regardless of the signal level of the analog input signal, and the inverter 10 and the OR circuit The output of 16 becomes a high logic level, and all transfer gates, that is, N-channel transistors 4, 6 and P-channel MOS transistor
5 and 7 become non-conductive. On the other hand, when the control signal CONT3 becomes the high logic level “H”, the output of the inverter 9 becomes high logic level regardless of the signal level of the analog input signal.
The output of 10 becomes a low logic level, and the N-channel MOS transistor 4 and the P-channel MOS transistor 5 become conductive. However, when the signal level of the analog input signal is at a low level, the output of the inverter 8 is at a low level, but the potential of the common drain terminal of the P-channel MOS transistor 13 and the N-channel MOS transistor 14 is also low. As for the output, the signal level of the analog input signal rises, and the level of the common drain
Until the threshold level is reached, the low logic level is output, and the N-channel MOS transistor 6 is off. In addition, the output of the OR circuit 16 has a low logic output in the range of the signal level of the analog input signal until the potential of the common drain terminal rises to the threshold level, and the P-channel MOS transistor is conductive.

The operation is performed as described above, and the overall on-resistance is substantially the same as that of FIG. 3 shown in the first embodiment.

[Effects of the Invention] As described above, the present invention relates to a semiconductor analog switch including a transfer gate and a control circuit for controlling conduction and non-conduction of the transfer gate, wherein a plurality of transfer gates are connected in parallel. When the analog switch is turned on, at least one of the plurality of transfer gates is always in a conductive state regardless of the signal level of the input analog signal, and the other transfer gates are connected to the input analog signal. The conduction / non-conduction can be controlled by the signal level of the analog switch, so that the fluctuation of the resistance value between the input and output of the analog switch with respect to the signal level of the analog input signal input to the semiconductor analog switch can be reduced. There is a huge effect that it becomes possible. Further, according to the method of the present invention, the latch-up phenomenon in the conventional CMOS structure as shown in FIG. 7, for example, is effective because a well of a special potential is not formed.

In the embodiments of the present invention, the semiconductor switch has been described as having a CMOS structure, but it is clear that the present invention is not limited to this. Also, the transfer gate whose conduction and non-conduction is controlled by the signal level of the analog input signal is provided with several types of signal level dependence of the analog input signal of the control circuit, and the variation can be further divided to reduce the fluctuation of the on-resistance. It is possible.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a first embodiment of a semiconductor analog switch according to the present invention, FIG. 2 is a time chart for explaining the operation of the first embodiment shown in FIG. 1, and FIG. FIG. 4 is a circuit diagram of a second embodiment of the semiconductor analog switch of the present invention, FIG. 5 is a circuit diagram of a semiconductor analog switch according to the first conventional example, and FIG. 6 is a characteristic diagram of the first conventional example shown in FIG. 5, FIG. 7 is a circuit diagram of a semiconductor analog switch according to a second conventional example, and FIG. 8 is a second conventional example shown in FIG. FIG. 1,2 ... analog signal input / output terminal, 3 ... control signal input terminal, 4,6,14,17,18 ... N-channel MOS transistor,
5,7,13,16 …… P-channel MOS transistor, 8,9,10 ……
Inverter, 11… AND circuit, 12,16… OR circuit, 15…
Buffer circuit.

Claims (1)

(57) [Claims] 1. An analog switch comprising a transfer gate of a semiconductor transistor and a control circuit for controlling conduction / non-conduction of the transfer gate, wherein the transfer gate has a plurality of transfer gates in parallel, and the control circuit When the analog switch is turned on, at least one of the plurality of transfer gates is always turned on regardless of the signal level of the input analog signal, and the other transfer gates are turned on / off depending on the signal level of the input analog signal. A semiconductor analog switch characterized in that non-conduction can be controlled.