KR20010040990A - Overvoltage-protected i/o buffer - Google Patents

Abstract

The present invention discloses a tristate I / O buffer (101) suitable for coordination with module 31 operating at a supply voltage higher than the supply voltage. The output 4 of the buffer 101 includes an overvoltage protection circuit 110 that prevents current leakage from the output 4 to the supply voltage line VDD of the buffer 101. The overvoltage protection circuit 110 includes a PMOS blocking transistor 120, a first PMOS control transistor 130, and a second NMOS control transistor 140. These two control transistors 130 and 140 are controlled by a control signal derived solely from the enable signal E.

Description

Overvoltage Protection I / O Buffers {OVERVOLTAGE-PROTECTED I / O BUFFER}

The present invention relates to an I / O buffer, and more particularly to a tristate I / O buffer, that is, a first state in which the output of the buffer has three states and the output is activated high. State, a second state in which the output is active, and a third state in which the output, also referred to as tristate, is inactive, and the output has a high impedance to the outside.

More specifically, the present invention relates to an I / O buffer configured according to the IC or component formation of the IC.

These logic buffers have generally been known and in the disabled state they generate logic high / low levels depending on the logic level received at the data input at their output. An important role of this buffer is to provide a logic output signal to the load while a preceding circuit providing the data signal is not loaded or is rarely loaded. Low or "0" hereafter corresponds to a first voltage level specified as Vss and generally referred to as "ground" and high or "1" to a higher voltage designated as V _DD and generally referred to as "supply voltage". Corresponds to 2 voltage levels.

In many cases, the output of the tristate buffer is connected to at least one input of at least one other logic circuit and to a bus to which one or more inputs of other logic circuits are connected. In such a bus system, the logic level of the bus is always determined by one of the connected logic circuits. The circuits connected by the appropriate control circuits have only one of them in the active high / low state, with the remaining circuits in their tristate whose outputs are consequently in a high impedance state for the bus. It is controlled in such a way that it is little or little affected by the high / low provided by the circuit.

Logic circuitry designs for a predetermined supply voltage. The typical value for this supply voltage is 5V, but recently circuits have been developed with lower supply voltages. Examples of such low standard supply voltages are 3.0V and 3.3V. These circuits have been especially developed for battery-powered systems such as, for example, laptops, because the supply voltage decreases as the supply voltage is lowered. Another reason for this trend for circuits with low voltages is the continuing trend toward miniaturization, which means a continual decrease in the dimensions of circuit components. When the supply voltages are the same, circuit components are exposed to unacceptably high field strengths.

In practice, however, the device may include several logic circuits designed for different supply voltages. The reason for this may be, for example, that a version for a low supply voltage has not yet been developed for a given circuit or the performance of a version for a high supply voltage is better. In practice, an I / O buffer may be connected to a bus that is also connected to a circuit that operates when it is above the supply voltage of the buffer. Caused by a circuit operating at such a higher supply voltage, the voltage level present at the output terminal of the I / O buffer is higher than its supply voltage level V _DD , resulting in the buffer being under its tristate condition and the logic of the bus A situation where the level is high may occur. Under such conditions, current will flow from the output terminal to the supply voltage terminal of the I / O buffer, which is undesirable. In addition, the voltage level of the supply voltage V _DD of the buffer may increase, which is also undesirable. The I / O buffer is therefore a protection circuit that can prevent such undesirable currents.

I / O buffers with such overvoltage protection are described in international patent application WO94 / 29961. The protection circuit comprises two PMOS transistors, one NMOS transistor and an inverter. The protection circuit is controlled by a control signal for the PMOS pull-up transistor and is subsequently derived from the data signal.

The control signal for the PMOS pull-up transistor is supplied by a logic unit in which the NAND gate is present in the circuit described in the above publication. In a known circuit, this logic unit serves to control the protection circuits, not the PMOS pull-up transistors, which must be able to supply relatively large currents and therefore must be relatively overproportioned. Also, the output of this logic unit is not the switching transients of the PMOS pull-up transistor, but the switching of that of the protection circuit, specifically the PMOS blocking transistor arranged in series with the PMOS pull-up transistor. It is excessive. In this known circuit, since the control signal for the PMOS pull-up transistor is obtained based on the enable signal and the data signal, the frequency of this data signal is typically much higher than the frequency of the enable signal. This means that practical limitations are placed on the frequency at which the logic unit can operate.

The fact that in a known circuit the protection circuit is controlled by a control signal derived from the data signal, the protection circuit switches relatively frequently from the on state to the off state, so that a relatively high power dissipation is achieved. It is accompanied by. This also means that known circuits react relatively slowly to state changes, suggesting a limitation in the frequency range.

In a known circuit, the gate of the PMOS blocking transistor is controlled through the second PMOS transistor. This second PMOS transistor has its gate connected to the internal supply voltage V _DD . When the voltage level at the output of this circuit increases but only slightly higher than the level of the internal supply voltage V _DD , the PMOS transistor is not blocked by leakage current but does not result in full conduction. There is a tendency to hold the blocking transistor. However, this is not entirely successful but as a result leakage current will also flow from the output to the internal supply V _DD through the blocking transistor and the pull-up transistor. Since these transistors are larger than the second PMOS transistor, this leakage current will also be greater than the leakage current through the second PMOS transistor. In the case of an all connected tristate buffer, this large leakage current must be supplied by the current active circuit. If the current active circuit cannot supply such a large leakage current, this state will prevent this level from being applied to the bus by the current active state. Even the voltage on the bus will remain below the sum of the internal supply voltage V _DD and the threshold for the blocking transistor, and consequently the leakage current will continue to be maintained.

It is an object of the present invention to obviate or at least mitigate the aforementioned disadvantages.

It is a primary object of the present invention to provide an overvoltage-protected I / O buffer with improved performance.

It is yet another object of the present invention to provide an I / O buffer having a smaller number of components.

Another important object of the present invention is to provide an I / O buffer having a protection circuit in a control circuit for a protection circuit derived exclusively from an enable signal.

These and other aspects, shapes, and advantages of the present invention will become apparent from the following detailed description of the preferred embodiments of the I / O buffer according to the present invention with reference to the drawings, wherein like or similar elements will refer to the same reference numerals. .

1 schematically illustrates the basic principle of an I / O buffer.

2 is a diagram schematically illustrating the structure of a PMOS transistor.

3 shows a circuit diagram of a preferred embodiment of an I / O buffer in accordance with the present invention.

1 illustrates the basic principle of an I / O buffer and denotes reference numeral 1 as a whole. The buffer 1 is a PMOS pull-up field-effect transistor 10 having a source 11, a drain 12, and a gate 13 and an NMOS having a source 21, a drain 22, and a gate 23. It consists of a pull-down field-effect transistor. The drain 12 of the PMOS pull-up transistor 10 and the drain 22 of the NMOS pull-down transistor 20 are connected to an output terminal 4 that provides an output signal X with each other. Source 11 of PMOS pull-up transistor 10 is connected to supply voltage V _DD and source 21 of NMOS pull-down transistor 20 is connected to reference voltage level V _ss , which is hereafter referred to as zero level. do.

The PMOS pull-up transistor 10 and the NMOS pull-down transistor 20 are controlled by the control device 5 having two outputs 6, 7. The first output 6 of the control device 5 is connected to the gate 13 of the PMOS pull-up transistor 10 and the second output 7 of the control device 5 is the NMOS pull-down transistor 20. Is connected to the gate 23. The control device 5 has a first input 2 for receiving a data signal A, which can also be referred to as a data input. The control device 5 has a second input 3 which receives an enable signal E which is also referred to as an enable signal. The value of the enable signal determines whether the buffer operation mode is in an "active" or "tristate" state. Depending on the implementation, the active mode of the buffer 1 may be defined according to the value high of the enable signal E and the tristate mode of the buffer 1 may be defined according to the value low of the enable signal E, or else The method can be done.

When the input signal A is high, the control device 5 also generates a high signal at its two outputs 6, 7 in the active mode of the buffer 1. While the NMOS pull-down transistor 20 is shut off, it conducts the PMOS pull-up transistor 10 and as a result pulls up the voltage at the output terminal 4 to level V _DD .

When the input signal A is low, the control device 5 also generates a high signal at its two outputs 6, 7 in the active state of the buffer 1. While the main PMOS transistor is shut off, this conducts the NMOS pull-down transistor 2, which in turn pulls down the output voltage X at the output terminal 4 to V _ss .

In the tristate mode the control device 5 provides a high signal at its first output 6 and also a low signal at its second output 7 regardless of the value of the data signal A resulting in As a result, both pull-up transistor 10 and pull-down transistor 20 are turned on. The NMOS pull-down transistor 20 then forms a high impedance between the output 4 and the zero level V _ss while the PMOS pull-up transistor 10 has a high impedance between the output 4 and the supply voltage V _DD . To form. In this case, if the output 4 of the buffer 1 is connected to the bus 30, and also connected to the output of the second signal supply means 31 and the input of the signal processing means 32, the signal supply means 31 ) Can provide its output signal to the signal processing means 32 without any problem, without being interrupted by the connected buffer 1, which means that the output 4 has a high impedance with respect to the bus 30. This is because it does not load the output signal of the signal supply means 31 as a result.

If the signal supply means 31 operates at a supply voltage higher than the signal voltage V _DD at which the buffer 1 operates, it may occur that the voltage level of the bus 30 is higher than the supply voltage V _DD . If the voltage at the output 4 is higher than the supply voltage V _DD due to external causes, that is, the voltage at the drain 12 of the PMOS pull-up transistor 10 is higher than the voltage at the source 11 of this transistor. As a result, unnecessary leakage may occur from drain 12 to source 11 and from output 4 to V _DD as described herein.

In CMOS technology, PMOS transistors are usually manufactured in N-type wells. This is schematically illustrated functionally in FIG. 2, which is indicated by reference numeral 40 on the substrate as a whole. In the surface portion of the substrate 40, an N-type well 41 is formed. In the N-type well 41, two P + regions 42 and 43 are formed and connected to the source terminal 52 and the drain terminal 53, respectively. A gate electrode 54 is disposed between the source terminal 52 and the drain terminal 53 and defines a channel region 44 between the two P + regions 42 and 43 of the surface of the N-type well 41. do.

In addition, an N + region 45 is formed in the N-type well 41 and connected to the N-well electrode 55 and connected to the source electrode 52 by an electrical connection 56.

The surface of such a PMOS transistor is in principle symmetrical under the condition that the P + regions 42 and 43 are substantially identical, as a result of which the source and drain terminals of the circuit can be interchanged. As such, it has become common practice to refer to P + connected to only one in these two P + regions 42,43 and to N + type N-well terminal 45 as a source.

The transition between the P + region 42 and the N-well region 41 forms a parasitic POSITION junction 662, which will also be later referred to as parasitic source junction 62. will be. In a similar manner, the transition between P + region 43 and N-well region 41 forms parasitic drain X-ray 63.

If such a PMOS transistor has its own source terminal connected to V _DD , the entire region including the P + region 42, the N + region 45 and the N-well region 41 is at the voltage level V _DD . If the voltage at the drain terminal 53 is higher than V _DD , the parasitic drain junction 63 is biased in the forward direction. If the voltage at the drain terminal 53 and the voltage at the source terminal 52 are higher than the threshold of this parasitic drain X-ray 63, current will flow from the drain to the source and consequently in the embodiment of FIG. 30) to V _DD .

3 shows an embodiment of an I / O buffer 101 according to the invention, wherein this overvoltage protection circuit 110 is arranged between the PMOS pull-up transistor 10 and the output 4. This overvoltage protection circuit 110 includes a PMOS blocking field-effect transistor 120, a first field-effect transistor 130 of the PMOS type and a second field-effect control transistor of the NMOS type. It includes. PMOS blocking transistor 120 has its drain 122 connected to drain 12 of PMOS pull-up transistor 10 and its source 12 connected to output 4. The first (NMOS) control transistor 130 has its drain 132 connected to the gate 123 of the PMOS blocking transistor 120 and its source 131 connected to the output 4. The second (NMOS) control transistor 120 has its drain 142 connected to the gate 123 of the PMOS blocking transistor 120 and its source 141 connected to ground Vss. Each of the two control transistors 130 and 140 gates 133 and 134 receives an enable signal A.

3 also shows a circuit diagram of an embodiment of the control device 5. In the present embodiment, the control device 5 includes a NAND gate 151, an AND gate 152, and an inverter 153. NAND gate 151 receives a data signal and an enable signal E at its two respective inputs and its output forms a first output 6 of control device 5 and consequently a PMOS pull-up. It is connected to the gate 13 of the transistor 10. The AND gate 152 receives the enable signal E and the inverter 153 inverted data signal A at its two inputs, the output of which is the second output 7 of the control device 5. And as a result are connected to the gate 23 of the NMOS pull-down transistor 20.

In the active mode (E = high), when the data signal A is low, the level of the first output 6 of the control device 5 is high, and as a result, the PMOS pull-up transistor 10 is cut off. If the level of the second output 7 of the control device 5 is also high, as a result the NMOS pull-down transistor 20 is turned on. Output 4 goes low as a result.

In the active mode (E = high), when the data signal A is high, the level of the first output 6 of the control device 5 becomes low, and consequently, the PMOS pull-up transistor 10 is turned on. If the level of the second output 7 of the control device 5 is also low, as a result the NMOS pull-down transistor 20 is shut off. After that, when the gate 143 level of the second NMOS control transistor 140 is high, as a result, when the second NMOS control transistor 140 becomes conductive and the gate 123 of the PMOS blocking transistor 120 becomes low level, As a result, this PMOS blocking transistor 130 is also conductive. If the gate 133 level of the first PMOS control transistor 130 is high, this transistor is blocked as a result. The level at the output 4 is then high.

In the tristate mode (E = low), when the level of the first output 6 of the control device 5 is high, as a result, the PMOS pull-up transistor 10 is cut off and the second output of the control device 5 ( 7) If the level is low, then the NMOS pull-down transistor 20 is shut off. Thereafter, when the gate 143 level of the second NMOS control transistor 140 is low, the second NMOS control transistor is turned off as a result. If the gate 133 level of the first PMOS control transistor 130 is low, as a result the first PMOS control transistor 130 is turned on and if an external source increases the voltage at the output 4, the result is a blocking transistor. Since the gate 123 level of 120 is pulled up to its source 121 level, this blocking transistor 120 is cut off and the relatively high voltage level of the output 4 reaches the PMOS pull-up transistor 10.

The main advantage of the circuit envisioned by the invention is that only the gates 151 and 152 of the control device 5 must control the pull-up and pull-down transistors 10 and 20 and are loaded by the components of the high voltage protection circuit 110. Should not be.

Another major advantage of the circuit envisioned by the present invention is that the switching state of the overvoltage protection circuit 110 component is completely dependent on the state of the enable signal E and not on the data signal A, which is the case of the two control transistors 130 and 140. This is because the control voltages for the gates 133 and 143 are derived entirely from the enable signal E. Therefore, when the high / low output state changes with the high / low transition of the data signal A, the overvoltage protection circuit 110 of the buffer 101 does not have any component whose switching state must be switched in the active mode, As a result, the buffer 101 can respond relatively quickly to the switching of the data signal A and thus can handle a relatively high frequency.

Another main advantage of the present invention is that the gate 133 of the first PMOS control transistor 130 is held at a constant low level by the enable signal E in the Trestate mode, resulting in the first PMOS control transistor 130. ) Is already turned on even with a small voltage increase of the output 4, and if the voltage at the output 4 increases slightly, the gate 123 of the blocking transistor 120 is pulled up to the voltage level of the output 4 As a result, the blocking transistor 120 is already interrupted during the small voltage increase of the output 4. This is compared with a circuit known from WO94 / 29961, in which the blocking transistor in WO94 / 29961 is not blocked until the voltage level at the output is greater than the sum of V _DD and the threshold of the first control transistor.

Another major advantage of the circuit envisioned by the present invention is that the overvoltage protection circuit 110 has a small number of components and these components can be implemented particularly simply during the manufacture of the buffer 101 if there is no need for additional manufacturing steps. Can be.

It will be apparent to those skilled in the art that the scope of the invention is not limited to the embodiments described herein but that various alterations and modifications are possible without departing from the scope of the invention as defined in the appended claims. will be.

For example, it will be apparent to those skilled in the art that the login function of the control device 5 can be implemented in another way.

In addition, when the tristate mode is characterized by E = high and the active mode is characterized by E = low, the control device 5 may be driven by the use of an inverter and / or OR / NAND gate to achieve the above-described operation. It will be apparent to those skilled in the art that the present invention may be simply changed.

It will also be apparent to those skilled in the art that the present invention may be used in 3V / 5V or 3.3V / 5V environments and in other voltage level environments. The invention is also useful because the voltage of the supply line can be reduced more rapidly than the output voltage during the turn-off of the system.

It will also be apparent to those skilled in the art that if the data signal A and / or the enable signal E are too weak, these signals can be amplified by the buffer.

Claims (7)

A data input 2 for receiving a logic data signal A, an enable input 3 for receiving a logic enable signal E, a first control output 6 and a second control output ( A control device 5 having 7), Supply level line (V _DD ) and ground-level line (V _SS ), An output terminal 4, 1 field-effect transistor (a) having a control terminal (13) disposed between the output terminal (4) and the supply-level line (V _DD ) and connected to the first control output (6) of the control device (5). first field-effect transistor: 10), Second field-effect transistor having a control terminal 23 disposed between the output terminal 4 and the ground-level line V _SS and coupled to the second control output 7 of the control device 5. 20, Disposed between the first field-effect transistor 10 and the output terminal 4 A third field-effect transistor 120 disposed in series with the first field-effect transistor 10, A fourth field-effect transistor 140 having a control terminal 133 and connected between the control terminal 123 of the third field-effect transistor 120 and the output terminal 4, An overvoltage protection circuit 110 having a control terminal 143 and comprising a fifth field-effect transistor 140 coupled to the control terminal 123 of the third field-effect transistor 120. In a tristate buffer (101) comprising: When the enable signal E has a first value HIGH, the control device 5 turns on the first field-effect transistor 10 according to the value of the logic data signal A. turn on or turn on the second field-effect transistor 20 and turn off the first field-effect transistor 10 and the value of the logic enable signal E is the second value. (LOW: low), the control device 5 turns off the first field-effect transistor 10 and the second field-effect transistor 20, and the voltage level of the output 4 is When the ground level V _SS is higher than the sum of the thresholds of the fourth field-effect transistor 130, the first field-effect transistor 10 and the second field-effect transistor 20 are turned on. When off, the overvoltage protection circuit 110 turns on the fourth field-effect transistor 130. And characterized in that each of the control terminals 133, 143 of the fourth and fifth field-effect transistors 130, 140 is controlled by a control signal derived exclusively from the enable signal E. Tristate buffer The method of claim 1, The overload protection circuit 110 continuously conducts the fourth field-effect transistor 130 when the first field-effect transistor 10 and the second field-effect transistor 20 are disconnected. ) Buffer. The method according to claim 1 or 2, And the respective control terminals of the fourth field-effect transistor and the fifth field-effect transistor (130,140) are interconnected. The method according to any one of claims 1 to 3, A buffer in which the respective control terminals (133,143) of the fourth field-effect transistor and the fifth field-effect transistor (130,140) are controlled by the enable signal (E) itself. The method according to any one of claims 1 to 4, The fifth field-effect transistor (140) is coupled between the third field-effect transistor (120) and the ground-level line (V _SS ). The method according to any one of claims 1 to 6, The first field-effect transistor 10 has its source 11 coupled to the supply-level line V _DD and its gate coupled to the first output 6 of the control device 5. PMOS pull-up field-effect transistor having (13), The upper second field-effect transistor 20 has its source 21 coupled to the ground-level line V _SS , and has its drain 22 connected to the output 4, and An NMOS pull-down field-effect transistor having its gate 23 connected to the second output 7 of the control device 5, The third field-effect transistor 120 has its source 121 connected to the output 4 and is connected to the drain 12 of the PMOS pull-up field-effect transistor 10. PMOS blocking transistor having a drain of The fourth field-effect transistor 130 has its source 131 connected to the output 4 and its drain 142 connected to the gate 123 of the PMOS blocking transistor 120. Branch is the first PMOS control transistor, The fifth field-effect transistor 140 has its source 141 connected to the ground-level line V _SS and its drain connected to the gate 123 of the PMOS blocking transistor 120. A second NMOS control transistor having 142, And the gate (133) of the first PMOS control transistor (130) and the gate (143) of the second NMOS control transistor (140) respectively receive control signals derived from the enable signal (E). The method of claim 6, Said gate (133) of said first PMOS control transistor (130) and said gate of said second NMOS control transistor (140) are interconnected and receive said enable signal (E).