JPH11328953A - Semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the chip size and cost of a dynamic RAM of a hierarchial word line system also a negative word line system. SOLUTION: Unit subword line driving circuits USD0 to USDm, which are provided to correspond to subword lines SW0 to SW3, are provided between a corresponding main word line MW0 and a subword line SW0. An N channel second MOSFETNH, which receives reversed word line selection driving signals FX0B to FX3B, is provided between an N channel first MOSFETNG, which receives nonreversed word line selection driving signals FX0T to FX3T, and the supplying point of the negative potential VNN that becomes a subword line SW0 and its ultimate nonselected level. Then, the first MOSFETNG is turned on and the level of the main word line MW0 is temporarily set to the ground potential of the circuit. Having completed the above operations, it is set to the negative potential VNN which is the ultimate nonselected level of the subword line SW0.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, for example, to a dynamic RAM (random access memory) using a negative word line system and a technique particularly effective for stabilizing the operation and reducing the cost. Things.

[0002]

2. Description of the Related Art Information storage capacitor and address selection M
A memory array in which a dynamic memory cell composed of an OSFET (metal oxide semiconductor type field effect transistor; in this specification, a MOSFET is a generic name of an insulated gate type field effect transistor) is arranged in a lattice, is a basic component thereof. There is a dynamic RAM.
In such a dynamic RAM or the like, the memory array is divided in the direction in which the word lines extend, and the word lines are hierarchized into main word lines and sub-word lines to reduce the load capacity. There is a so-called hierarchical word line system that can be implemented. Further, by setting the non-selection level of the word line to a predetermined negative potential and completely turning off the address selection MOSFET of the dynamic memory cell, the leakage current of the memory cell is reduced, and the power consumption of the dynamic RAM and the like is reduced. There is a so-called negative word line system that can be achieved.

[0003]

Prior to the present invention, the present inventors engaged in the development of a dynamic RAM employing the above-described negative word line system, and noticed the following problems. That is, in this dynamic RAM, FIG.
As shown in FIG. 5, for example, the sub memory array SMA0
Of the sub-word line drive circuit SWD0 provided corresponding to the sub-word line SW0
0 is a CMOS (complementary MOS) type and the sub word line S
W0 and a non-inverted word line selection drive signal line FX0T (here, for a non-inverted signal or the like which is selectively set to a high level when it is set to an effective level, T
And is represented by P channel MOS whose gate is connected to main word line MW0B
FETPC, sub-word line SW0 and internal voltage VNN
An inverted word line selection drive signal line FX0B provided between the gates thereof (here, an inverted signal which is selectively set to a high level when it is set to an effective level, is suffixed with B at the end of its name). The same applies to the following.)
It is configured based on a channel MOSFET NR.

The MO of the unit sub-word line drive circuit USD0
As shown in FIG. 16, the SFETPC is selectively turned on when the main word line MW0B is set to the low level such as the internal voltage VNN, and the SFETPC is set to the high level corresponding to the power supply voltage VDD of the non-inverted word line selection drive signal FX0T. To the sub-word line SW0, which is set to the selected level. The MOSFET NC is selectively turned on when the inverted word line selection drive signal FX0B is set to a high level such as the internal voltage VDL, and the sub word line SW is turned on.
0 is a negative potential non-selection level such as the internal voltage VNN.

As is well known, a unit sub-word line driving circuit represented by USD0 is provided corresponding to each of the sub-word lines constituting sub-memory array SMA0. P-channel and N-channel MOSFETs
Circuit requires a region for well isolation, and a P-channel MOSFET PC
N itself has a small driving capability and has the same driving capability.
It requires a larger layout area than a channel MOSFET. As a result, the layout area required for the unit sub-word line drive circuit increases, and the chip size of the dynamic RAM increases, which hinders cost reduction.

On the other hand, in the dynamic RAM using the negative word line system, a negative potential, ie, an internal voltage VNN, which is a non-selection level of the sub-word line SW0 or the like, is externally supplied by an internal voltage generation circuit built in the dynamic RAM. Power supply voltage VDD and ground potential VSS
Is generated based on Therefore, for example, when the dynamic RAM includes a plurality of memory arrays and a plurality of word lines are simultaneously set to the selected level, the potential of the internal voltage VNN fluctuates when these word lines are simultaneously returned to the non-selected level. Then, the operation of the dynamic RAM becomes unstable.

In order to cope with this, in the dynamic RAM, the sub-word line SW0 is arranged in parallel with the MOSFET NR for setting the sub-word line SW0 to the non-selection level.
MOSFET NQ for lowering the level of W0 to ground potential VSS is provided. This MOSFETN
Q is turned on when the main word line MW0B is at an invalid level, that is, at a high level such as the power supply voltage VDD, and connects the sub-word line SW0 to be unselected to the ground potential supply point VSS having a relatively small impedance. I do. Then, when the level of the sub-word line SW0 substantially drops to the ground potential VSS, the MOSFET NR is turned on, and the level of the sub-word line SW0 is finally set to the non-selection level, that is, the internal voltage VNN.

As a result, the internal voltage VN which is generated by the internal voltage generation circuit built therein and has a relatively small supply capability.
The load on N can be reduced, the potential fluctuation can be suppressed, and the operation of the dynamic RAM can be stabilized.
Since the OSFET NQ is required, the layout required area is further increased, and the chip size of the dynamic RAM is further increased, which hinders cost reduction.

An object of the present invention is to provide a semiconductor memory device such as a dynamic RAM which can reduce the cost while stabilizing its operation.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0011]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, in a dynamic RAM or the like employing a hierarchical word line system and a negative word line system, a unit sub word line drive circuit of a sub word line drive circuit provided corresponding to a sub word line is constituted by only N-channel MOSFETs, for example, An N-channel first MOSFET provided between a main word line and a sub-word line and receiving a non-inverted word line selection drive signal corresponding to its gate, and a sub-word line and a negative potential supply at the final non-selection level A second MOSFET of an N-channel type which is provided between the first MOSFET and an inverted word line selection drive signal corresponding to the gate of the main word. After temporarily setting the line level to the circuit ground potential, The non-selection level serving negative potential.

According to the above-described means, the MOS for lowering the level of the sub-word line to the ground potential of the circuit first is used.
Without providing an FET for each unit sub-word line drive circuit, it is possible to reduce the load on a negative potential having a relatively small supply capacity, suppress the potential fluctuation, and to provide an N-channel MOSFET from each unit sub-word line drive circuit.
The layout area of the unit sub-word line drive circuit can be reduced by eliminating a P-channel MOSFET which is larger in size than T and requires a well isolation region. As a result, the chip size of the dynamic RAM or the like can be reduced while stabilizing the operation, and the cost can be reduced.

[0013]

FIG. 1 is a block diagram showing one embodiment of a dynamic RAM (semiconductor memory device) to which the present invention is applied. First, an outline of the configuration and operation of the dynamic RAM according to this embodiment will be described with reference to FIG. The circuit elements constituting each block in FIG. 1 are formed on a single semiconductor substrate surface such as single crystal silicon by a known MOSFET integrated circuit manufacturing technique. In addition, the dynamic RAM actually employs a so-called shared sense method, and uses a memory array MAR.
Y is paired with the sense amplifier SA interposed therebetween, and the memory array MARY and the peripheral circuits are also divided into a number of sub-memory arrays in the bit line extension direction. However, since this is not directly related to the gist of the present invention, It is shown in a simplified manner.

Referring to FIG. 1, a dynamic RAM according to this embodiment has a memory array MARY arranged so as to occupy most of the semiconductor substrate surface as a basic component. The dynamic RAM employs a hierarchical word line system, and the memory array MARY is divided into (k + 1) sub memory arrays SMA0 to SMAk in the word line extending direction. The memory array MARY further includes sub memory arrays SMA0 to SMA0.
It includes k + 1 sub-word line drive circuits SWD0 to SWDk provided corresponding to SMAk.

Each of sub memory arrays SMA0 to SMAk of memory array MARY has a predetermined number of sub word lines SW arranged in parallel in the vertical direction in the figure and a predetermined number of groups arranged in parallel in the horizontal direction in the figure. And complementary bit lines. At the intersection of these sub-word lines and complementary bit lines, an information storage capacitor and an address selection MOSFET
Are arranged in a lattice pattern. The specific configuration of the memory array MARY will be described later in detail.

Sub-words SW forming sub-memory arrays SMA0 to SMAk of memory array MARY are coupled to corresponding sub-word line drive circuits SWD0 to SWDk, and are selectively set to a selected level. The sub word line driving circuits SWD0 to SWDk are connected to the sub memory arrays SMA0 to SMA0.
It has a unit sub-word line driving circuit provided corresponding to each sub-word line SW of SMAk. To these unit sub-word line driving circuits, four main word line driving signals MW are sequentially supplied in common from the main word line driving circuit MWD via the corresponding main word lines MW, and a 4-bit word (not shown). A line selection drive signal is commonly supplied. Sub word line drive circuits SWD0-SW
The specific configuration of Dk will be described later in detail.

The main word line drive circuit MWD is supplied with a predetermined word main word line selection signal from the X address decoder XD. The X address decoder XD is supplied with i + 1-bit internal address signals X0 to Xi from the X address buffer XB and the internal control signal XG from the timing generation circuit TG. Further, the X address buffer AX receives an X address signal AX0 from an external access device through address input terminals A0 to Ai.
To AXi are supplied in a time-division manner, and an internal control signal XL is supplied from the timing generation circuit TG.

The X address buffer XB is provided with an X address signal AX supplied through address input terminals A0 to Ai.
0 to AXi are captured and held according to the internal control signal XL, and based on these X address signals, internal address signals X0 to Xi composed of non-inverted and inverted signals are formed and supplied to the X address decoder XD.

The X address decoder XD includes a main word line drive decoder and a word line selection drive decoder (not shown), as described later. Among them, the main word line drive decoder selectively operates in response to the high level of the internal control signal XG, and the X address buffer X
B, upper i of the internal address signals X0 to Xi supplied from B
One bit, that is, the internal address signals X2 to Xi are decoded, and a corresponding bit of a main word line selection signal (not shown) for the main word line drive circuit MWD is alternatively set to a low level selection level. Further, the word line selection drive decoder selectively operates in response to the high level of the internal control signal XG, and the internal address signals X0 to X0.
Lower two bits of Xi, that is, internal address signals X0 and X
1 is decoded, and a corresponding bit of a word line selection signal (not shown) for the main word line drive circuit MWD is alternatively set to a low level selection level.

On the other hand, the main word line drive circuit MWD
Based on a main word line selection signal supplied from a main word line drive decoder of X address decoder XD, a corresponding main word line of memory array MARY, that is, a corresponding bit of main word line drive signal MW is alternatively selected. In addition to the high-level selection level, the corresponding bit of the word line selection drive signal consisting of the non-inversion and inversion signals is selected based on the word line selection signal supplied from the word line selection drive decoder of the X address decoder XD. The state where the non-inverted signal is at a high level and the inverted signal is at a low level is referred to as logic "1", and the opposite state is referred to as logic "0". ). Further, the sub-word line driving circuits SWD0 to SWD
k is a combination of the main word line drive signal MWB and the word line selection drive signal supplied from the main word line drive circuit MWD, and the corresponding sub memory arrays SMA0 to SMA0.
The SMAk sub-word line SW is alternatively set to a predetermined selection level.

In this embodiment, a dynamic RA
M takes a negative word line system, and the non-selection level of the sub-word lines SW forming the sub-memory arrays SMA0 to SMAk is the second potential, that is, the negative internal voltage VNN such as -0.9 V (volt). The selection level is the first potential, that is, the power supply voltage VDD of a positive potential such as +3.3 V, for example. Further, in this embodiment, each of the unit sub-word line driving circuits SWD0 to SWDk provided corresponding to the sub-word line SW is constituted by an N-channel MOSFET, and the main word line at the selected level is set. The level of MW is first temporarily set to the circuit ground potential, that is, the ground potential VSS for a predetermined period, and then the internal voltage VN
N. This makes it possible to reduce the chip size of the dynamic RAM and reduce its cost while stabilizing its operation. The specific configuration of the sub-word line drive circuits SWD0 to SWDk and the selection and non-selection levels of the main word line MW and the sub-word line SW will be described later in detail.

Next, the complementary bit lines constituting the sub memory arrays SMA0 to SMAk of the memory array MARY are:
While being coupled to the sense amplifier SA, the complementary common data lines CD0 * to CDj * (here, for example, the non-inverted common data line CD0T and the inverted common data line CD0B, In addition, it is indicated by adding * like complementary common data line CD0 *.
The same applies hereinafter), that is, connected to the data input / output circuit IO.

To the sense amplifier SA, a bit line selection signal of a predetermined bit (not shown) is supplied from a Y address decoder YD, and an internal control signal PA is supplied from a timing generation circuit TG. The Y address decoder YD is supplied with i + 1-bit internal address signals Y0 to Yi from the Y address buffer YB and an internal control signal YG from the timing generation circuit TG. Furthermore, Y address signals AY0 to AYi are supplied to the Y address buffer YB in a time division manner from an external access device via address input terminals A0 to Ai, and an internal control signal YL is supplied from a timing generation circuit TG. . In addition,
Although the sense amplifier SA and the Y address decoder YD are actually divided corresponding to the sub memory arrays SMA0 to SMAk, they are integrally shown because they are not directly related to the gist of the present invention.

The Y address buffer YB is provided with a Y address signal AY supplied via address input terminals A0 to Ai.
0 to AYi are captured and held in accordance with the internal control signal YL, and based on these Y address signals, internal address signals Y0 to Yi composed of non-inverted and inverted signals are formed and supplied to the Y address decoder YD. Also, Y
Address decoder YD is selectively turned on in response to the high level of internal control signal YG, decodes internal address signals Y0-Yi supplied from Y address buffer YB, and supplies a bit line selection signal to sense amplifier SA. Is alternatively set to a high-level selection level.

The sense amplifier SA is connected to the memory array MAR
Y, that is, a predetermined number of unit circuits provided corresponding to the respective complementary bit lines of the sub memory arrays SMA0 to SMAk, each of which includes a unit amplifier circuit, a bit line precharge circuit, and a switch MOSFET.
including. Of these, the unit amplifier circuit of each unit circuit is selectively and simultaneously operated by the dynamic RAM being selected and the internal control signal PA being set to the high level, and the memory array MARY, that is, the sub memory array The small read signals output from the predetermined number of memory cells coupled to the selected sub-word lines of SMA0 to SMAk via the corresponding complementary bit lines are respectively amplified to produce high-level or low-level binary read signals.

On the other hand, the bit line precharge circuit of each unit circuit of the sense amplifier SA selectively and simultaneously operates in response to the high level of an internal control signal PC (not shown), and operates in the memory array MARY, that is, the sub memory array SMA0. SMAk to non-inverted and inverted signal lines of the corresponding complementary bit lines are respectively precharged to a predetermined intermediate potential. Further, the switch MOSFETs of each unit circuit are selectively turned on by j + 1 sets in response to the high level of the corresponding bit of the bit line selection signal, and the memory array M
ARY, that is, the corresponding j + 1 pairs of complementary bit lines and complementary common data lines CD of the sub memory arrays SMA0 to SMAk.
0 * to CDj *, that is, selectively connected to the data input / output circuit IO.

The complementary common data lines CD0 * to CDj * are
The data input / output circuit IO is coupled to a corresponding unit circuit. The data input / output circuit IO includes a timing generation circuit T
G supplies internal control signals WP and OC (not shown).

The data input / output circuit IO includes j + 1 unit circuits provided corresponding to the complementary common data lines CD0 * to CDj *. Each of these unit circuits includes a write amplifier, a main amplifier, and a data input buffer. And a data output buffer. Among these, the internal control signal WP is commonly supplied to the write amplifier of each unit circuit, and the internal control signal OC is commonly supplied to the data output buffer.

When the dynamic RAM is selected in the write mode, the data input buffers of each unit circuit of the data input / output circuit IO have data input terminals D0-D.
The write data of j + 1 bits supplied via j is taken in and transmitted to the corresponding write amplifier. At this time, the write amplifier of each unit circuit selectively and simultaneously operates in response to the high level of the internal control signal WP, and writes write data transmitted from the corresponding data input buffer with a predetermined complementary write signal. After doing
The selected j + 1 of the memory array MARY from the complementary common data lines CD0 * to CDj * via the sense amplifier SA
Write to memory cells.

On the other hand, when the dynamic RAM is selected in the read mode, the main amplifier of each unit circuit of the data input / output circuit IO receives the sense amplifier SA from the selected j + 1 memory cells of the memory array MARY.
And the binary read signal output via complementary common data lines CD0 * to CDj * is further amplified and transmitted to the corresponding data output buffer. At this time, the data output buffer of each unit circuit selectively and simultaneously operates in response to the high level of the internal control signal OC, and outputs j + 1-bit read data transmitted from the corresponding main amplifier to the data input / output terminal. Output to an external access device via D0 to Dj.

The timing generating circuit TG includes a clock signal CLK and a clock enable signal CKE supplied from an external access device, a row address strobe signal RASB, a column address strobe signal CASB, and a write enable signal WEB supplied as an activation control signal. Based on the above, the various internal control signals are selectively formed and supplied to each section of the dynamic RAM.
As a result, the dynamic RAM of this embodiment operates synchronously in accordance with the clock signal CLK, and its operation mode is the row address strobe signal R, which is a start control signal.
It is selectively designated according to a combination of the logic levels of ASB, column address strobe signal CASB and write enable signal WEB.

In this embodiment, the dynamic RA
M is supplied with a power supply voltage VDD and a ground potential VSS, which are operation power supplies thereof, via external terminals VDD and VSS. Further, as described above, the dynamic RAM employs the negative word line system, and the non-selection level of the sub-word line SW constituting the sub-memory arrays SMA0 to SMAk of the memory array MARY is a negative potential such as -0.9V. In addition to the internal voltage VNN, the operating power supply for the peripheral circuits is the internal voltage VDL having a relatively small absolute value, for example, + 1.8V. For this reason, the dynamic RAM uses the power supply voltage V
Internal voltages VDL and V based on DD and ground potential VSS
An internal voltage generation circuit VG for generating NN is provided.

FIG. 2 is a block diagram showing a first embodiment of the main word line drive circuit MWD included in the dynamic RAM of FIG. The configuration and operation of the main word line drive circuit MWD included in the dynamic RAM of this embodiment will be described with reference to FIG.
FIG. 2 also shows a block configuration of the X address decoder XD included in the dynamic RAM of this embodiment.

In FIG. 2, the main word line driving circuit M
WD is four unit word line selection drive circuits UF provided corresponding to word line selection drive signals FX0 * to FX3 *.
XD0 to UFXD3 and main word lines MW0 to MWp
, And p + 1 unit main word line drive circuits UMWD0 to UMWDm provided correspondingly. Among them, the unit word line selection drive circuits UFXD0 to UFXD3 include:
Word line selection drive decoder F of X address decoder XD
XSD corresponding word line selection signals FS0B to FS3
B is supplied to the unit main word line driving circuit UMWD0.
UMWDp include the main word line drive decoder M
The corresponding main word line select signal MS0B ~
MSpB is supplied. The word line selection drive decoder FXSD of the X address decoder XD receives lower-order 2-bit internal address signals X0 to X1 from the X address buffer XB.
Are supplied to the main word line drive decoder MWSD, and the internal address signals X2 to Xi of the upper i−1 bits are supplied. The word line selection drive decoder and the main word line drive decoder are further commonly supplied with an internal control signal XG from a timing generation circuit TG.

As described above, the word line selection driving decoder FXSD of the X address decoder XD outputs the internal control signal X
In response to the high level of G, the semiconductor memory device is selectively activated, decodes internal address signals X0 to X1, and outputs word line selection signals FS0B to FS0B to main word line drive circuit MWD.
The corresponding bit of FS3B is alternatively set to a low level selection level. Also, the main word line drive decoder MW
SD selectively operates in response to the high level of the internal control signal XG, decodes the internal address signals X2 to Xi supplied from the X address buffer XB, and selects the main word line drive circuit MWD for the main word line selection circuit MWD. The corresponding bits of the signals MS0B to MSpB are alternatively set to a low level selection level.

The word line selection drive decoder FXSD of the main word line drive circuit MWD is an X address decoder XD
Non-inverted word line selection signals FX0T to FX3 whose effective level is the power supply voltage VDD and whose invalid level is the internal voltage VNN, based on the word line selection signals FS0B to FS3B supplied from the word line selection drive decoder FXSD.
T and an inverted word line select signal FX whose effective level is an internal voltage VNN and whose invalid level is an internal voltage VDL.
0B to FX3B are selectively formed, and the memory array MA
It is supplied to the RY sub-word line drive circuits SWD0 to SWDk. Also, the main word line drive decoder MWSD is
Main word line selection signal MS0 supplied from main word line drive decoder MWSD of X address decoder XD
B to MSpB, the effective level of the power supply voltage VD
D, and the main word line drive signals MW0 to MWp whose final invalid level is the internal voltage VNN are selectively formed, and the sub word line drive circuits SWD0 to SWD of the memory array MARY via the main word lines MW0 to MWp.
k.

The unit main word line drive circuit UMW
D0 to UMWDp are the main word line drive signals MW0 to MWWDp.
Immediately before MWp is set to the invalid level of the internal voltage VNN, the potential is temporarily set to the ground potential VSS for a predetermined period. Including this, the unit word line selection driving circuits UFXD0 to UFXD
3 and the unit main word line drive circuits UMWD0 to UMWD0
The specific configuration and the like of the MWDm will be described later in detail.

FIG. 3 shows a unit word line selection drive circuit UFXD0 included in main word line drive circuit MWD of FIG.
FIG. 4 is a circuit diagram of one embodiment, and FIG. 4 is a signal waveform diagram of the embodiment. Based on these figures, the unit word line selection drive circuit UFX included in the main word line drive circuit MWD of the dynamic RAM according to this embodiment will be described.
The specific configuration and operation of D0 to UFXD3 will be described. In FIG. 3, all the unit word line selection driving circuits UFXD0 to UFXD0 are connected to the unit word line selection driving circuit UFXD0.
The UFXD3 will be described. In the following circuit diagram, a MOSFE in which an arrow is attached to a channel (back gate) portion thereof
T is a P-channel type, and is distinguished from an N-channel MOSFET without an arrow. In addition, the power supply voltage VDD and the internal voltage VDL, and the ground potential VSS and the internal voltage VNN written near each logic gate are:
The high-potential-side and low-potential-side operation power supplies of the respective logic gates are shown, respectively. However, a logic gate without such display uses the internal voltage VDL as its high-potential-side operation power supply and uses the ground potential VSS.
Is the low-potential-side operation power supply.

In FIG. 3, unit word line selection drive circuit UFXD0 includes one delay circuit DL1 and three level shift circuits LS1 to LS3. The delay circuit DL1 has one input terminal receiving a corresponding output signal of the word line selection drive decoder FXSD of the X address decoder XD, that is, the word line selection signal FS0B, and having the other input terminal having the inverters V1 and V2. Includes a NAND (NAND) gate NA1 receiving a delayed signal.
The output terminal of the NAND gate NA1, that is, the internal node n
The internal signal na at a is supplied to the gate of the P-channel MOSFET P6 constituting the level shift circuit LS3.

Here, the NAND gate NA1 and the inverters V1 and V2 constituting the delay circuit DL1 use the internal voltage VDL as its high-potential-side operation power supply and the ground potential VS
S is the low-potential-side operation power supply. Therefore, the output signals of these logic circuits both have internal voltage VDL at its high level and ground potential VSS at its low level. The word line selection signal FS supplied from the word line selection drive decoder FXSD of the X address decoder XD
4B, as shown in FIG. 4, the internal voltage VDL is normally set to an invalid level of a high level such as +1.8 V when the dynamic RAM is in a standby state. When the selected state is set in the active command cycle, the level is set to a low effective level such as the ground potential VSS at a predetermined timing, and then the dynamic RAM is set to the selected state in a precharge command cycle, for example. Such a high level is returned to the invalid level.

Needless to say, the output signal of the NAND gate NA1 constituting the delay circuit DL1, ie, the internal signal na
Is set to a low level such as the ground potential VSS when the word line selection signal FS0B and the delay signals due to the inverters V1 and V2 are both set to the high level, and the internal voltage V is set when any of these input signals is set to the low level.
It is set to a high level like DL. Therefore, when the word line selection signal FS0B changes from the high level to the low level, the internal signal na changes from the low level to the high level almost without delay, but the word line selection signal FS0B changes from the low level to the high level. When it is changed, it changes from a high level to a low level after being delayed by an amount corresponding to the delay time t1 of the inverters V1 and V2. The delay time t1 is used to set a time difference between the time when the non-inverted word line selection drive signal FX0T is set to the invalid level and the time when the inverted word line selection drive signal FX0B is set to the invalid level, as will be apparent from the following description. It will be.

Next, the level shift circuit LS1 includes an N-channel MOSFET N2 having a gate receiving the word line selection signal FS0B, a power supply voltage VDD and a MOSFET N.
A P-channel MOSFET P1 and an N-channel MOSFET N1 provided in series between the two gates. The source of MOSFET N2 is coupled to ground potential VSS and its drain is a P-channel MOSFET.
It is coupled to power supply voltage VDD via P2. Also, MO
The gate of SFET N1 is coupled to an internal voltage supply point VDL and the gate of MOSFET P1 is connected to the commonly coupled drain of MOSFETs P2 and N2, ie, internal node nb.
Is combined with The gate of MOSFET P2 is MOSF
Coupled to the commonly coupled sources of ETP1 and N1.

As shown in FIG. 4, when the word line selection signal FS0B, which is the output signal of the word line selection drive decoder FXSD of the X address decoder XD, is set to a high invalid level such as the internal voltage VDL, the unit word In the level shift circuit LS1 of the line selection drive circuit UFXD0, the MOSFET N2 is turned on and the internal node n
The internal signal nb at b is at a low level such as the ground potential VSS. At this time, the MOSFET P1 is turned on in response to the low level of the internal signal nb,
The gate potential of ETP2 is changed to power supply voltage VDD, that is, for example, +
High level such as 3.3V. For this reason, MOS
FETP2 is completely turned off, and MOSFETP2
And the leakage current through N2 is cut off.

On the other hand, when the word line selection signal FS0B is set to a low effective level such as the ground potential VSS, in the level shift circuit LS1, the MOSFET N2 is turned off, and the MOSFET P2 is turned on instead. Therefore, the potential of the internal signal nb is changed to the power supply voltage VD
As a result, the MOSFET P1 is turned off. As a result, the MOSFET P2 is completely turned on, and the potential of the internal signal nb is changed to the power supply voltage VDD.
Reach a high level like. As a result, the internal voltage V
As for the signal level of the word line selection signal FS0B in which DL is set to the high level and the ground potential VSS is set to the low level, only the high level is converted into the power supply voltage VDD by the level shift operation of the level shift circuit LS1. The internal signal nb, which is the output signal of the level shift circuit LS1,
P-channel MOS constituting level shift circuit LS2
It is supplied to the gate of FETP4.

The level shift circuit LS2 has a P-channel MOSFET P receiving the internal signal nb at its gate.
4 and a P-channel MOSFET P provided in series between the gate of MOSFET P4 and internal voltage VNN.
3 and an N-channel MOSFET N3. MOS
The source of FET P4 is coupled to power supply voltage VDD, and the drain is coupled to internal voltage VNN via N-channel MOSFET N4. The gate of the MOSFET P3 is coupled to the ground potential VSS, and the MOSFET N3
Is coupled to the commonly coupled drain of MOSFETs P4 and N4, ie, internal node nc. MOS
The gate of FET P4 is coupled to the commonly coupled sources of MOSFETs P3 and N3.

As shown in FIG. 4, when the internal signal nb, which is the output signal of the level shift circuit LS1, is at a low level such as the ground potential VSS, the level shift circuit LS
In 2, the MOSFET P4 is turned on, and the internal signal nc at the internal node nc is at a high level such as the power supply voltage VDD. At this time, the MOSFET N3 is turned on by receiving the high level of the internal signal nc, and
The gate potential of the SFET N4 is set to the internal voltage VNN, that is, a low level of a negative potential such as -0.9V. As a result, the MOSFET N4 is completely turned off, whereby the leakage current through the MOSFETs P4 and N4 is cut off.

On the other hand, when the internal signal nb is set to a high level such as the power supply voltage VDD, the MOSFET P4 is turned off in the level shift circuit LS2, and
SFETPN4 is turned on. Therefore, the potential of the internal signal nc decreases toward the internal voltage VNN, and in response, the MOSFET N3 is turned off. Therefore, MOSFET N4 is completely turned on, and the potential of internal signal nb reaches a low level like internal voltage VNN. As a result, the word line selection signal FS for setting the power supply voltage VDD to the high level and the ground potential VSS to the low level
As for the signal level of 0B, only its low level is the internal voltage VN due to the level shift operation of the level shift circuit LS2.
N.

The internal signal nc, which is the output signal of the level shift circuit LS2, passes through the inverter V3 using the power supply voltage VDD as its high-potential-side operation power supply and the internal voltage VNN as its low-potential-side operation power supply, and then selects the non-inverting word line. Drive signal FX
0T and the sub-word line SW of the memory array MARY
D0 to SWDk. Accordingly, the non-inverted word line selection drive signal FX0T is, as shown in FIG.
The internal voltage VNN, for example, -0.9 V is set to its low level, that is, an invalid level, the power supply voltage VDD, for example, +3.3 V, is set to its high level, that is, an effective level, and its rise and fall are determined by the word line selection signal F.
The signal has a relatively large amplitude without significantly delaying the fall and rise of S0B.

Next, the level shift circuit LS3 has a circuit configuration similar to that of the level shift circuit LS2, and has an internal signal na as an output signal of the delay circuit DL1 at its gate.
P-channel MOSFET P6 receiving the
It includes a P-channel MOSFET P5 and an N-channel MOSFET N5 provided in series between the gate of the FET P6 and the internal voltage VNN. The source of MOSFET P6 is coupled to internal voltage VDL and its drain is
Internal voltage VNN via N-channel MOSFET N6
Is combined with The gate of MOSFET P5 is coupled to ground potential VSS, and the gate of MOSFET N5 is
The MOSFETs P6 and N6 are coupled to a commonly coupled drain, that is, an internal node nd. The gate of MOSFET P6 is coupled to the commonly coupled sources of MOSFETs P5 and N5.

As shown in FIG. 4, when the internal signal na as the output signal of the delay circuit DL1 is at a low level such as the ground potential VSS, the level shift circuit LS3
MOSFET P6 is turned on, and internal signal nd at internal node nd is set to a high level like internal voltage VDL. At this time, the MOSFET N5 outputs the internal signal n
d is turned on in response to the high level of
The gate potential of N6 is set to the low level of the internal voltage VNN. Therefore, the MOSFET N6 is completely turned off, and the leakage current through the MOSFETs P6 and N6 is cut off.

On the other hand, when the internal signal na is set to a high level such as the internal voltage VDL, the MOSFET P6 is turned off in the level shift circuit LS3, and
The FET PN6 is turned on. Therefore, the internal signal nd
Falls toward the internal voltage VNN, whereby the MOSFET N5 is turned off. Therefore, M
OSFET N6 is completely turned on, and internal signal nd
Reaches a low level like the internal voltage VNN.
As a result, the signal level of the word line selection signal FS0B that sets the internal voltage VDL to the high level and sets the ground potential VSS to the low level is such that only the low level is converted to the internal voltage VNN by the level shift operation of the level shift circuit LS3. Become.

The internal signal nd, which is the output signal of the level shift circuit LS3, passes through two inverters V4 and V5, both using the power supply voltage VDD as its high-potential-side operation power supply and the internal voltage VNN as its low-potential-side operation power supply. , And the inverted word line selection drive signal FX0B becomes the memory array MARY.
Are supplied to the sub word lines SWD0 to SWDk. Therefore, as shown in FIG. 4, the inverted word line selection drive signal FX0B has the internal voltage VDL, for example, +1.8.
V is set to its high level, that is, invalid level, and the internal voltage V
NN, that is, for example, -0.9V is set to the low level, that is, the effective level, and the falling of the inverters V4 and V5 with respect to the falling of the word line selection signal FS0B.
Of the word line selection signal FS0B, the rising of which is delayed by an amount corresponding to the delay time t1 of the delay circuit DL1 and the delay time t42 of the inverters V4 and V5. The signal has a relatively large amplitude.

As described above, the memory array MARY of the dynamic RAM is divided into (k + 1) sub memory arrays SMA0 to SMAk, and the sub word line driving circuits SWD0 to SWD0 to
WDk is provided. Therefore, the word line selection drive signals FX0 * to FX3 * are actually formed individually corresponding to the sub memory arrays SMA0 to SMAk.

FIG. 5 shows a unit main word line driving circuit UMWD included in main word line driving circuit MWD of FIG.
0 is a circuit diagram of an embodiment, and FIG. 6 is a signal waveform diagram of the embodiment. Based on these figures,
The unit main word line drive circuit U included in the main word line drive circuit MWD of the dynamic RAM according to this embodiment
The specific configuration and operation of MWD0 to UMWDk will be described. In FIG. 3, all the unit main word line drive circuits UMWD0 to UMWDk will be described using the unit main word line drive circuit UMWD0.

In FIG. 5, the unit main word line drive circuit UMWD0 includes one delay circuit DL2 and two level shift circuits LS4 and LS5. this house,
The delay circuit DL2 has one input terminal receiving the output signal of the NAND gate NA2, that is, the internal signal ne, and the other input terminal having a main word line selection signal MS0B as an output signal of the main word line drive decoder MWSD of the X address decoder XD. , And a NAND gate NA3 for receiving a delay signal from the inverters V9 and VA. NAND gate N
One input terminal of A2 has a main word line selection signal M
S0B is supplied, and the other input terminal is supplied with an inverted delay signal by the inverters V6 to V8. The output signal of the NAND gate NA2, that is, the internal signal ne is supplied to one input terminal of the NAND gate NA3, and becomes an internal signal nh via the inverter VB.
It is supplied to the gate of OSFETNB. The output signal of the NAND gate NA3 is a P-channel MOSFET constituting the level shift circuit LS5 as an internal signal nf.
It is supplied to the gate of PA.

As shown in FIG. 6, the main word line select signal MS0B supplied from the main word line drive decoder MWSD of the X address decoder XD has the internal voltage VDL when the dynamic RAM is in the standby state. It is considered a high level invalid level like
For example, when the dynamic RAM is set to a selected state in an active command cycle, the dynamic RAM is set to a low-level effective level such as the ground potential VSS at a predetermined timing.
The dynamic RAM is returned to an invalid level such as the internal voltage VDL by being set to a selected state in a precharge command cycle, for example. Further, as described above, all the logic gates constituting delay circuit DL2 are connected to internal voltage V
Since DL is used as the high-potential-side operation power supply and ground potential VSS is used as the low-potential-side operation power supply, the output signal of each logic gate has its high level set to the internal voltage VDL and its low level set to the ground potential VSS.

Needless to say, the output signal of the NAND gate NA2 constituting the delay circuit DL2, ie, the internal signal ne
Is set to a low level such as the ground potential VSS when the main word line selection signal MS0B and the inversion delay signals by the inverters V6 to V8 are both set to the high level,
When any of these input signals is at a low level, it is at a high level such as the internal voltage VDL. Therefore, as shown in FIG. 6, internal signal ne is normally at a high level like internal voltage VDL, and when main word line select signal MS0B is returned from the low level to the high level, delay of inverters V6 to V8 is delayed. The pulse signal temporarily becomes a low level such as the ground potential VSS only during a period corresponding to the time t21.

On the other hand, the output signal of NAND gate NA3 constituting delay circuit DL2, that is, internal signal nf is the same as the output signal of NAND gate NA2, that is, internal signal ne, and the delayed signal of inverter V9 and VA of main word line select signal MS0B. And the ground potential VS
It is set to a low level like S, and when any of them is set to a low level, it is set to a high level like the internal voltage VDL. Therefore, internal signal nf is normally at ground potential VS
When the dynamic RAM is selected in the active command cycle, the internal voltage is delayed from the fall of the main word line selection signal MS0B by an amount corresponding to the delay time t22 of the inverters V9 and VA. High level like VDL,
When the dynamic RAM is set to the selected state in the precharge command cycle and returned to the standby state, it substantially corresponds to the pulse width of the internal signal ne from the rise of the main word line selection signal MS0B, ie, the delay time t21 of the inverters V6 to V8. It is a signal that is returned to a low level such as the ground potential VSS with a delay by an amount.

Next, the level shift circuit LS4 has the same circuit configuration as the level shift circuit LS1 of the unit word line selection drive circuit UFXD0. The level shift circuit LS4 sets the internal voltage VDL to its high level and sets the ground potential VSS to its low level. Only the high level of the word line selection signal MS0B is converted to the power supply voltage VDD. Also, the level shift circuit LS
Reference numeral 5 designates an output signal of the NAND gate NA3 of the delay circuit DL2 which has the same circuit configuration as the level shift circuit LS3 of the unit word line selection drive circuit UFXD0, sets the internal voltage VDL to its high level, and sets the ground potential VSS to its low level. Only the low level of the internal signal nf is converted to the internal voltage VNN.

The output signal of the level shift circuit LS4 uses the power supply voltage VDD as its high-potential-side operation power supply and the ground potential VS
After being inverted by an inverter VC which uses S as its lower-potential-side operation power supply, it is supplied as an internal signal ng to the gate of the P-channel MOSFET PB in the output section. As described above, the output signal of the NAND gate NA2 of the delay circuit DL2, that is, the internal signal ne is supplied to the inverter N through the inverter VB.
The output signal of the level shift circuit LS5, that is, the internal signal ni is supplied to the gate of the channel MOSFET NB.
It is supplied to the gate of the N-channel MOSFET NC.

The source of MOSFET PB constituting the output section is coupled to power supply voltage VDD, and the sources of MOSFET NB and NC are coupled to ground potential VSS and internal voltage VNN, respectively. The commonly coupled drains of these MOSFETs PB and NB and NC are coupled to main word line MW0.

As shown in FIG.
When the AM is in the standby state, in the unit main word line drive circuit UMWD0, as described above, the internal signals ng and ni are set to the high level such as the power supply voltage VDD or the internal voltage VDL, respectively, and the internal signal nh is grounded. Potential VSS
Is set to a low level. Therefore, both the MOSFETs PB and NB provided in the output unit are turned off, the MOSFET NC is turned on, and the main word line MW0 is set to the internal voltage VNN, that is, a low level invalid level such as -0.9V. .

On the other hand, when the dynamic RAM is selected in the active command cycle, the unit main word line drive circuit UMWD0 first sets the internal signal ng to a low level such as the ground potential VSS, and
The internal signal ni is set to a low level like the internal voltage VNN, and the internal signal nh is kept at a low level like the ground potential VSS. Therefore, the MOSFET NC is turned off in response to the low level of the internal signal ni, and the MOSF
ETPB is turned on in response to the low level of the internal signal ng, and the main word line MW0 is set to a high effective level such as the power supply voltage VDD. This state is
The dynamic RAM is set to a selected state, for example, in a precharge command cycle, and a main word line selection signal MS
It continues until 0B is returned to a high level like the internal voltage VDL.

When the dynamic RAM is selected in the precharge command cycle and returned to the standby state,
In unit main word line drive circuit UMWD0, first, internal signal ng is returned to a high level such as power supply voltage VDD, and internal signal nh is temporarily set to a high level such as internal voltage VDL. Is returned to the low level, the internal signal ni is returned to the high level such as the internal voltage VDL. In the output section of the unit main word line drive circuit UMWD0, first, the internal signal n
g, the MOSFET PB turns off in response to the high level of the internal signal nh, and
SFETNB is turned on. When the MOSFET NB is turned off in response to the low level of the internal signal nh, the internal signal ni is set to the high level,
The NC is turned on.

As a result, the main word line MW0 at a high effective level such as the power supply voltage VDD is obtained.
Is temporarily set to the ground potential VSS only while the internal signal nh is at the high level, and then returned to the low level invalid level such as the internal voltage VNN. As described above, it is one point of the present invention that the main word line MW0 is temporarily set to the ground potential VSS immediately before the main word line MW0 is set to the final invalid level, that is, the internal voltage VNN. This will be described in detail.

FIG. 7 is a partial circuit diagram of the first embodiment of the sub-word line drive circuit SWD0 included in the dynamic RAM of FIG. 1, and FIG. 8 is a signal waveform of the first embodiment. The figure is shown. The specific configuration and operation of the sub-word line drive circuits SWD0 to SWDk included in the dynamic RAM of this embodiment will be described with reference to these drawings. FIG. 7 also shows a partial circuit diagram of the sub memory array SMA0 of the memory array MARY corresponding to the sub word line drive circuit SWD0. Hereinafter, the sub-word line drive circuits SWD0 to SWDk and the unit sub-word line drive circuits USD0 to USDm will be described using the sub-word line drive circuit SWD0 and the unit sub-word line drive circuit USD0 in FIG.
Will be described.

In FIG. 7, sub memory array SMA0
Are (m + 1) sub-word lines SW0 to SWm (sub-word lines SW4 to SWm)
Are not shown. Hereinafter, the circuits related to the sub-word lines SW4 to SWm are also not shown) and n + 1 sets of complementary bit lines B0 * to Bn arranged in parallel in the horizontal direction.
* Is included. At the intersection of these sub-word lines and complementary bit lines, an information storage capacitor and an address selection MOS
(M + 1) × (n + 1) dynamic memory cells MC composed of FETs are arranged in a lattice. One electrode of the information storage capacitor of the (m + 1) memory cells MC arranged in the same column of the sub memory array SMA0 has complementary bit lines B0 * to
The gates of the address selection MOSFETs of the n + 1 memory cells MC which are alternately coupled to the non-inverted or inverted signal lines of Bn * with a predetermined regularity and are arranged in the same row are common to the corresponding sub-word lines SW0 to SWm, respectively. Be combined.

The sub-word lines SW0 to SWm of the sub-memory array SMA0 are arranged below the corresponding unit sub-word line driving circuit US of the sub-word line driving circuit SWD0.
D0 to USDm. The sub-word line drive circuit SWD0 receives p from the main word line drive circuit MWD via the main word line MW, that is, MW0 to MWp.
+1 bit main word line drive signal MW, that is, MW0
To MWp, and a 4-bit word line selection drive signal FX including non-inverted and inverted signals, that is, FX0 * to FX3 *. Note that the number p + 1 of the main word lines MW0 to MWp is equal to the sub word line S
With respect to the number m + 1 of W0 to SWm, there is a relationship of p + 1 = (m + 1) / 4.

The unit sub-word line driving circuits USD0 to USDm of the sub-word line driving circuit SWD0 are represented by the unit sub-word line driving circuit USD0 in FIG.
The drain (in this specification, N-channel MOSF
Although the upper terminal of the ET is called a drain, it may act as a source in an actual operation process. The same applies hereinafter) are the non-inverted signal lines of the word line select drive signal lines FX0 * to FX3 *, that is, the non-inverted word line select drive signal lines FX0T to FX0F.
N-channel MOS sequentially coupled to X3T every fourth
FET ND (third MOSFET) and N-channel MOSFET NE (first MOSFET) provided in series between main word line MW0 and internal voltage VNN
And NF (second MOSFET).

MOSFET ND constituting unit sub-word line drive circuit USD0 of sub-word line drive circuit SWD0
The power supply voltage VDD (first voltage) is commonly supplied to the gates of the gates, and the source (here, an N-channel MOSF) is supplied.
The lower terminal of the ET is referred to as a source, but may act as a drain in the course of actual operation. Hereinafter the same)
Is coupled to the gate of MOSFET NE. Also, M
The gates of the OSFETs NF are sequentially coupled to inverted signal lines of the corresponding word line selection drive signal lines FX0 * to FX3 *, that is, inverted word line selection drive signal lines FX0B to FX3B, and the source of the MOSFET NE, ie, the MOSF
The drain of ETNF is coupled to corresponding sub-word lines SW0-SW3 of sub-memory array SMA0.

As described above, the main word line MW0, that is, the main word line drive signal MW0 is, when the dynamic RAM is in the standby state as shown in FIG. Such a low level invalid level. Then, when the dynamic RAM is set to a selected state in an active command cycle, for example, it is set to a high effective level such as the power supply voltage VDD, and when the dynamic RAM is set to a selected state in a precharge command cycle, for example, After being temporarily set to the ground potential VSS for a predetermined period,
The level is returned to a low level such as the internal voltage VNN, that is, a final invalid level.

On the other hand, the word line selection drive signal FX0 * is
When the dynamic RAM is in the standby state, it is set to logic "0" and its non-inverted signal, that is, the non-inverted word line selection drive signal FX0T is a low level such as the internal voltage VNN, and its inverted signal, that is, the inverted word line selection drive signal. FX
0B is a high invalid level such as the internal voltage VDL. In addition, during the period from when the dynamic RAM is selected in the active command cycle to when the dynamic RAM is returned to the standby state by the precharge command cycle, the logic is set to "1", and the non-inverted word line selection drive signal FX0T is supplied with the power supply voltage. A high level such as VDD and the inverted word line selection drive signal FX0B are set to a low level effective level such as the internal voltage VNN.

The dynamic RAM is set in a standby state,
When the non-inversion and inversion signal lines of the main word line MW0 and the word line selection drive signal line FX0 * are both at an invalid level, the unit sub word line drive circuits USD0 to USDm of the sub word line drive circuit SWD0 have MOSFE.
The inverted word line selection drive signal FX0B to which TNF corresponds
In response to the high level of FX3B, it is turned on and MOS
FETNE is a corresponding non-inverted word line selection drive signal FX.
It is turned off in response to the low level of 0T. As a result, the sub word lines SW0 to SW0 of the sub memory array SMA0
SWm are all set to a non-selection level like the internal voltage VNN. At this time, the sub memory array SMA0
Are precharged by the corresponding unit circuit of the sense amplifier SA to have an intermediate potential such as the internal voltage HV.

Next, when the dynamic RAM is selected in the active command cycle ACTV, FIG.
First, as shown in FIG.
* To FX3 *, for example, the word line selection drive signal FX0
* Is alternatively set to logic "1" prior to the main word line MW0, and its non-inverted word line selection drive signal FX0
T is a high level such as the power supply voltage VDD, and its inverted word line selection drive signal FX0B is a low level effective level such as the internal voltage VNN. Also, with a slight delay, for example, the main word line MW0 of the main word lines MW0 to MWp is set to a high effective level such as the power supply voltage VDD.

In the sub-word line drive circuit SWD0, first, the word line selection drive signal FX0 * corresponds to (m +
1) / 4 unit sub word line drive circuits USD0, US
In D4 to USDm-3, the MOSFET NF is turned off in response to the low level of the inverted word line selection drive signal FX0B, and the gate capacitance of the MOSFET NE of each unit sub word line drive circuit is set to the corresponding MO.
Non-inverted word line selection drive signal FX via SFETND
MOST from the high level of 0T, that is, the power supply voltage VDD.
It is charged to a high level lower by the threshold voltage of TND.

Here, the main word line MW0 is slightly delayed.
Is set to a high level like the power supply voltage VDD, the main word line MW0 and the word line selection drive signal FX0 *
In the single unit sub-word line drive circuit USD0 corresponding to both the sub-word line SW and the corresponding sub-word line SW via the MOSFET NE,
0 is transmitted. At this time, the power supply voltage VDD
The gate potential of the MOSFET NE, which has been charged to a high level lower by the threshold voltage of the FET ND, is further boosted by the absolute value of the power supply voltage VDD by the self-boost action. Therefore, MOSFETN
D is turned off to act as a so-called cut MOSFET. The gate of MOSFET NE is held at a high potential, and the gate of MOSFET NE has a high potential, so that the effective level of main word line MW0, that is, power supply voltage VDD is reduced. The sub word line SW0 is transmitted to the sub word line SW0 without any change, and the sub word line SW0 is set to a complete selection level.

Note that the sub word line SW0 is connected to the power supply voltage VD
By setting it to a high level like D, the parasitic capacitance coupled to the sub-word line SW0 of the sub-memory array SMA0 is charged to this power supply voltage VDD. The high potential of the gate of the MOSFET NE of the unit sub-word line drive circuit USD0 is gradually leaked, for example, through a diffusion layer or the like serving as the source of the MOSFET ND. The time until the decrease is sufficiently long as compared with the operation cycle of the dynamic RAM, and is not a problem. Further, other unit sub-word line driving circuits USD4 to USD receiving the high level of the non-inverted word line selection driving signal FX0T.
At m-3, the corresponding main word lines MW1 to MWp are set to the low level like the internal voltage VNN.
A non-selection level such as NN is left.

In sub-memory array SMA0 in which sub-word line SW0 is alternatively set to a select level, a minute read signal according to data held in n + 1 memory cells MC coupled to sub-word line SW0 is supplied to complementary bit line B0.
* To Bn *. These minute read signals are respectively amplified by the unit amplifier circuits of the corresponding unit circuits of the sense amplifier SA, and finally the internal voltage VD
This is a binary read signal in which L is at a high level and the ground potential VSS is at a low level.

As described above, the operating power supply for the peripheral circuits including the sense amplifier SA and the X address decoder XD is set to the internal voltage VDL having a relatively small absolute value, and the operating power supply is lowered, thereby achieving miniaturization and high integration. Advanced dynamic R
The power consumption and the speed of the AM can be reduced and the breakdown voltage of the element can be prevented. Further, the sub word lines SW0 to S
By setting the final non-selection level of Wm to a negative potential such as the internal voltage VNN, the externally supplied power supply voltage VDD can be used as it is as the selection level of the sub-word lines SW0 to SWm, and the memory array MAR can be used.
Address selection MOSFE of memory cell MC constituting Y
T is completely turned off, the leakage current of the memory cell MC can be reduced, and its information retention characteristics can be improved. As a result, the refresh cycle in the standby state of the dynamic RAM can be lengthened, and its power consumption can be reduced. Can be achieved.

When the access to the specified address of the memory array MARY is completed and the dynamic RAM is selected in the precharge command cycle,
As described above, first, the main word line MW0 is temporarily set to the ground potential VSS for a predetermined period, and then to the final invalid level, that is, the internal voltage VNN. When the main word line MW0 is set to the ground potential VSS, the non-inverted word line selection drive signal F0 of the word line selection drive signal FX0 * is output.
X0T is set to an invalid level like the internal voltage VNN, and with a slight delay, the inverted word line selection drive signal FX0B of the word line selection drive signal FX0 * is set to an invalid level like the internal voltage VDL.

In the unit sub-word line drive circuit USD0 of the sub-word line drive circuit SWD0, the main word line MW0
Is changed to the ground potential VSS, the MOSFET NE
Receive the high level of the non-inverted word line selection drive signal FX0T, and remain in the ON state. Therefore, high-level charges such as the power supply voltage VDD accumulated in the parasitic capacitance of the sub-word line SW0 are transferred from the MOSFET NE to the main word line MW0 and the main word line drive circuit MW.
MOSF of D unit main word line drive circuit UMWD0
Discharged to ground potential VSS via ETNC. As described above, the ground potential VSS is connected to the external terminal VSS.
, And its impedance is extremely small. Therefore, the electric charge accumulated in the parasitic capacitance of the sub word line SW0 is transferred to the ground potential VS through the MOSFET NC of the unit main word line drive circuit UMWD0.
Even if it is discharged to S, the potential fluctuation of the ground potential VSS, that is, 0 V is small, and does not cause any problem.

The potential of the main word line MW0, that is, the potential of the sub word line SW0 is set to the ground potential VSS, and the non-inverted word line selection drive signal FX0T of the word line selection drive signal FX0 * is used.
Is returned to an invalid level such as the internal voltage VNN, the MOSFET N
E is turned off. Further, in response to the subsequent high level of the inverted word line selection drive signal FX0B, the MOSFET NF is turned on, and the sub word line SW0 is set to the final non-selection level, that is, the internal voltage VNN. Complementary bit line B
The non-inverted and inverted signal lines of 0 * to Bn * are precharged by the corresponding unit circuits of the sense amplifier SA when a predetermined time has elapsed after the sub-word line SW0 is set to the non-selection level, and the intermediate potential HV It is said.

As described above, in the dynamic RAM of this embodiment, the unit sub-word line drive circuits USD0 to USDm of the sub-word line drive circuits SWD0 to SWDk provided corresponding to the sub-word lines SW0 to SWm are three N The channel MOSFETs ND to NF, that is, only the N-channel MOSFETs, and the main word lines MW0 to MWp are temporarily set to the ground potential VSS immediately before being set to the invalid level.
After the high-level charges accumulated in the parasitic capacitances 0 to SWm are discharged to the low-impedance ground potential VSS through the MOSFET NE of each unit sub-word line drive circuit and the main word lines MW0 to MWp, The selected level is set to the internal voltage VNN.

As a result, a P-channel MOSFET requiring a larger size and a well isolation region than an N-channel MOSFET having the same driving capability is obtained.
Can be constituted only by an N-channel MOSFET without the unit sub-word line drive circuits USD0 to USDm, and a MOSF for temporarily lowering the high level of the sub-word line to the ground potential VSS.
ET is not provided for each unit sub-word line drive circuit, that is, all the sub-word line drive circuits SWD0 to SWD0 are not provided.
By providing the sub word line driving circuits SWD0 to SWDk in the main word line driving circuit shared by SWDk, the required layout area can be reduced. As a result, the chip size of the dynamic RAM is reduced,
The cost can be reduced, the load on the internal voltage VNN formed by the built-in internal voltage generation circuit VG can be reduced, the potential fluctuation can be suppressed, and the operation of the dynamic RAM can be stabilized. You can do it.

FIG. 9 shows a sub-word line drive circuit SWD0 included in a dynamic RAM to which the present invention is applied.
10 is a partial circuit diagram of the second embodiment, and FIG. 10 is a signal waveform diagram of the second embodiment. In addition,
The sub-word line drive circuit SWD0 of this embodiment is the same as that of FIG.
And basically follows the embodiment of FIG.
The description will be added only for the different parts.

In FIG. 9, the unit sub-word line drive circuit USD0 of the sub-word line drive circuit SWD0 of this embodiment is shown.
To USDm are unit sub-word line drive circuits USD0 shown in FIG.
, The corresponding main word line M
Two N-channel MOSFETs NG (first MO) provided in series between W0 and internal voltage supply point VNN
SFET) and NH (second MOSFET). Among them, the gate of the MOSFET NG is coupled to the non-inverted signal line of the corresponding word line select drive signal line FX0 *, that is, the non-inverted word line select drive signal line FX0T.
The gate of ETNH is an inverted signal line of the word line selection drive signal FX0 *, that is, an inverted word line selection drive signal line FX0B.
Is combined with The commonly coupled drain and source of MOSFETs NG and NH are connected to corresponding sub-word line SW
Combined with zero.

In this embodiment, the main word line MW
0, as shown in FIG. 10, as in the embodiment of FIGS. 7 and 8, when the dynamic RAM is selected in the active command cycle ACTV, a high effective level such as the power supply voltage VDD is obtained. It is said. When the dynamic RAM is selected in the precharge command cycle PREC, it is temporarily set to the ground potential VSS for a predetermined period, and then to the final invalid level, that is, the internal voltage VNN.

On the other hand, the non-inverted signal line of the word line select drive signal line FX0 *, that is, the non-inverted word line select drive signal line FX
0T is a high voltage that is higher than the power supply voltage VDD by at least the threshold voltage of the MOSFET NG at about the same time that the main word line MW0 is set to the effective level when the dynamic RAM is selected in the active command cycle ACTV. VCH is set to an effective level such as VCH, and the dynamic RAM
When the selected state is set by EC, the main word line MW
When 0 is set to the ground potential VSS, it becomes an invalid level like the internal voltage VNN. When the dynamic RAM is selected in the active command cycle ACTV, the inverted signal line of the word line selection drive signal line FX0 *, that is, the inverted word line selection drive signal line FX0B, has an effective level such as the internal voltage VNN. When the dynamic RAM is selected in the precharge command cycle PREC, the non-inverted word line selection drive signal F
After X0T is set to the invalid level, it is set to an invalid level such as the internal voltage VDL.

When the dynamic RAM is in the standby state, the main word line MW0 and the word line selection drive signal FX
When both the non-inverted and inverted signal lines of 0 * are at an invalid level, in the unit sub-word line drive circuit USD0 of the sub-word line drive circuit SWD0, the MOSFET NH is turned on in response to the high level of the corresponding inverted word line selection drive signal FX0B. State, the MOSFET NG is turned off, and the sub-word line SW0 is set to a non-selection level such as the internal voltage VNN.

Next, when the dynamic RAM is set to the selected state in the active command cycle ACTV, in the unit sub-word line drive circuit USD0, the MOSFET N
H is turned off in response to the low level of the inverted word line selection drive signal FX0B, and the MOSFET NG is turned on in response to the high level of the non-inverted word line selection drive signal FX0T. Then, the main word line MW0
Is set to a high level like the power supply voltage VDD,
The high level of the main word line MW0 is the MOSFET
The signal is transmitted to the corresponding sub-word line SW0 via NG. At this time, the high level of the non-inverted word line selection drive signal FX0T is the high voltage VCH which is higher than the power supply voltage VDD by at least the threshold voltage of the MOSFET NG, as described above. That is, the power supply voltage VDD is transmitted without being affected by the threshold voltage of the MOSFET NG, and the sub-word line SW0 is set to a complete selection level like the power supply voltage VDD.

When the access to the designated address of the memory array MARY is completed and the dynamic RAM is selected in the precharge command cycle,
As described above, first, the main word line MW0 is temporarily set to the ground potential VSS for a predetermined period, and then to the final non-selection level, that is, the internal voltage VNN. When the main word line MW0 is set to the ground potential VSS, the non-inverted word line selection drive signal FX0T of the word line selection drive signal FX0 * is set to an invalid level like the internal voltage VNN,
Further later, the inverted word line selection drive signal FX0B of the word line selection drive signal FX0 * is set to an invalid level such as the internal voltage VDL.

In the unit sub-word line drive circuit USD0,
When the main word line MW0 is changed to the ground potential VSS, the non-inverted word line selection drive signal FX0T is still at the high level, and the MOSFET NG is kept on. Therefore, the high-level charge accumulated in the parasitic capacitance of the sub-word line SW0 is discharged from the MOSFET NG to the ground potential VSS via the main word line MW0.

The potential of the main word line MW0, that is, the potential of the sub word line SW0 is set to the ground potential VSS, and the non-inverted word line selection drive signal FX0T of the word line selection drive signal FX0 * is used.
Is returned to an invalid level such as the internal voltage VNN, the MOSFET N
G is turned off. Further, in response to the subsequent high level of the inverted word line selection drive signal FX0B, the MOSFET NH is turned on, and the sub word line SW0 is set to the final non-selection level, that is, the internal voltage VNN.

As described above, in the dynamic RAM of this embodiment, the unit sub-word line drive circuits USD0 to USDm of the sub-word line drive circuits SWD0 to SWDk provided corresponding to the sub-word lines SW0 to SWm include two N-channels. MOSFETs NG to NH, that is, only N-channel MOSFETs, and the main word lines MW0 to MWp are temporarily set to the ground potential VSS immediately before being set to the invalid level.
To the high-level charge accumulated in the parasitic capacitance of SWm
After being discharged to the low-impedance ground potential VSS via the MOSFET NG of each unit sub-word line drive circuit and the main word lines MW0 to MWp, the final non-selection level, that is, the internal voltage VNN is set. The non-inverted signal lines of the word line selection drive signal lines FX0 * to FX3 *, that is, the non-inverted word line selection drive signals FX0T to FX3
The effective level of T is higher than the power supply voltage VDD by MOSFET NG
High voltage VCH higher than the threshold voltage of
A static selection operation without using the self-boost operation by the FET capacitance is performed.

As a result, in this embodiment, the unit sub-word line drive circuits USD0 to USDm are constituted by two N-channel MOSFETs, and the layout required area is further reduced to further reduce the cost of the dynamic RAM. 7 and 8, the load on the internal voltage VNN formed by the internal voltage generating circuit VG is reduced, the potential fluctuation is suppressed, and the operation of the dynamic RAM is improved. Can be stabilized. Further, the unit sub-word line driving circuit U
Since the selection operation of the sub-word lines SW0 to SWm by SD0 to USDm is performed statically, even when the sub-word lines are set to the selected level for a long time, the required level can be maintained, thereby enabling the operation of the dynamic RAM. Can be further stabilized.

FIG. 11 shows a sub word line drive circuit SWD included in a dynamic RAM to which the present invention is applied.
0 is a partial circuit diagram of the third embodiment, and FIG. 12 is a signal waveform diagram of the third embodiment. In addition,
Since the sub-word line drive circuit SWD0 of this embodiment basically follows the embodiment of FIGS. 7 and 8, only the different parts will be described.

Referring to FIG. 11, unit sub-word line drive circuits USD0 to USDm forming sub-word line drive circuit SWD0 of this embodiment correspond to corresponding word lines as represented by unit sub-word line drive circuit USD0 in the figure. N-channel MOSFET N provided in series between selection drive signal lines FX0-FX3 and internal voltage VNN
J (first MOSFET) and NK (second MOSFET)
T) and its drain is, for example, the non-inverted signal line of the corresponding main word line MW0 *, that is, the non-inverted main word line M
N-channel MOs that are commonly coupled to W0T sequentially four by four
SFETNI (fourth MOSFET). The power supply voltage VDD is commonly supplied to the gate of the MOSFET NI, and the source thereof is
Coupled to the gate of TNJ. In addition, MOSFETNK
Are sequentially connected to an inverted signal line of the corresponding main word line MW0 *, that is, an inverted main word line MW0B.
The sources and drains of the MOSFETs NJ and NK which are commonly coupled one by one are coupled to the corresponding sub-word line SW0.

As shown in FIG. 12, like the main word line MW0 of the embodiment shown in FIGS. 7 and 8, the word line selection drive signal FX0 changes the internal voltage VNN when the dynamic RAM is in the standby state. When the dynamic RAM is set to the selected state in the active command cycle, the selected level is set to the power supply voltage VDD. When the dynamic RAM is selected in the precharge command cycle, the dynamic RAM is temporarily set to the ground potential VSS for a predetermined period, and then returned to the final non-selection level such as the internal voltage VNN. On the other hand, the main word line MW0 * has a dynamic type R like the word line selection drive signal FX0 * shown in FIGS.
When the AM is in the standby state, it is set to logic "0", and is set to logic "1" during the period from when the dynamic RAM is selected in the active command cycle until the dynamic RAM is returned to the standby state by the precharge command cycle. .

The dynamic RAM is set in a standby state,
Word line selection drive signal FX0 and main word line M
When both the non-inverted and inverted signal lines of W0 * are at the invalid level, in the unit sub-word line drive circuit USD0 of the sub-word line drive circuit SWD0, the MOSFET NK is turned on in response to the high level of the corresponding main word line MW0B, and the MOSFET NJ Is turned off in response to the low level of the corresponding non-inverted main word line MW0T, so that sub word line SW0 of sub memory array SMA0 is turned off.
Is set to a non-selection level like the internal voltage VNN.

Next, when the dynamic RAM is set to the selected state in the active command cycle ACTV, the unit sub-word line drive circuit USD0 first sets the MOSFET
NK is turned off in response to the low level of the inverted main word line MW0B, and the gate capacitance of the MOSFET NJ becomes
From the high level of the non-inverted main word line MW0T, that is, the power supply voltage VDD via the corresponding MOSFET NI,
It is charged to a high level lower by the threshold voltage of SFETNI. When the word line selection drive signal FX0 is set to a high level like the power supply voltage VDD with a slight delay, the high level of the word line selection drive signal FX0 is applied to the corresponding sub-word line SW0 via the MOSFET NJ in the ON state. Is transmitted.

At this time, the MOSFE is changed from the power supply voltage VDD.
The gate potential of MOSFET NJ, which has been charged to a high level lower by the threshold voltage of TNI, is further boosted by the absolute value of power supply voltage VDD due to its self-boost action. Therefore, the MOSFET NI is turned off and acts as a cut MOSFET.
The gate of the OSFET NJ is held at a high potential, and the effective level of the word line selection drive signal FX0, that is, the power supply voltage VDD is not reduced by the high potential of the gate of the MOSFET NJ, and the sub-word line SW is not reduced.
0, and the sub-word line SW0 is set to a complete selection level.

When the access to the specified address of the memory array MARY is completed and the dynamic RAM is selected in the precharge command cycle,
As described above, first, the word line selection drive signal FX0 is temporarily set to the ground potential VSS for a predetermined period, and then to the final non-selection level, that is, the internal voltage VNN. When the word line selection drive signal FX0 is set to the ground potential VSS, the non-inverted main word line MW0T of the main word line MW0 * is set to an invalid level such as the internal voltage VNN,
With further delay, the inverted main word line MW0B of the main word line MW0 * is set to a high level invalid level such as the internal voltage VDL.

In the unit sub-word line drive circuit USD0,
When the word line selection drive signal FX0 is changed to the ground potential VSS, the MOSFET NJ is kept on. Therefore, the high-level charge stored in the parasitic capacitance of the sub-word line SW0 is discharged from the MOSFET NJ to the ground potential VSS via the word line selection drive signal FX0. Also, with a slight delay, the main word line MW
0 * non-inverting main word line MW0T is the internal voltage VNN
MOSFETNJ
Is turned off, the MOSFET NK is turned on in response to the subsequent high level of the inverted main word line MW0B, and the sub-word line SW0 is set to the final non-selection level, that is, the internal voltage VNN.

As described above, in the dynamic RAM of this embodiment, the unit sub-word line driving circuits USD0 to USDm of the sub-word line driving circuits SWD0 to SWDk provided corresponding to the sub-word lines SW0 to SWm are provided as shown in FIG. As in the embodiment of FIG.
SFETs NI to NK and the main word lines MW0 to MWp of the embodiment of FIGS.
Are replaced by word line selection drive signals FX0 to FX3, and the word line selection drive signals FX0 * to FX3 * are replaced by main word lines MW0 * to MWp *, and have the same functions. As a result, also in this embodiment, it is possible to obtain the same operation and effects as those of the embodiment of FIGS. 7 and 8, thereby stabilizing the operation, reducing the chip size of the dynamic RAM, and Cost can be reduced.

FIG. 13 shows a sub-word line drive circuit SWD included in a dynamic RAM to which the present invention is applied.
0 is a partial circuit diagram of the fourth embodiment, and FIG. 14 is a signal waveform diagram of the fourth embodiment. In addition,
Since this embodiment basically follows the embodiment of FIGS. 7 and 8 and FIGS. 11 and 12, only the different parts will be described.

Referring to FIG. 13, unit sub-word line driving circuits USD0 to USDm constituting sub-word line driving circuit SWD0 of this embodiment are unit sub-word line driving circuits U
As represented by SD0, two N-channel MOSFETs provided in series between corresponding word line selection drive signal lines FX0 to FX3 and internal voltage VNN
NM (first MOSFET) and NN (second MOSF
ET) and an N-channel M whose drains are commonly coupled to the corresponding main word line MW0, for example, four by four.
OSFETNL (fifth MOSFET).

The power supply voltage VDD is commonly supplied to the gate of the MOSFET NL, and the source thereof is
Coupled to the gate of FETNM. Also, MOSFET
The gate of NN is the corresponding N-channel MOSFET N
P (sixth MOSFET) coupled to the power supply voltage VDD and a corresponding N-channel MOSFET N
Internal voltage supply point VN via O (seventh MOSFET)
N. The commonly coupled sources and drains of MOSFETs NM and NN are connected to corresponding sub-word lines S
Connected to W0. Further, a corresponding precharge control signal PC is commonly supplied to a gate of MOSFET NP, and a gate of MOSFET NO is coupled to a corresponding sub-word line SW0.

As shown in FIG. 14, word line selection drive signal FX0 is at an invalid level such as internal voltage VNN when dynamic RAM is in a standby state, and dynamic RAM is selected in active command cycle. Then, it is set to an effective level like the power supply voltage VDD. When the dynamic RAM is set to the selected state in the precharge command cycle, the dynamic RAM is temporarily set to the ground potential VSS for a predetermined period, and then the internal voltage VNN is set.
Is returned to an invalid level such as On the other hand, the main word line MW0 is set to an invalid level such as the internal voltage VNN when the dynamic RAM is in the standby state, and is set in the standby state by the precharge command cycle after the dynamic RAM is selected in the active command cycle. Until the power supply voltage VDD is restored, it is kept at an effective level like the power supply voltage VDD. Further, a precharge control signal PC
As in the case of the inverted word line selection drive signal FX0B in the embodiment of FIGS. 7 and 8, when the dynamic RAM is in the standby state, it is set to an invalid level such as the internal voltage VDL, and the dynamic RAM is activated. The internal voltage VNN is applied from the time when the cycle is selected to the time when the standby state is returned by the precharge command cycle.
The effective level is as follows.

The dynamic RAM is set in a standby state,
When the word line selection drive signal FX0, the main word line MW0, and the precharge control signal PC are all at an invalid level, in the unit sub-word line drive circuit USD0 of the sub-word line drive circuit SWD0, the MOSFET NP corresponds to the corresponding precharge control signal PC. The transistor NN is turned on in response to the high level, and the MOSFET NN is also turned on when the power supply voltage VDD is supplied via the MOSFET NP in the on state. MOSFET NM
Is turned off in response to the low level of the corresponding main word line MW0, so that sub-word line SW0 is set to a non-selection level like internal voltage VNN, and
SFETNO is turned off.

Next, when the dynamic RAM is set to the selected state in the active command cycle ACTV, the unit sub-word line drive circuit USD0 first sets the MOSFET
NP is turned off in response to the low level of the precharge control signal PC, and the gate capacitance of the MOSFET NM is changed to the main word line MW0 via the corresponding MOSFET NL.
From the power supply voltage VDD,
It is charged to a high level lower by the threshold voltage of L. When the word line selection drive signal FX0 is set to the high level with a slight delay, the word line selection drive signal FX0
The high level of 0 is transmitted to the corresponding sub-word line SW0 via the MOSFET NM.

At this time, the MOSFE is changed from the power supply voltage VDD.
The gate potential of MOSFET NM, which has been charged to a high level lower by the threshold voltage of TNL, is further boosted by the absolute value of power supply voltage VDD by its self-boost action. Therefore, the MOSFET NL is turned off and acts as a cut MOSFET.
By holding the gate of the OSFET NM at a high potential and holding the gate of the MOSFET NM at a high potential, the effective level of the word line selection drive signal FX0, that is, the power supply voltage VDD is transmitted to the sub-word line SW0 as it is. The MOSFET NO is turned on when receiving a high level such as the power supply voltage VDD of the sub-word line SW0, and changes the gate potential of the MOSFET NN to the internal voltage VNN.
And the MOSFET NN is turned off.

That is, in this embodiment, the MOSFET N
By adding O and NP, the unit sub-word line drive circuits USD0 to USDm have a so-called self-latch function, and both the main word line and the word line selection drive signal need only be provided with a non-inverted signal. As a result, the required layout area of the sub-word line drive circuits SWD0 to SWDk can be further reduced, the chip size of the dynamic RAM can be further reduced, and the cost can be further reduced.

When the access to the specified address of the memory array MARY is completed and the dynamic RAM is selected in the precharge command cycle, first, the word line selection drive signal FX0 is temporarily set to the ground potential VSS for a predetermined period. After that, the final invalid level, that is, the internal voltage VNN is set. When the word line selection drive signal FX0 is set to the ground potential VSS, the main word line MW0 is set to an invalid level like the internal voltage VNN,
With further delay, the precharge control signal PC changes to the internal voltage VD.
The invalid level is a high level such as L.

In the unit sub-word line drive circuit USD0,
When the word line selection drive signal FX0 is changed to the ground potential VSS, the MOSFET NM is kept on. Therefore, the high-level charge stored in the parasitic capacitance of the sub-word line SW0 is discharged from the MOSFET NM to the ground potential VSS via the word line selection drive signal FX0. Also, with a slight delay, the main word line MW
When 0 is returned to an invalid level such as the internal voltage VNN, the MOSFET NM is turned off, and the MOSFET NP receives the high level of the precharge control signal PC.
Is turned on, the MOSFET NN is turned on, and the sub-word line SW0 is set to the final non-selection level, that is, the internal voltage VNN. The MOSFET NO is turned off in response to the low level of the sub-word line SW0, and returns to the initial state.

As described above, in the dynamic RAM of this embodiment, the unit sub-word line driving circuits USD0 to USDm of the sub-word line driving circuits SWD0 to SWDk provided corresponding to the sub-word lines SW0 to SWm have a total of five. Unit sub-word line drive circuits USD0 to USD are constituted by N-channel MOSFETs NL to NP and MOSFETs NO and NP are added.
m has a self-latch function, whereby the required number of main word lines and word line selection drive signal lines can be reduced. As a result, in the case of this embodiment, the layout required area of the sub-word line drive circuits SWD0 to SWDk is further reduced while obtaining the same operation and effect as those of the embodiment of FIGS. The size can be further reduced, and the cost can be further reduced.

The functions and effects obtained from the above embodiments are as follows. That is, (1) In a dynamic RAM or the like employing a hierarchical word line system and a negative word line system, the unit sub word line drive circuit of the sub word line drive circuit provided corresponding to the sub word line is composed of only N-channel MOSFETs, For example, an N-channel first MOSF provided between a corresponding main word line and a sub-word line and receiving a non-inverted word line selection drive signal corresponding to its gate.
Basically, an ET and an N-channel type second MOSFET provided between a sub-word line and a supply point of a negative potential at the final non-selection level and receiving an inverted word line selection drive signal corresponding to its gate. And the first
After the level of the main word line is temporarily set to the ground potential of the circuit in a state where the MOSFET is turned on, the level of the sub word line is first set to the ground level of the circuit by setting it to a negative potential which is a non-selection level of the sub word line. Without providing a MOSFET for lowering the potential to each unit sub-word line drive circuit, the load on the negative potential having a relatively small supply capacity can be reduced and the potential fluctuation can be suppressed.

(2) According to the above item (1), the operation of the dynamic RAM or the like can be stabilized. (3) According to the above item (1), the layout of the unit sub-word line drive circuit is eliminated from each unit sub-word line drive circuit by eliminating the P-channel MOSFET having a larger size than the N-channel MOSFET and requiring the well isolation region. The effect that the required area can be reduced can be obtained. (4) According to the above items (1) and (3), it is possible to obtain an effect that the chip size of the dynamic RAM or the like can be reduced and the cost can be reduced.

(5) In the above items (1) to (4), an N-channel type between the gate of the second MOSFET and the first voltage, the gate of which receives a predetermined precharge control signal. A sixth MOSFET is provided, between the gate of the second MOSFET and the supply point of the negative potential.
By providing an N-channel type seventh MOSFET whose gate is coupled to a corresponding sub-word line, each unit sub-word line drive circuit has a self-latch function, and a main word line and a word line selection drive signal line are required. The effect that the number can be reduced can be obtained. (6) According to the above item (5), the required area of the unit sub-word line drive circuit can be further reduced, the chip size of the dynamic RAM can be further reduced, and the cost can be further reduced. Can be

Although the invention made by the inventor has been specifically described based on the embodiments, the invention is not limited to the above-described embodiments, and can be variously modified without departing from the gist thereof. Needless to say, there is. For example, in FIG. 1, the memory array MARY of the dynamic RAM can be divided into an arbitrary number of sub-memory arrays in the bit line extension direction as described above. Each of the sub memory arrays SMA0 to SMAk can include a predetermined number of redundant elements, and the dynamic RAM can include a circuit for relieving defects. The dynamic RAM does not require that the hierarchical word line system be employed. Further, the dynamic RAM can include a plurality of banks composed of a memory array MARY and its direct peripheral circuits. Can be taken.

In FIG. 2, main word line driving circuit M
As described above, the WD can actually include the unit word line selection driving circuits UFXD0 to UFXD3 corresponding to the sub word line driving circuits SWD0 to SWDk.
May be provided in common, and a circuit for combining the output signal thereof, that is, the word line selection drive signals FX0 * to FX3 *, and the sub memory array selection signal may be separately provided. The combination of the internal address signals supplied to the word line selection drive decoder FXSD of the X address decoder XD and the main word line drive decoder MWSD can take various embodiments.

In FIG. 3 and FIG. 5, the unit word line selection drive circuit UFXD0 and the unit main word line drive circuit U
The specific configuration of the MWD0 and the conductivity type of the MOSFET are as follows.
It is not restricted by this embodiment. 4 and 6, the specific level and timing relationship of each signal does not limit the gist of the present invention.

In FIG. 7, FIG. 9, FIG. 11, and FIG. 13, the unit sub-word line drive circuit USD0 of the sub-word line drive circuit SWD0 is such that the main word line or word line selection drive signal supplied to its source is finally invalidated. It is possible to include a P-channel MOSFET similar to the MOSFETPC of FIG. 15 on condition that the potential is temporarily set to the ground potential VSS immediately before the level is set. In each embodiment, the roles of the main word line and the word line selection drive signal can be interchanged. Furthermore, the specific configuration of the unit sub-word line drive circuit USD0, the conductivity type of the MOSFET, and the like can take various embodiments. 8, 10, and 1
2 and FIG. 14, the specific level and timing relationship of each signal does not limit the gist of the present invention.

In the above description, the case where the invention made by the present inventor is mainly applied to the dynamic RAM, which is the application field of the background, has been described.
The present invention is not limited to this, and can be applied to, for example, various memory integrated circuit devices having a dynamic RAM as a basic configuration, and logic integrated circuit devices including such a memory integrated circuit device. INDUSTRIAL APPLICABILITY The present invention can be widely applied to at least a negative word line type semiconductor memory device and a device or system including the same.

[0124]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, in a dynamic RAM or the like employing a hierarchical word line system and a negative word line system, a unit sub word line drive circuit of a sub word line drive circuit provided corresponding to a sub word line is constituted by only N-channel MOSFETs, for example, An N-channel first MOSFET provided between a main word line and a sub-word line and receiving a non-inverted word line selection drive signal corresponding to its gate, and a sub-word line and a negative potential supply at the final non-selection level And an N-channel type second MOSFET which receives an inverted word line selection drive signal corresponding to the gate of the N-channel MOSFET, and sets the level of the main word line to ON by the first MOSFET. In this state, after temporarily setting the circuit to the ground potential, By setting the negative potential as the selected level, the load on the negative potential having a relatively small supply capacity can be reduced without providing a MOSFET for lowering the level of the sub-word line to the ground potential of the circuit for each unit sub-word line driving circuit. In addition, the potential fluctuation can be suppressed, and the size of each unit sub-word line drive circuit is larger than that of the N-channel MOSFET, and the P-channel MOSFET requiring a well isolation region is eliminated. The required area can be reduced. As a result, the chip size of the dynamic RAM or the like can be reduced while stabilizing the operation, and the cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a dynamic RAM to which the present invention is applied.

FIG. 2 is a block diagram showing one embodiment of a main word line drive circuit included in the dynamic RAM of FIG. 1;

FIG. 3 is a circuit diagram showing one embodiment of a unit word line selection drive circuit included in the main word line drive circuit of FIG. 2;

FIG. 4 is a signal waveform diagram showing one embodiment of a unit word line selection drive circuit of FIG. 3;

FIG. 5 is a circuit diagram showing one embodiment of a unit main word line drive circuit included in the main word line drive circuit of FIG. 2;

FIG. 6 is a signal waveform diagram showing one embodiment of the unit main word line drive circuit of FIG. 5;

FIG. 7 is a partial circuit diagram showing a first embodiment of a sub-word line drive circuit included in the dynamic RAM of FIG. 1;

FIG. 8 is a signal waveform diagram showing one embodiment of the sub-word line drive circuit of FIG. 7;

FIG. 9 is a partial circuit diagram showing a second embodiment of a sub-word line drive circuit included in a dynamic RAM to which the present invention is applied.

FIG. 10 is a signal waveform diagram showing one embodiment of the sub-word line drive circuit of FIG. 9;

FIG. 11 is a dynamic RAM to which the present invention is applied;
FIG. 13 is a partial circuit diagram showing a third embodiment of the sub-word line drive circuit included in the third embodiment.

FIG. 12 is a signal waveform diagram showing one embodiment of the sub-word line drive circuit of FIG. 11;

FIG. 13 is a dynamic RAM to which the present invention is applied;
FIG. 13 is a partial circuit diagram showing a fourth embodiment of the sub-word line drive circuit included in the fourth embodiment.

14 is a signal waveform diagram showing one embodiment of the sub-word line drive circuit of FIG.

FIG. 15 is a partial circuit diagram showing an example of a sub-word line drive circuit included in a dynamic RAM developed by the present inventors prior to the present invention.

FIG. 16 is a signal waveform diagram illustrating an example of a sub-word line drive circuit of FIG.

[Explanation of symbols]

MARY: Memory array, SMA0 to SMAk: Sub memory array, SWD0 to SWDk: Sub word line drive circuit, MW: Main word line, SW: Sub word line, MWD: Main word line drive circuit, XD ... X
Address decoder, XB... X address buffer, SA
…… Sense amplifier, YD …… Y address decoder, YB
... Y address buffer, IO ... Data input / output circuit,
TG: timing generation circuit, VG: internal voltage generation circuit, D0 to Dj: input / output data or its input / output terminals,
CLK ... clock signal or its input terminal, CKE ...
Clock enable signal or its input terminal, RASB ...
... Row address strobe signal or its input terminal, CA
SB: column address strobe signal or input terminal thereof, WEB: write enable signal or input terminal thereof, A0 to Ai: address signal or input terminal thereof, V
DD: power supply voltage or its input terminal, VSS: ground potential or its input terminal, VDL, VNN: internal voltage. M
W0 to MWp, MW0 * to MWp * ... main word lines, FX0 to FX3, FX0 * to FX3 * ... word line selection drive signals, SW0 to SWm ... subword lines, B0
* To Bn *: complementary bit line, MC: dynamic memory cell, USD0 to USDm: unit sub-word line drive circuit. FXSD: Word line selection drive decoder, M
WSD: Main word line drive decoder, UFXD0
UFXD3: Unit word line selection drive circuit, UMWD0
.About.UMWDm... A unit main word line drive circuit. LS1
... LS5... Level shift circuit, DL1 to DL2. P1-PC: P-channel MOSFET, N
1 to NR: N-channel MOSFET, V1 to VC ...
... Inverters, NA1 to NA2 ... Nand gates. AC
TV ... active command or active command cycle, PREC ... precharge command or precharge command cycle.

Continued on the front page (72) Inventor Masashi Horiguchi 5-2-1, Josuihonmachi, Kodaira-shi, Tokyo Inside the Semiconductor Division, Hitachi, Ltd. Inside Hitachi, Ltd. Device Development Center

Claims (7)

[Claims] A memory array including a word line whose selection level is set to a first potential and whose non-selection level is set to a second potential having a polarity opposite to that of the first potential; A level is set to the first potential, and a first drive signal line whose effective level is set to the second potential is provided between a selected drive signal line and the word line corresponding to the selected drive signal line. And a word line drive circuit including a second MOSFET provided between the corresponding word line and the supply point of the second potential, respectively, and the selection drive signal line is A semiconductor memory device which is temporarily set to a circuit ground potential immediately before being set to a second potential. 2. The method according to claim 1, wherein the first potential is a predetermined positive potential, and the second potential is a predetermined negative potential. A semiconductor memory device wherein both MOSFETs are N-channel MOSFETs. 3. The semiconductor memory device according to claim 1, wherein the semiconductor memory device employs a hierarchical word line system, wherein a sub word line and a main word line provided corresponding to a predetermined number of the sub word lines are provided. And a word line selection drive signal line for alternately designating the predetermined number of sub word lines corresponding to each of the main word lines, wherein the word line is the sub word line The word line drive circuit is a sub-word line drive circuit provided corresponding to the sub-word line, wherein the sub-word line has a corresponding main word line at an effective level, and the corresponding word line selection drive A semiconductor memory device, wherein the signal line is selectively set to the above-mentioned selection level by being set to an effective level. 4. The method according to claim 1, wherein the selection drive signal line is the main word line, and the sub-word line drive circuit is the first MOSFET.
And a third MOSFET of an N-channel type which is provided between the gate of the word line selection drive signal line and receives the first voltage at the gate thereof. A semiconductor memory device which is coupled to an inverted signal line of the corresponding word line selection drive signal line. 5. The word line selection drive signal according to claim 1, wherein the selection drive signal line is the main word line, and the gate of the first MOSFET is a corresponding word line selection drive signal. And the second MOSFE
A semiconductor memory device, wherein the gate of T is coupled to its inverted signal line. 6. The method according to claim 1, wherein the selection drive signal line is the word line selection drive signal line, and the sub-word line drive circuit is the first MOSFET.
A fourth MOSFET of an N-channel type provided between the gate of the second MOSFET and the corresponding main word line and receiving a first voltage at the gate thereof. A semiconductor memory device coupled to an inverted signal line of the main word line. 7. The method according to claim 1, wherein the selection drive signal line is the word line selection drive signal line, and the sub-word line drive circuit is the first MOSFET.
An N-channel fifth MOSFET provided between the gate of the second MOSFET and the corresponding main word line and receiving a first voltage at the gate; and a fifth MOSFET between the gate of the second MOSFET and the first voltage. Provided at its gate to receive a precharge control signal
A sixth MOSFET of a channel type; a seventh MOSFET of an N-channel type provided between the gate of the second MOSFET and the supply point of the negative potential, the gate of which is coupled to the corresponding sub-word line; A semiconductor memory device characterized by including: