JP2001093989A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To adjust the threshold voltage of a read transistor, without adding special processes in a DRAM gain cell for logic mixed mounting. SOLUTION: A semiconductor device is provided with a storage node SN for retaining data as a potential change, and a read transistor TR, where a gate is connected to the storage node SN, either a source or a drain is connected to a bit line BL, and the transistor TR is turned on or off according to the potential of the storage node SN, and stored data is read out to the bit line BL. The gate electrode of the read transistor TR is made of a semiconductor material having an opposite conductivity to that of a channel, namely p+ polysilicon, when the read transistor TR is, for example, an nMOSFET.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a so-called DRAM.
The present invention relates to a semiconductor device having a memory cell structure called a gain cell, in which data held in an internal storage node is amplified by a reading transistor and read out to a bit line.

[0002]

2. Description of the Related Art At present, a DRAM (Dynamic Random Access Memory) which is the most representative of a high-density, large-capacity semiconductor memory.
In (ory), a memory cell is configured by connecting a transistor, which is turned on / off by a word line potential between a bit line and a common potential line, and a memory capacitor in series. In this one-transistor-one-capacitor type memory cell, the connection point between the memory capacitor and the transistor serves as a storage node, and data "1" and "0" are determined based on the difference in the amount of charge stored in the storage node. . To ensure stable operation when reading stored data,
It is necessary to cause a sufficiently large potential change to appear on the bit line. Therefore, in order to increase the capacity (capacitor capacity) that can store the charge of the memory capacitor,
A dedicated process including a step of forming a capacitor electrode having a special shape or a step of forming a film made of a high dielectric material is indispensable.

However, as the occupied area of the semiconductor memory cell is reduced, the capacitance value of the capacitor tends to decrease. In addition, since the bit line capacitance increases due to the increase in the capacitance, the data can be read without being buried in noise. It has become a remarkable problem that it is more difficult to obtain a change in bit line potential than before. Therefore, if the cell area is reduced without changing the structure and the material, it is expected that the read signal of the DRAM cell will be small, and eventually it will be difficult to detect the data stored in the memory cell. You.

In recent years, systematization of LSI has progressed,
Various types of memory-embedded logic LSIs have been realized more than before. For this reason, DRA
Rather than increasing the capacitance of the capacitor per unit area of M, it has become easier to obtain a cost advantage if the process exclusive for the capacitor is abolished and the process is made as common as possible with the logic unit.

Therefore, a so-called gain cell, which has a plurality of transistors for writing and reading, and amplifies stored data by a reading transistor and outputs the amplified data to a bit line, is attracting attention again. As gain cells, for example, a three-transistor type having two read transistors and one write transistor, and a two-transistor-one-capacitor type having write and read transistors and a boosting capacitor at a storage node are known.

Of the conventional DRAM gain cells, 2
FIG. 11 shows a circuit diagram of the transistor-1 capacitor type cell. This conventional DRAM gain cell 100 includes a write transistor TW, a read transistor TR, and a capacitor CAP. The write transistor TW has a gate connected to the write word line WWL and one of a source and a drain connected to the write bit line WBL.
It is connected to the. Read transistor TR has a gate connected to the source of the write transistor TW, the other of the drain, a source connected to the read bit line RBL, the drain is connected to the supply line VDD of the power supply voltage V _DD. The capacitor CAP has one electrode connected to the connection point between the read transistor TR and the write transistor TW, and the other electrode connected to the read word line RWL. One electrode of the capacitor CAP and a connection middle point between the read transistor TR and the write transistor TW connected thereto are connected to the memory cell M
A storage node SN of C.

In this memory cell 100, storage node S
The bias value of the gate electrode of the read transistor TR is changed by changing the charge accumulation amount of N. For example, the charge accumulation amount of the storage node SN is zero, or
The state that is so small that the read transistor TR is not turned on under the predetermined bias condition at the time of reading is made to correspond to the storage data “0”, and the state where charge is accumulated as the read transistor TR is turned on is changed to the storage data “1” Make it correspond.

At the time of writing, a write word line WWL
To turn on the write transistor TW,
The charge storage amount of the storage node SN is changed according to the set potential of the write bit line WBL.

At the time of reading, storage data "1"
In the case of, the charge accumulation amount of the storage node SN is relatively large, so that the read transistor TR is turned on, charge is supplied from the supply line of the power supply voltage V _DD to the read bit line RBL, and the potential thereof increases. On the other hand, in the case of the storage data “0”, since the charge storage amount of the storage node SN is zero or relatively small, the read transistor TR remains off, and the voltage of the bit line RBL maintains the initial state (precharge voltage). . A change in the potential of the read bit line RBL according to the stored data is detected by a sense amplifier (not shown) and determined as stored data.

As described above, the charge accumulation of the capacitor CAP may be such that the ON / OFF of the read transistor TR can be controlled in accordance with the stored data. That is, in this memory cell, unlike the one-transistor one-capacitor type DRAM cell, it is not necessary to directly charge and discharge a large-capacity bit line with the stored charge of the capacitor, so that the charge storage capacity of the capacitor is small. As a result, in the memory cell having this structure, it is not necessary to improve the charge storage amount per unit area by devising a capacitor structure, and it is not necessary to develop a capacitor dielectric material having a high dielectric constant. In addition, since the structure is not complicated, it is easy to manufacture, and there is an advantage that the process can be easily shared, such as forming a capacitor electrode collectively with the logic wiring layer, and the manufacturing cost can be reduced accordingly.

[0011]

However, when a memory cell array using such a conventional DRAM gain cell is integrated together with a logic circuit in one chip, the required transistor threshold voltage differs between the memory section and the logic section. That is a problem.

In the logic section, in order to satisfy the demand for higher speed and lower voltage, which is becoming more severe year by year, there is a tendency that the transistor threshold voltage is reduced and used so that the drive current can be increased even at low voltage.

On the other hand, in the memory section, among the transistors constituting the DRAM gain cell, the read transistor, when the read and write word lines are in the low-level charge holding period, when the storage amount of the storage node is small, and the charge is low. It must be turned off both at the time of storing “1” with a large holding amount. Therefore, the gate threshold voltage of the read transistor needs to be set higher than the storage node potential when "1" is stored. If this voltage relationship is not satisfied, the read transistor is turned on even during a time other than the read operation, which may cause malfunctions such as destruction of latch data on the bit line. Also, if the threshold voltage of the read transistor is lowered while satisfying this voltage relationship, the difference in the amount of charge of the storage node according to the logical value of the data is reduced, the operation margin is reduced, and the device is susceptible to noise. It becomes a factor.

For this reason, in the conventional logic LSI with embedded memory, it is necessary to provide a transistor threshold voltage difference between the logic section and the memory section in advance. For this reason,
Conventionally, a process for adjusting the threshold voltage by selectively ion-implanting at least one side during manufacturing is additionally required, and there is a disadvantage that a cost increase cannot be avoided.

An object of the present invention is to provide a semiconductor memory device, such as a DRAM gain cell, in which data is stored depending on the magnitude of the gate potential of a read transistor, having a structure in which the gate threshold voltage of the read transistor can be adjusted without increasing a special process. It is to provide a storage device.

[0016]

A semiconductor memory device according to the present invention has a storage node for holding data as a potential change, a gate connected to the storage node, and one of a source and a drain connected to a bit line. A read transistor that is turned on or off in accordance with the potential of the storage node and reads the stored data to the bit line, wherein a gate electrode of the read transistor is formed using a semiconductor material having a conductivity type opposite to that of a channel. Become.

The present invention is widely applicable to 2-transistor-1-capacitor type cells, 3-transistor type cells and the like. For example, in the case of having a two-transistor-one-capacitor cell, the data is stored between the storage node and the bit line or another bit line according to a voltage applied to a write word line connected to a gate. The semiconductor device further includes a write transistor that controls writing to the node, and a capacitor that is connected between the storage node and the read word line and that changes a storage node potential at the time of reading.

The read transistor may be an n-channel insulated gate field effect transistor having a gate electrode containing p-type polysilicon or a p-channel insulated gate field effect transistor having a gate electrode containing n-type polysilicon. either will do.

When the channel conductivity type of the read transistor is n-type, the threshold voltage is set as a charge holding condition according to the logic of the data when the write word line and the read word line are low. The potential is set higher than the potential of the storage node having a different value. In addition, as a normal read operation condition in this case, the threshold voltage of the read transistor is increased by capacitive coupling according to the high-level potential of the storage node and the voltage applied to the read word line at the time of reading. Less than the sum of the potential rise of
In addition, it is set to a value larger than the sum of the low-level potential of the storage node and the potential rise of the storage node. The channel conductivity type of this read transistor is n
In the case of the type, when the charge holding condition and the normal read operation condition are summarized, the threshold voltage is determined by capacitive coupling according to the high-level potential of the storage node and the voltage applied to the read word line at the time of read. The value is set to be smaller than the added value of the rising potential of the storage node and larger than the larger of the high-level potential of the storage node and the potential rise of the storage node.

Preferably, a sense amplifier having a latch function is connected to the bit line.

In another semiconductor device according to the present invention, a storage node for holding data as a potential change, a gate connected to the storage node, one of a source and a drain connected to a bit line, and a potential of the storage node A memory section including a memory cell array in which a plurality of memory cells each having a read transistor that is turned on or off according to the above and reads the storage data to the bit line, a p-channel insulated gate field-effect transistor, and an n-channel insulated gate A CMOS transistor circuit portion including a field effect transistor, and a gate electrode of the read transistor is made of a semiconductor material having a conductivity type opposite to a conductivity type of a channel.

In an operation in which a memory cell array is configured by arranging memory cells having such a configuration in a matrix, when rewriting, first, reading is performed before a writing operation, and original data is latched in a sense amplifier. Keep it.
In reading when both the write and read transistors are of the n-channel type, for example, after discharging a bit line, a high level potential is set to the read word line while the potential of the write word line is low. The storage node potential increases due to the capacitive coupling of the capacitor, and the read transistor is turned on or off according to storage data (initial potential of the storage node). Thereby, a potential difference is generated in the bit line according to the stored data. This potential difference is amplified and latched by the sense amplifier. In writing, first, new data is set only on the bit line connected to the cell to be rewritten (selected cell). Thereafter, the write word line potential is changed from low level to high level while the read word line potential is at low level.
As a result, the new data is written in the selected cell, and the original data is rewritten in the other unselected cells.

Normally, an insulated gate field effect transistor is of the n-channel type because of the surface channel type.
A p-type gate electrode is used for the p-channel type. On the other hand, in the semiconductor memory device according to the present invention, an impurity having a conductivity type opposite to that of the channel is introduced into the gate electrode of the read transistor. Therefore, the work function difference between the p-type semiconductor region where the channel is formed and the p-type gate electrode material (or between the n-type semiconductor region where the channel is formed and the n-type gate electrode material) increases. As a result, a higher threshold voltage is realized as compared with an insulated gate field effect transistor generally used in a logic section or the like. The introduction of different impurities into the gate electrode
Since the MOS transistor circuit section is commonly used, when a CMOS transistor circuit section is built in the semiconductor device, an additional step does not occur by applying the present invention.

[0024]

FIG. 1 is a block diagram showing a main part of a memory cell array and its peripheral circuits of a semiconductor memory device according to an embodiment of the present invention. This semiconductor storage device 1
In the memory cell array, m × n (m, n:
(Arbitrary natural numbers) of memory cells (DRAM gain cells) are arranged in a matrix. Further, one reference cell RC, one sense amplifier SA, one discharge circuit DCH, and one column selection circuit are provided for each column.

FIGS. 2 to 4 show DRA to which the present invention can be applied.
FIG. 3 is a circuit diagram illustrating a configuration example of an M gain cell. FIG.
FIG. 2 is a circuit diagram showing a main configuration of each column in FIG. 1. As shown in FIG. 5, a DRAM gene cell MCij (i = 1 to m,
j = 1 to n; hereinafter simply referred to as MC) is the bit line BL
, The reference cell RC is connected to a bit complementary line BL_ paired with the bit line BL, and the sense amplifier SA, the discharge circuit DCH, and the column selection circuit are connected to both the bit line BL and the bit complementary line BL_. .

The DRAM gene cell MC shown in FIG. 2 is a two-transistor-one-capacitor type, and includes a write transistor TW, a read transistor TR, and a capacitor CAP. The write transistor TW is
The gate is connected to the write word line WWL, and the source,
One of the drains is connected to the bit line BL. Read transistor TR has a gate connected to the source of the write transistor TW, the other of the drain, a source connected to bit line BL, and a drain connected to the supply line VDD of the power supply voltage V _DD. The capacitor CAP has one electrode connected to the connection point between the read transistor TR and the write transistor TW, and the other electrode connected to the read word line RWL. This capacitor CAP
And the connection midpoint between the read transistor TR and the write transistor TW connected thereto is
It forms the storage node SN of the memory cell MC.

In response, reference cell R in FIG.
C includes a reference write transistor RTW, a reference read transistor RTR, and a reference capacitor RCAP. The reference write transistor RTW has a gate connected to the reference write word line RWWL, and one of a source and a drain connected to the bit auxiliary line BL_. Referring read transistor RTR, the gate is connected to a source of reference write transistor RTW, the other of the drain, a source connected to the complementary bit line BL_, and the drain is connected to the supply line VDD of the power supply voltage V _DD. One electrode of the reference capacitor RCAP has a reference read transistor RTR and a reference write transistor RT.
The other electrode is connected to the reference read word line RRWL. This reference capacitor R
One electrode of the CAP and the reference read transistor RTR and the reference write transistor R connected thereto.
The midpoint of the connection of the TW forms a storage node RSN of the reference voltage in the reference cell MC.

The DRAM cell MC shown in FIG. 3 is of a three-transistor type, and includes a write transistor TW and a first transistor TW.
It comprises a read transistor TR1 and a second read transistor RT2. Write transistor T
W has a gate connected to the write word line WWL, and one of a source and a drain connected to the bit line BL. The first read transistor TR1 has a gate connected to the read word line RWL and a drain connected to the bit line B.
L and the source is the second read transistor RT
2 drain. The second read transistor TR2 has a gate connected to the other of the source and the drain of the write transistor TW, a drain connected to the source of the first read transistor TR1, and a source connected to a common potential line (for example, a ground line). . Second
A connection midpoint between the gate of the read transistor TR2 and the write transistor TW forms a storage node SN of the memory cell MC.

In the DRAM gain cell MC shown in FIG.
In addition to the bit line (write bit line WBL) to which the write transistor TW is connected, the read bit line RBL
And the drain of the first read transistor TR1 is connected to the read bit line RBL. Other configurations are the same as those in FIG.

The sense amplifier SA, as shown in FIG.
pMOS transistor PS1 and nMOS transistor N
A CMOS inverter constituted by S1 and p
MOS transistor PS2 and nMOS transistor NS
2 and a CMOS inverter. As shown, the sense amplifier SA is a latch circuit in which input terminals and output terminals of these inverters are connected to cross each other.

In the sense amplifier SA, the sources of the pMOS transistors PS1 and PS2 are both connected to the positive drive voltage supply line SPL, and the nMOS transistor NS
1 and NS2 are both supply lines SN of the negative drive voltage.
L. pMOS transistors PS1 and n
Each drain of MOS transistor NS1 and pMO
Each gate of the S transistor PS2 and the nMOS transistor NS2 is connected to the bit line BL. Similarly, p
MOS transistor PS2 and nMOS transistor NS
2 and the gates of the pMOS transistor PS1 and the nMOS transistor NS1
L_.

The discharge circuit DCH comprises transistors Q1, Q2, Q3. The transistor Q1 is an nMOS transistor for potential equalization (equalizing), and is connected between the bit line BL and the bit auxiliary line BL_. Transistors Q2 and Q3
Is an nMOS transistor for ground potential connection (grounding), which is connected in series between the bit line BL and the bit auxiliary line BL_, and whose connection midpoint is connected to the supply line (ground line) of the ground potential GND. ing. Transistor Q1,
Q2 and Q3 are both connected to a supply line for the discharge control signal EQ.

The column selecting circuit is connected between the bit line BL and the data input / output line I / O, and is connected between the bit auxiliary line BL_ and the data input / output auxiliary line I / O_. And a transistor Q5. Both transistors Q4 and Q5 are composed of, for example, nMOS transistors and have their gates connected to each other and input to a column decoder (not shown).

Two transistors according to the embodiment of the present invention
FIG. 6 shows an example of a plane pattern of a one-capacitor memory cell MC.
Shown in FIG. 7 is a schematic sectional view taken along line AA of FIG. FIG. 6A shows the state after the formation of the second wiring layer.
(B) shows the state after completion, and the manufacturing of the memory cell will be described with reference to these drawings.

First, a p-type well (p
A well 2 is formed, and an element isolation insulating layer is formed on the surface in a predetermined pattern. Next, a gate insulating film 3 made of, for example, silicon oxide and a first wiring layer made of polysilicon are sequentially formed. By ion implantation after the formation of the polysilicon, p-type impurities and n-type impurities are separately applied to the polysilicon. In this example, at least the polysilicon region serving as the gate electrode of the read transistor TR is a p-type. A laminated film of a silicon oxide film 4 and a silicon nitride film 5 is deposited on the polysilicon, and the polysilicon and the gate insulating film 3 are patterned together with the laminated films 4 and 5. As a result, as shown in FIG.
A write word line WWL orthogonal to the well 2 and penetrating between cells in the word line direction (horizontal direction in the drawing), and a p-type first local interconnect layer 20 orthogonal to the p well 2 and locally provided in the cell
Are formed.

A side wall insulating layer 6 is formed on the side wall of the first wiring layer. An n-type impurity region 21 having an LDD structure is formed by introducing an n-type impurity at a low concentration initially and a high concentration after the sidewall insulating layer 6 is formed on the surface of the p-well 2 around it. The n-type impurity region 21 has, as a supply line VDD for the power supply voltage V _DD , a wiring portion penetrating between cells in the word line direction and shared between two cells adjacent in the bit line direction (vertical direction in the drawing). A read transistor TR is formed in the p-well surface region in a portion orthogonal to the first local interconnect layer 20 immediately beside this interconnect portion (power supply voltage supply line VDD). Further, a write transistor TW is formed in a portion of the p-well surface orthogonal to the write word line WWL.

A first interlayer insulating film is formed, the first interlayer insulating film is patterned, and contact holes 22 and 23 opened on n-type impurity region 21 and contacts opened on first local wiring layer 20 are formed. The holes 24 are formed at the same time. Of these, the contact hole 22 opened on the n-type impurity region 21 immediately beside the read transistor TR becomes a part of the bit contact BC. A second local wiring layer 25 and a pad layer 26 are formed on the first interlayer insulating film. Second local wiring layer 2
Reference numeral 5 denotes a connection between the contact holes 23 and 24, and a pad layer 26.
Are overlapped on the contact holes 22.

A second interlayer insulating film is formed, and the second interlayer insulating film is patterned, as shown in FIG.
Via holes 27 and 28 are formed. First via hole 27
Are opened on the pad layer 26 and become a part of the bit contact BC. The first via hole 28 is formed in the second local wiring layer 25.
Open up. The first via hole 2 is formed on the second interlayer insulating film.
7 and a pad layer 29 in contact with the first via hole 28 are formed simultaneously.

A third interlayer insulating film is formed, and the third interlayer insulating film is patterned to form a second via hole 30 on the pad layer 29. A rectangular capacitor lower electrode layer 31 connected to the second via hole 30 on the third interlayer insulating film
To form After forming the capacitor dielectric film, a capacitor upper electrode layer 32 is formed on the capacitor dielectric film so as to penetrate between cells in the word line direction.

In this example of the cell structure, the transistors TR,
Both TWs are bulk type and have excellent transistor characteristics and uniformity.
There is an advantage that compatibility with the MOS transistor process is good.

In the formation of this cell structure, a step of forming a resist and implanting ions are required to make the gate electrode 20 of the read transistor TR p-type.
However, the implantation of the impurity of the different conductivity type into the gate electrode is performed by another circuit formed simultaneously, for example, the CMO of FIG.
This is necessary for forming the S sense amplifier circuit SA.
There is no increase in the number of steps in the whole manufacturing of the semiconductor device.

Next, the operation of the circuit shown in FIG. 5 will be described with reference to the timing chart of FIG. Before the data latch in FIG. 8, the bit line BL is held at the ground potential GND by the discharge circuit DCH. When the control signal EQ changes from low level to high level, the transistor Q
1 turns on to electrically connect the bit line BL and the supplementary bit line BL_, and the transistors Q2 and Q3 turn on to connect both the bit line BL and the supplementary bit line BL_ to the ground line. As a result, the ground potential 0 V is set in the bit line BL and the bit auxiliary line BL_ in a short time.
Further, during this discharge period, the reference write word line RWWL is activated, and the reference write transistor R
TW turns on. Therefore, the electric charge of the storage node RSN of the reference cell RC is released to the bit auxiliary line BL_, and the potential of the storage node RSN is initialized to the ground potential 0V.

The data latch is an operation in which the written storage data is read out to the bit line BL and latched by the sense amplifier SA. At the time of this read, as shown in FIG. 8A, a high-level read voltage (for example,
The power supply voltage V _DD ) is applied. Thereby, in all the memory cells MC connected to the same word line in FIG.
Read transistor TR according to storage node SN potential Vsn, that is, the gate potential of read transistor TR
Turns on or off. For example, only when data "1" is held, the read transistor TR is turned on, and the bit line BL is charged by the power supply voltage _VDD . In the case of holding “0” data, the potential of the bit line BL does not change while the read transistor TR remains off.

Next, writing is performed. At the time of writing, as shown in FIG.
Is changed from a high level to a low level, and FIG.
As shown in (C), the new data to be written is
Set to L. In other words, only the bit line BL to which the selected cell is connected is selected by the column decoder, and the new data held in the write latch circuit (not shown) is forcibly set to the selected bit line BL. Subsequently, as shown in FIG. 8B, the write word line WWL is set from low level to high level, and the data latched on the bit line BL is simultaneously transmitted to all cells in the same row as the selected cell. Write. As a result, the original data is rewritten in the non-selected cells, and the selected cells are rewritten with the new data. After that, the write word line WWL is returned to the low level.

Reading is performed in the same manner as the data latch.
By setting the read word line RWL to high level, data in the storage node is read to the bit line BL. At this time, a high-level voltage is set to the reference read word line RRWL simultaneously with the activation of the read word line RWL. The reference cell RC has a capacitance value of the reference capacitor RCAP and a reference read transistor RT
In accordance with the set value of the gate capacitance of R, the potential rise width due to the activation of the reference read word line RRWL is designed in advance so as to be half that on the memory cell side. Therefore, the potential of the bit auxiliary line BL_ maintains the bit line B while maintaining the intermediate value of the variation width according to the data held in the bit line BL.
It rises with L.

At a stage where the potential change of the bit line BL corresponding to the held data has occurred to some extent, the sense amplifier SA is activated. That is, the positive drive voltage SPL is a positive voltage,
For example, it becomes the power supply voltage V _DD , followed by the negative drive voltage SN
L changes to, for example, ground potential 0V. As a result, the potential difference of the bit line BL is rapidly opened to the full amplitude of the power supply voltage V _DD , and the signal is amplified, using the intermediate voltage of the bit auxiliary line BL_ as the reference voltage. As for the data read by the sense amplifier SA, only the data selected by the column decoder is sent to the data input / output line I / O by turning on the transistor Q4, and is output to the outside.

Since the sense amplifier SA is constituted by a latch circuit, it is possible to subsequently perform a write-back (refresh). That is, transistors Q4 and Q5
Is turned off, the read word line RWL is set to the low level, and then the write word line WWL is set to the high level, as shown in FIGS. 8A and 8B. Then, the signal amplified by the sense amplifier SA and latched on the bit line BL is directly rewritten as write data to the storage node SN via the ON-state write transistor TW.

The above-mentioned reading is basically non-destructive data reading. That is, although the charge of the storage node SN is induced by the capacitor and increases, the write transistor TW is turned off during the read period, and the read transistor TR is an insulated gate type. Therefore, the charge is lost due to the off-leak current of the write transistor TW. Lord. Therefore, it is not necessary to perform the refresh every time the data is read out, and it suffices to perform the refresh periodically every relatively long time.

Next, conditions of the transistor threshold voltage for normal operation in the cell of FIG. 2 will be presented. Now
The threshold voltage of the write transistor TW is denoted by VthW, and the threshold voltage of the read transistor TR is denoted by VthR. When a predetermined applied voltage is applied at the time of writing, the potential of each common line is such that the potential of the write word line WWL is VWWL,
The potential of the read word line is 0 V, the potential of the bit line BL when "0" is written is VBL0, the potential of the bit line BL when "1" is written is VBL1 (> VBL0), and the power supply voltage supply line V
It is assumed that the potential of _DD is _VDD .

At the time of writing, VBL0 or VBL1 is set to the bit line BL according to the logic of the write data. The write transistor TW is turned on with the potential of the read word line RWL set to 0V. In the case of writing “0” data, since the bit line BL potential is preset to a low voltage level VBL0, when the write transistor TW is turned on, charges are drawn from the storage node SN, and the potential Vsn ( 0) is VBL0
become.

On the other hand, in the case of writing "1" data, since the bit line BL potential is preset to VBL1 of a high voltage level, when the write transistor TW is turned on, charge is supplied to the storage node SN. In this case, the potential Vsn (1) of the storage node SN is equal to the so-called “Vt of the nMOS transistor in the write transistor TW.
As a result, the potential of the smaller of VBL1 and (VWWL-VthW), that is, Vsn (1) = MIN (VBL1, VWW
L−VthW).

As described above, the storage node SN after writing is performed.
Is determined by the bit line potential, the gate applied voltage of the write transistor TW, and the threshold voltage according to the write data set on the bit line BL.

[0053] At the time of data holding after writing both 0V to the write word line WWL and the read word line RWL, the potential of the power supply voltage supply line VDD and to V _DD, the potential of the bit line BL is set to an arbitrary value And At this time, the read transistor TR needs to be turned off at the potential 0 V of the read word line RWL. For this reason,
The condition for holding data is that the threshold voltage VthR of the read transistor TR satisfies the following equation (1).

[0054]

Vsn (0) <Vsn (1) <VthR (1)

On the other hand, with respect to the potential of each common line at the time of reading, the potential of the write word line WWL and the precharge potential of the bit line BL are both 0 V, the potential of the read word line RWL is VRWL, and the potential of the power supply voltage supply line VDD. Is set to V _DD .

That is, first, the bit line BL is precharged to a state of 0V in advance. Further, in order to keep the write transistor TW off, the potential of the write word line WWL is set to 0V. After that, the read word line RW
A predetermined voltage is applied to L, and the potential is set to VRWL. Thus, the potential of storage node SN capacitively coupled to read word line RWL via capacitor CAP rises. The final value of the rise in the potential of the storage node SN depends on the potential Vsn (0) or Vsn (1) of the storage node SN at the time of data retention, and this determines whether the read transistor TR is on or off. That is, when the held data is “0”, the read transistor TR remains off, and when the held data is “1”, the read transistor TR shifts from the off state to the on state. As a result, when the held data is “1”, charges are supplied from the power supply voltage supply line VDD and the potential of the bit line BL increases, while
When the held data is “0”, the current flows only about the off-leak current of the transistor, so that the potential of the bit line BL hardly changes. Thus, storage node SN
Can be converted into a potential change of the bit line BL and read.

In order for the above read operation to be performed, the threshold voltage VthR of the read transistor TR must be
The value must be larger than the final value of the potential rise of the storage node SN when “0” data is retained and smaller than the final value of the potential rise of the storage node SN when retaining “1” data. That is, the threshold voltage of the read transistor TR needs to satisfy the following expression (2).

[0058]

(Equation 2)

Here, the capacitance of the capacitor CAP is represented by C1,
When the gate capacitance of the read transistor TR is C2, α is a predetermined constant given by C1 / (C1 + C2). The following equation (3) is obtained from the above equations (1) and (2).

[0060]

Vsn (0) <MAX (Vsn (1), αVRWL) <VthR <Vsn (1) + αVRWL (3)

Assume that the capacitor CAP and the read transistor TR are formed so as to satisfy αVRWL = Vsn (1). At this time, the above equation (3) is simplified to the following equation (3) ′.

[0062]

[Formula 4] αVRWL <VthR <2αVRWL (3) '

In the case of equation (3) ′, the difference between the gate voltage when the read transistor TR is on and when it is off, that is, the gate voltage difference between data “1” and data “0” is αV
RWL. As the cell size is reduced, the capacitance of the capacitor CAP is limited, and α generally tends to decrease. In addition, it is desirable to reduce VRWL from the demand for reduction of the power supply voltage.
However, when αVRWL decreases for such a reason,
As is apparent from the above equation (3) ′, the voltage margin of the normal read operation is reduced, and the read operation is susceptible to noise. Therefore, αVRWL has a certain lower limit, and as a result, the threshold voltage VthR of the read transistor TR cannot be reduced too much.

On the other hand, in a logic circuit, there is a tendency that the transistor threshold value is lowered in order to secure a drive current and operate at high speed even if the voltage is lowered. For this reason, in an LSI in which the above-described DRAM gain cell is mixed with a logic circuit, necessary transistor threshold voltages in the memory section and the logic section are different. That is, it is necessary to make the threshold voltage VthR of the read transistor TR in the memory cell higher than the threshold voltages of the other transistors.

In the present embodiment, at least the read transistor TR has a gate electrode conductivity type opposite to that of the channel, and a large work function difference between the two to set a large threshold voltage. Moreover, no additional steps are required to provide this threshold voltage difference. VBL0 =
If the transistor threshold voltages VthW and VthR satisfying the above equation (3) can be set as 0V, VBL1 = VWWL = VRWL = _VDD , the memory cell MC operates without using the power supply voltage _VDD and the ground potential of 0V. It is possible to do. Therefore, in this case, it is not necessary to generate another internal power supply voltage in the peripheral circuit or to form a special transistor for high voltage. That is, from the viewpoint of power supply or from the viewpoint of a process that does not require a high-withstand-voltage transistor, the memory manufacturing process has better consistency with the logic manufacturing process. Although the capacitor CAP is provided, since the shape is a parallel plate type using a wiring layer as an electrode, compatibility with the logic manufacturing process is also high in this regard. As described above, the memory-logic hybrid IC can be easily realized at low cost.

In this embodiment, various changes are possible. In the present embodiment, the read transistor TR
Although the gate electrode of (or TR1) is p-type, the gate electrode of the write transistor TW or another read transistor TR2 can be p-type if necessary.

In FIG. 2, the read transistor TR is connected between the bit line BL and the power supply voltage line VDD. This is because the data read out to the bit line BL can be latched and used as data at the time of refreshing or unselected cell data at the time of rewriting without directly inverting the logic. Therefore, when a function of forcibly inverting latch data is provided, the read transistor TR may be connected to the ground line instead of the power supply voltage common line VDD. Conversely, in FIGS. 3 and 4, the second read transistor TR2 may be connected to the supply line of the power supply voltage V _DD .

As shown in FIG. 9, the channel conductivity type of the read transistor TR and the write transistor may be p-type. In this case, as shown in FIG. 10, at least the gate electrode 41 of the read transistor TR is of an n-type. In addition, from the viewpoint that the logical inversion of the latch data is not required, it is desirable that the read transistor TR be connected to the ground line. In this case, a precharge circuit that sets the bit line BL and the bit auxiliary line BL_ to a high-level voltage is provided instead of the discharge circuit DCH in FIG. The precharge circuit connects, for example, the ground line of discharge circuit DCH in FIG.
It is configured by replacing with the _DD supply line VDD. With the transistor being a pMOS, if the high level and the low level of the signal level are all reversed, the above operation description can be applied as it is.

Further, one of the channel conductivity types of the read transistor TR and the write transistor TW is p
And the other may be n-type. Also in this case, at least the gate electrode of the read transistor TR
The conductivity type is reversed from the channel conductivity type.

The operation is not limited to the mode described above. For example, there is an operation mode in which the potential of the read word line RWL is set to a high level at the time of writing, the potential of the read word line RWL is set at a low level at the time of reading, and the potential drops by αVRWL. In this mode, normal data reading can be performed on the condition that the potential after falling has an intermediate value between the initial storage node potentials Vsn (0) and Vsn (1).

[0071]

According to the semiconductor memory device of the present invention,
At least the threshold voltage is increased by inverting the conductivity type of the gate electrode of the read transistor to that of the channel. For this reason, the threshold voltage of another write transistor or a transistor included in a logic circuit, a sense amplifier circuit, or the like is lowered to perform high-speed operation, while at the same time, preventing a reduction in an operation margin of a memory cell and preventing malfunction. I'm preventing. Therefore, the memory section having this memory cell is suitable for being mixed with a circuit that requires low voltage and high speed operation. Further, for example, when the logic circuit, the sense amplifier circuit and the like are originally CMOS transistor circuits,
The conversion of some of the gate electrodes to the reverse conductivity type does not involve an additional step and does not cause a cost increase. As described above, according to the present invention, it is easy to realize a system IC with a simple manufacturing process, low cost, and high operation reliability.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a memory cell array and its peripheral circuits of a semiconductor memory device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration example 1 of a DRAM gain cell to which the present invention can be applied;

FIG. 3 is a circuit diagram showing a configuration example 2 of a DRAM gain cell to which the present invention can be applied;

FIG. 4 is a circuit diagram showing a configuration example 3 of a DRAM gain cell to which the present invention can be applied;

FIG. 5 is a circuit diagram showing a configuration of a main part (for one column of cells) of a memory cell array according to an embodiment of the present invention.

FIG. 6 is a plan view showing the structure of a DRAM gain cell of Configuration Example 1.

FIG. 7 is a cross-sectional view illustrating a structure of a read transistor.

FIG. 8 is a timing chart showing signal waveforms at a read word line, a write word line, a bit line, and a storage node during operation of the DRAM gain cell according to the embodiment of the present invention.

FIG. 9 is a circuit diagram showing a modification example of the DRAM gain cell according to the embodiment of the present invention, taking Configuration Example 1 as an example.

FIG. 10 is a cross-sectional view of a read transistor in a modification of FIG.

FIG. 11 shows a conventional two-transistor-one-capacitor DR.
It is a circuit diagram of an AM cell.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2, 40 ... Well, 3 ... Gate insulating film, 4 ... Silicon oxide film, 5 ... Silicon nitride film, 6 ... Side wall insulating layer, 20, 41 ... First wiring layer (gate electrode), 21 42, impurity region, 22-24 contact hole, 25, 26 second wiring layer, 27, 28 first via hole, 29 third wiring layer, 30 second via hole,
31: fourth wiring layer, 32: fifth wiring layer, MC: DRAM
Gain cell (memory cell), RC: reference cell, SA: sense amplifier, DCH: discharge circuit, TW: write transistor, TR, TR1, TR2: read transistor, CAP: capacitor, WWL: write word line, RWL: read word line , BL ... bit line,
BL_: bit supplementary line, RBL: read bit line, BC
... Bit contact, VDD ... Power supply voltage supply line, SN
... a storage node.

Claims (9)

[Claims] A storage node for holding data as a potential change, a gate connected to the storage node, one of a source and a drain connected to a bit line, and turned on or off according to the potential of the storage node. And a read transistor for reading stored data to the bit line, wherein a gate electrode of the read transistor is made of a semiconductor material having a conductivity type opposite to a conductivity type of a channel. 2. A write circuit connected between the storage node and the bit line or another bit line, and for controlling writing of the data to the storage node in accordance with a voltage applied to a write word line connected to a gate. A transistor, connected between the storage node and a read word line;
2. The semiconductor device according to claim 1, further comprising: a capacitor that changes a storage node potential at the time of reading. 3. The semiconductor device according to claim 1, wherein said readout transistor is an n-channel insulated gate field effect transistor including a gate electrode containing p-type polysilicon. 4. The semiconductor device according to claim 1, wherein said readout transistor is a p-channel insulated gate field effect transistor including a gate electrode containing n-type polysilicon. 5. When the read transistor has an n-type channel conductivity, the threshold value is different according to the logic of the data when the write word line and the read word line take a low level. 3. The semiconductor device according to claim 2, wherein the potential is set higher than the potential of said storage node. 6. When the channel conductivity type of the read transistor is n-type, the threshold value is determined by a high level potential of the storage node and a capacitive coupling according to a voltage applied to the read word line at the time of reading. 3. The value is set to a value that is smaller than an added value of the potential rise of the storage node and that is larger than the added value of the low-level potential of the storage node and the potential rise of the storage node. 13. The semiconductor device according to claim 1. 7. If the channel conductivity type of the read transistor is n-type, the threshold value thereof is determined by a high level potential of the storage node and a capacitive coupling according to a voltage applied to the read word line at the time of reading. The value is set to a value smaller than an added value of an increase in the potential of the storage node and an electric potential higher than a larger one of the high-level potential of the storage node and the increase in the potential of the storage node. 3. The semiconductor device according to 2. 8. The semiconductor device according to claim 1, wherein a sense amplifier having a latch function is connected to said bit line. 9. A storage node for holding data as a potential change, a gate connected to the storage node, one of a source and a drain connected to a bit line, and turned on or off according to the potential of the storage node. A memory section including a memory cell array in which a plurality of memory cells each including a read transistor for reading stored data to the bit line are arranged; a CMO including a p-channel insulated gate field-effect transistor and an n-channel insulated gate field-effect transistor
And a gate electrode of the read transistor is made of a semiconductor material having a conductivity type opposite to a conductivity type of a channel.