JPH05128857A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To reduce the power consumption at the time of data writing and to make fast the data writing by providing a writing amplifying circuit to limit the amplitude level of an I/O line and a sense amplifying circuit to operate in response to a control signal. CONSTITUTION:At the time of data writing to a memory cell, a writing amplifying circuit W/Ai amplifies input data Di, and outputs them to complementary data lines (I/O line) DBi and DBXi. Then, the level of the data line is limited to voltage levels (Vcc-Vth and Vss+Vth) smaller than the voltage of the power line. As the result, the charging discharging current of the I/O line can be reduced and the power consumption at the time of the data writing can be reduced. By timing (operation of a control signal WC) of the data writing starting and synchronizing to a column selecting signal CL and stopping and restarting the action of a sense amplifying circuit S/Ai, the delaying of the writing time is limited. Then, the data writing can be made fast.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a technique for improving the performance of data writing in a dynamic random access memory (DRAM). In recent DRAMs, high-speed operation and low power consumption have been demanded, and simultaneous writing and reading of a plurality of bits have been demanded with the increase in memory capacity. Therefore, it is necessary to prepare a large number of data lines, that is, input / output (I / O) lines, and read and write data via these I / O lines.

[0002]

2. Description of the Related Art In a conventionally known DRAM I / O circuit, the level of the I / O line is maximized between the levels of the power supply voltages Vcc and Vss in both data writing and data reading. Amplitude (that is, full swing) is carried out to the limit, and information is transmitted by it.

However, when the memory is operated in a high-speed cycle such as a high-speed page mode, the charge / discharge current of the I / O line occupies most of the power consumption of the device.
Some kind of countermeasure is required. To deal with this, in a typical conventional DRAM, a current mirror type amplifier circuit is used at the time of reading, or the I / O line and the amplifier circuit are separated when amplifying the information of the I / O line. By doing so, the level of the I / O line itself is not amplified.

However, at the time of data writing, the levels of the I / O lines (complementary data lines DB, DBX) are still oscillated between the levels of the power supply voltages Vcc and Vss as shown in the waveform diagram of FIG. , Which has been an obstacle to reducing power consumption. This tendency is especially due to the I / O accompanying the recent increase in capacity.
It is getting bigger and bigger with the increase of O line.

[0005]

As described above, in the conventional DRAM, when writing data, the level of the I / O line is maximized to the level of the power supply voltage (full swing).
Therefore, there is a problem that it is not possible to promote low power consumption of the device. When writing data, I
There is also a drawback that the data writing time becomes relatively long due to the full swing of the / O line level. Therefore, there is a disadvantage that it is not possible to meet the multi-bitization (simultaneous writing / reading of a plurality of bits) which has been required in recent years.

The present invention was created in view of the above problems in the prior art, and an object of the present invention is to provide a semiconductor memory device capable of reducing power consumption at the time of writing data and performing the data writing at high speed. I am trying.

[0007]

In order to solve the above-mentioned problems, a semiconductor memory device of the present invention has a complementary data line for transmitting read data or write data and a complementary bit line for transmitting data read from a memory cell. Line, a sense amplifier circuit connected to the complementary bit line and operating in response to a control signal, a transfer gate connecting the complementary bit line to the complementary data line when the memory cell is selected, and a power supply line A write amplifier circuit for amplifying input data from the outside and outputting the amplified data to the complementary data line, wherein the write amplifier circuit sets the level of the complementary data line to the above-mentioned level when writing data to the memory cell. The voltage is reduced to a voltage level lower than the voltage of the power supply line, and the sense amplifier circuit sets a predetermined logic level of the control signal. It is characterized by stopping the further operation.

[0008]

According to the above configuration, when writing data,
Since the amount of change (that is, the amplitude) of the level of the complementary data line for writing, that is, the I / O line is limited by the write amplifier circuit, the charging / discharging current of the I / O line can be reduced, and consequently the data writing Power consumption can be reduced.

Further, during the data writing period, the operation of the sense amplifier circuit corresponding to the cell to be written (that is, the selected memory cell) is stopped, so that the amplitude limitation of the I / O line level at the time of writing causes a limitation. The writing time delay is suppressed. This contributes to speeding up data writing. Details of other structural features and operations of the present invention will be described using embodiments described below with reference to the accompanying drawings.

[0010]

FIG. 1 shows the structure of a DRAM as an embodiment of the present invention. In the figure, 1 is a dynamic memory cell array having a capacity of 4M, 2 is a clock generator which generates a first clock in response to an active low row address strobe signal RASX and a column address strobe signal CASX, respectively. Is the inverted signal of the column address strobe signal CASX and the first signal
AND gate responsive to the output of the AND gate, 4 is a clock generator for generating a second clock in response to the output of the AND gate, and 5 is responsive to the second clock and an external active low write enable signal WEX. Generating a write clock WC, 6 is a mode controller for setting the normal operation mode or the test mode in response to the column address strobe signal CASX and the first clock, and 7 is the mode controller for setting the test mode A counter for counting the refresh address sometimes, 8 performs buffering and predecoding of the address in response to the count value of the counter and the external 10-bit address signals A _{0 to} A ₉ and the second clock. Circuits, 9 and 10 are predecoded addresses A plurality of word lines and a plurality of bit lines (that is, column lines) in the memory cell array 1 in response to the first and second clocks, respectively, based on the information.
A row decoder and a column decoder for selecting any one of the above, and 11 connects the selected bit line to the corresponding data line (I / O line) and outputs the data read from the selected cell to the first clock and Write clock WC
Sense amplifier (S /
A) circuit and I / O gate, 12 responds to the data read through the S / A circuit and I / O gate in response to a second clock and an external active low output enable signal OEX. External data output buffer (4-bit data DQ _{1 to} DQ ₄ ), 13 is a data input buffer that captures external 4-bit data in response to the write clock WC, and 14 amplifies the captured input data. And a write amplifier (W / A) circuit connected to the I / O gate, and 15 denotes a generator for generating a substrate bias.

A high-potential power supply voltage Vcc and a low-potential power supply voltage Vss are supplied to each circuit in the DRAM.
Next, the configurations of the S / A circuit and the I / O gate 11 and the W / A circuit 14 in FIG. 1 will be described with reference to FIGS. First, referring to FIG. 2, the S / A circuit is composed of n (n is a multiple of 8) sense amplifiers S / A _{1 to} S / An, and complementary bit lines BL ₁ , BLX _{1 to} BLn, BLXn, respectively. Connected to the memory cell array via a pair of column gate transistors (I / O gates)
The pair of complementary I / O lines DB ₁ , DBX _{1 to} DB ₈ , DBX ₈ are sequentially connected. In other words, the sense amplifiers S / A ₁ , S / A ₉ , ...
/ O lines DB ₁ and DBX ₁ connected to sense amplifiers S / A ₂ and S / A ₁₀ ,
... are connected to the same I / O lines DB ₂ and DBX ₂ , and so on, and so on.

On the other hand, the W / A circuit 14 has eight write amplifiers.
Consist _{W / A 1 ~W / A 8} , respectively amplify the data D ₁ to D ₈ from the data input buffer, respectively corresponding complementary I
/ O lines DB ₁ , DBX _{1 to} DB ₈ , DBX ₈ are connected. In FIG. 3, S
A circuit configuration of one column of the / A circuit and the W / A circuit (that is, each sense amplifier S / Ai and each write amplifier W / Ai) is shown.

First, the write amplifier W / Ai includes inverters 20 and 21 which respond to the corresponding input data Di, respectively.
, An inverter 22 responsive to the output of the inverter 20, an n-channel transistor 23 and a p-channel transistor 2 connected in series between the power supply line Vcc and the power supply line Vss.
4. From n-channel transistor 25 and n-channel transistor 26, and n-channel transistor 27, p-channel transistor 28, n-channel transistor 29 and n-channel transistor 30 which are also connected in series between power supply line Vcc and power supply line Vss It is configured. Here, the gates of the transistors 23, 26, 27 and 30 are connected to their respective drains, and the transistors 24, 25,
The output of the inverter 21, the output of the inverter 20, the output of the inverter 22 and the input data Di are applied to the gates of 28 and 29, respectively. The drains of the transistors 24 and 25 are connected to one of the corresponding I / O lines DBi and DBXi (D
Bi), and the drains of the transistors 28 and 29 are connected to the other I / O line (DBXi).

On the other hand, the sense amplifier S / Ai includes a NAND gate 40 that responds to a write signal (write clock WC) and a column selection signal CL, an inverter 41 that responds to the output of the NAND gate, and four cross-connected transistors. (P channel transistors 42, 44 and n channel transistors 43, 45) and corresponding complementary bit lines BLi, BL in response to the above-mentioned first clock (sense amplifier activation signal).
A flip-flop for expanding the level of Xi to a predetermined level, a p-channel transistor 46 connected between the flip-flop and one of the sense amplifier activation signal lines PSA and turned on / off in response to the output of the inverter 41, and An n-channel transistor 47 connected between the flip-flop and the other sense amplifier activation signal line NSA and turned on / off in response to the output of the NAND gate 40. The complementary bit lines BLi, BLXi and the corresponding I / O lines DBi, DBXi are connected via a pair of transfer gate n-channel transistors 51 and 52, and the transistors 51, 52 respond to the column selection signal CL. And turn it on and off.

The operation of the circuit of FIG. 3 will be described below with reference to the signal waveform diagram of FIG. In the initial state, the complementary I / O lines DBi and DBXi are at the "H" level (Vcc level), and the complementary bit lines BLi and BLXi are at the "L" level (Vss level) and "H" level, respectively. It is assumed to be at the "level (Vcc level).

First, regarding the write amplifier W / Ai, when the input data Di is at "H" level, the outputs of the inverters 20 and 21 are at "L" level and the output of the inverter 22 is at "H" level. Transistors 25 and 28 are cut off, and transistors 24 and 29 are turned on.
As a result, the level of the drain ends (DBi) of the transistors 24 and 25 rises to "H" level, and the level of the drain ends (DBXi) of the transistors 28 and 29 falls to "L" level.

However, an n-channel transistor 23 is provided between the source of the p-channel transistor 24 and the power supply line Vcc.
Since (the gate is connected to the drain) is connected, the level of the I / O line DBi finally stabilizes at a level lower than the power supply voltage Vcc by the threshold level Vth of the transistor 23 (FIG. 4). reference). Similarly, regarding the level of the complementary I / O line DBXi, since the n-channel transistor 30 (its gate is connected to the drain) is connected between the drain of the n-channel transistor 29 and the power supply line Vss, Power supply voltage V
It stabilizes at a level higher than ss by the threshold level Vth of the transistor 30.

When the input data Di is at "L" level, the level relationship between the complementary I / O lines DBi and DBXi is opposite to the logic shown in FIG. 4, and its operation mode is easy from the above description. The explanation is omitted here. Thus, in the write amplifier W / Ai, the transistors 23, 26,
27 and 30 are complementary I / O lines DBi and DB when writing data
The change width (that is, amplitude) of the level of Xi is set to the conventional (Vcc-V
It has a function of limiting the potential difference of (ss) to the potential difference of (Vcc-Vss-2Vth).

On the other hand, with respect to the sense amplifier S / Ai, the data write operation is started (that is, the write clock WC is at "H" level) and the bit line pair BLi, BLXi corresponding to the memory cell to be written, that is, the column. Is selected (that is, the column selection signal CL is at "H" level), the output of the NAND gate 40 is at "L" level and the output of the inverter 41 is at "H" level.
Cut off each. As a result, the flip-flops 42 to 45 are connected to the sense amplifier activation signal lines PSA, NS.
Electrically disconnected from A. That is, the sense amplifier S / Ai corresponding to the cell selected at the time of data writing stops its function (inactive state).

At this time, the "H" level column selection signal CL
As a result, the I / O gates 51, 52 are opened, so that the complementary I / O lines DBi, DBXi whose amplitude level is limited are connected to the complementary bit lines BLi, BLXi via the I / O gate. When data writing is completed (that is, the write clock WC is at "L" level) or a bit line pair other than the bit line pair is selected (that is, the column selection signal CL is at "L" level), the output of the NAND gate 40 is Since the "H" level and the output of the inverter 41 are the "L" level, the transistor 4
6,47 each turn on. As a result, the flip-flops 42 to 45 are connected to the sense amplifier activation signal line.
It is connected to PSA and NSA and receives power supply. That is, the sense amplifier S / Ai restarts its operation (active state).

By the re-operation of the sense amplifier, the data on the complementary bit lines BLi and BLXi, whose amplitude levels have been limited until then, are level-amplified to the potentials of Vcc and Vss, respectively, and as a result, the write operation becomes normal. Done.
Comparing the operation timing waveform (see FIG. 4) by the circuit configuration of this embodiment with the conventional operation timing waveform shown in FIG. 5, in the case of FIG. 5, I / O for writing information to the bit lines BL, BLX is performed. Although the levels of the lines DB and DBX are made to swing (full swing) between the power supply voltages Vss and Vcc, in the present embodiment (FIG. 4), the level amplitude of the I / O lines DBi and DBXi is limited (see the figure). In the example, a level between Vth and (Vcc-Vth)), thereby reducing the charge / discharge current of the I / O line. As a result, power consumption at the time of writing data can be reduced.

Since the operation of the sense amplifier S / Ai is stopped and restarted in synchronization with the data write start timing and the column selection signal CL, the delay of the write time can be suppressed as compared with the conventional type. it can. This contributes to speeding up data writing. In the present embodiment, the case where the amplitude levels of the I / O lines DBi and DBXi are limited by using the n-channel transistors 23, 26, 27 and 30 has been described. May be configured to perform.

Further, in the above-mentioned embodiment, the amplitude limitation is controlled on both the high potential side (Vcc) and the low potential side (Vss) of the power source voltage, but this is controlled on either one of the power source potential sides. It may be controlled. To this end, in the configuration of FIG. 3, for example, either one of the transistors 23 and 26 may be omitted, or the transistors 27 and 30 may be omitted.
Either one of them may be omitted.

Further, the level at which the amplitude is limited is also set to the threshold level Vth (see FIG. 4) for one transistor in this embodiment. For example, in the configuration of FIG. 3, the transistor 23 (or 26, 27, 30) is used. ) Two steps,
3 stages, ............ 2V each by connecting in series
Of course, it is possible to appropriately change and set the levels of th, 3Vth, ...

[0025]

As described above, according to the present invention, power consumption can be reduced and high-speed multi-bit data writing can be realized. by this. Memory (especially DRA
It is possible to improve the characteristics of M).

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a DRAM as an embodiment of the present invention.

FIG. 2 is a diagram schematically showing a configuration of an S / A circuit, an I / O gate, and a W / A circuit in FIG.

FIG. 3 is one of the S / A circuit and W / A circuit in FIG.
It is a circuit diagram which shows the structure for columns.

FIG. 4 is a signal waveform diagram for explaining the operation of the circuit of FIG.

FIG. 5 is a signal waveform diagram for explaining write and read operations in a conventional type.

[Explanation of symbols]

BL ₁ , BLX _{1 to} BLn, BLXn ... Complementary bit lines DB ₁ , DBX _{1 to} DB ₈ , DBX ₈ ... Complementary data lines (I / O lines) Di ... Input data (write data) S / Ai ... Sense amplifier circuit Vcc , Vss ... Power supply line (power supply voltage) W / Ai ... Write amplification circuit WC ... Control signal (write clock) 23 to 30, 42 to 47 ... (MOS) transistor 40 ... NAND gate 41 ... Inverter 51, 52 ... I / O gate (Transfer gate)

Claims (5)

[Claims] 1. Complementary data lines (DBi, DBXi) for transmitting read data or write data, complementary bit lines (BLi, BLXi) for transmitting data read from a memory cell, and connected to the complementary bit lines. And a sense amplifier circuit (S / Ai) that operates in response to a control signal (WC), and a transfer gate (51, 52) that connects the complementary bit line to the complementary data line when the memory cell is selected.
And a write amplifier circuit (W / Ai) that is connected to a power supply line (Vcc, Vss) and amplifies input data (Di) from the outside and outputs the amplified data to the complementary data line. When writing data, the write amplifier circuit reduces the level of the complementary data line to a voltage level (Vcc-Vth, Vss + Vth) smaller than the voltage of the power supply line, and the sense amplifier circuit sets a predetermined level of the control signal. A semiconductor memory device characterized in that its operation is stopped by setting a logic level. 2. The write amplifier circuit (W / Ai) is a pair of transistors having a CMOS structure that responds to the input data.
(24,25; 28,29) and level shift means (23,26,27,30) connected between the source side of at least one of the pair of transistors and the power supply line, 2. The semiconductor memory device according to claim 1, wherein the level reduction amount of the complementary data line is determined by the voltage shift amount of the level shift means. 3. The semiconductor memory device according to claim 2, wherein the level shift means is composed of an n-channel type or p-channel type transistor whose gate is connected to the drain. 4. The sense amplifier circuit (S / Ai) includes a flip-flop (42 to 45) for expanding the level of the complementary bit line to a predetermined level, and a logic level of the control signal when the memory cell is selected. Gate means (40, 41, 46, 40, 41, 46, for controlling the flip-flop to an active state or an inactive state according to
47) The semiconductor memory device according to claim 1, further comprising: 5. The semiconductor memory device according to claim 1, wherein the memory cell is a dynamic memory cell.