JPH06333389A - Column system driving method and semiconductor memory - Google Patents

Abstract

PURPOSE:To increase the speed of data reading/writing cycles. CONSTITUTION:By driving a boosting circuit for generating a high voltage Vch by boosting an internal power source voltage Vcc and field effective transisters 101-108 for selectively connecting a data line coupled to a memory cell to a common data line using the high voltage Vch obtained by the boosting circuit, the operating speed is increased. At this time, since all levels of data lines to be selected simultaneously are rewitten, input/output circuits are provided corresponding to a number of plural data lines simultaneously selected by the column selecting control at a time.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for speeding up a semiconductor memory device, and further a column processing circuit, which is effective when applied to, for example, a synchronous DRAM (dynamic random access memory). .

[0002]

2. Description of the Related Art In a conventional DRAM (dynamic random access memory), a transfer MOS selection signal for connecting a data line (also referred to as a bit line) coupled to the memory and a common I / O line. (Hereinafter, referred to as “data line selection signal”) is assigned to one to two to four data lines in terms of layout efficiency.
Since it was S, it was made equal to the power supply voltage potential at the time of selection. That is, the high level for selecting the data line is made equal to the internal power supply voltage Vcc, and the transfer MOS is selected by such a data line selection signal.

At the time of reading memory cell data, a plurality of data selected and read by one data line selection signal decoded by a column address are transmitted to the main amplifier by each common I / O line, and the main amplifier is supplied. The selected data is specified by the column address assigned to the amplifier. On the other hand, at the time of writing data, the level of the pair of common I / O lines is amplified by the write buffer,
The I / O transfer MOS is opened to transmit write data to the data line. At this time, other data lines sharing the data line selection signal are also selected and connected to the common I / O line. The common I / O line in the non-write state is precharged to the power supply potential or half of it, so to prevent data destruction, activate the sense amplifier before raising the data line selection signal and use the old data. Must be sufficiently amplified. Therefore, in the selected data line, the signal amplified by the sense amplifier and the write data compete with each other, and the write buffer is required to have a driving force capable of inverting the sense amplifier amplified signal.

An example of a document describing DRAM is "LSI Handbook (Page 486-)" issued by Ohm Co., Ltd. on November 30, 1984.

[0005]

However, in order to hold the data of the non-write data lines selected at the same time, a proper sense amplifier which does not destroy the data of the data line by the precharged common I / O. It is necessary to select the driving force and the mutual conductance gm of the I / O transfer MOS. This is transfer M
The mutual conductance gm of the OS cannot be sufficiently increased, which hinders the speeding up of the write operation and the read operation.

Further, in the conventional method, the high level of the data line selection signal is set to be equal to the power supply voltage.
It was lowered by the threshold value of S, and the lack of the level was compensated by amplifying with a sense amplifier.
As such, in the conventional device, the data line and the common I
The data transfer section with the / O line is the bottleneck for high-speed writing.

An object of the present invention is to provide a technique for shortening the cycle time by accelerating the data read / write cycle.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0009]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows.

That is, a high voltage obtained by boosting the internal power supply voltage is used to drive the field effect transistor for selectively coupling the data line coupled to the memory cell to the common data line according to the column address. Use voltage.

Further, by using a booster circuit for generating a high voltage by boosting the internal power supply voltage and the high voltage obtained by the booster circuit, the data line coupled to the memory cell is selectively A semiconductor memory device is configured to include a drive circuit for driving a field effect transistor for coupling to a common data line. At this time, a plurality of data lines simultaneously selected from one memory cell mat by one column selection control are assigned to different I / Os so that all of the simultaneously selected data lines can be rewritten. can do.

[0012]

According to the above-mentioned means, using the high voltage obtained by boosting the internal power supply voltage to drive the field effect transistor increases the transconductance of the field effect transistor. The signal level drop by the threshold value is prevented, and this acts to speed up the data read and write cycles, thus achieving a reduction in cycle time.

[0013]

FIG. 1 shows a DRAM according to an embodiment of the present invention.
(Dynamic Random Access Memory) is shown.

Although not particularly limited, the DRAM shown in FIG. 1 writes data in synchronization with a clock of an MPU (micro processing unit) (not shown).
It is a synchronous DRAM that enables reading. In the burst mode of the synchronous DRAM, the column address of the selected word is sequentially incremented, and the bit lines are sequentially selected to enable data input / output.

Such a synchronous DRAM is not particularly limited, but the input / output control circuits 11 to 11 for enabling data input / output to / from the outside through the input / output pins I / O1 to I / O4. 14 and input / output circuits 21 to 24 and 31 for amplifying memory read data from the memory cells.
To 34, 41 to 44, 51 to 54, memory cell arrays ARY0 to ARY7 in which a plurality of dynamic memory cells are arranged in an array, and data line selection signal YS are generated by decoding address signals Y0 to Y7. Column address decoder (ColumnDE
C) 17 and row decoders (RowDEC) 60 to 67 for generating control signals for driving the word lines by decoding the addresses X0 to X8.

Although not particularly limited, a non-multiplex system is adopted for fetching addresses, and a row address strobe signal RAS * (* indicates signal inversion or row active) and a column address strobe signal CAS * which are timing clocks are used. An external address signal is taken in synchronously, and row address (X0 to X0
X9) and column addresses (Y0 to Y9) are generated. Although not particularly limited, the row address (X0 to X8) is a word line 512 in one array.
Since one is selected from the books, it is input to the row decoders 60 to 61 arranged corresponding to each memory cell array. In this embodiment, since the shared system in which the sense amplifier is shared by the two arrays is used, the row address (X9) is used for selecting the memory cell array arranged on the left and right of the sense amplifier (SA). The column addresses Y0 to Y7 are decoded by the column decoder 17 to generate 256 data line selection signals YS. As shown representatively, one data line selection signal YS selects four data lines per one memory cell array. Since the shared method is used, the sense amplifier (SA) and common I /
The O line is shared by the two memory cell arrays identified by the row address (X9). That is,
Depending on the logic state of the row address (X9), one of the two memory cell arrays is selectively operated by the sense amplifier (S
By being connected to A) and the common I / O line, data can be read / written from / to the memory cell array.

FIG. 3 typically shows a configuration example of the input / output circuits 21 to 24.

As shown in FIG. 3, input / output circuits 21-2
Reference numeral 4 denotes a write buffer WB for amplifying a signal input from the outside via the input / output pins I / O1 to I / O4 and outputting the amplified signal to the common I / O, and conversely, the common I / O. And a main amplifier MA for amplifying the data of 1 to enable external output.

FIG. 4 shows the memory cell array A in FIG.
A configuration example of a column system direct peripheral circuit of RY0 and AEY1 is representatively shown.

The data line selection signal YS formed based on the output signal of the column decoder 17 is transferred to the transfer MO.
The input is made in S101 to S108. The transfer MOSs 101 to 108 are so-called column selection switches.
By 108, complementary data lines are selectively coupled to common I / O lines. Memory cell array AR
Y0 and ARY1 are shared MOS 71 to 78, 81
Separated by ~ 88. By asserting the shared signal SHR0 or SHR1 to a high level,
The memory cell array ARY0 or ARY1 is selectively coupled to the sense amplifiers SA1 to SA4. Here, the high level of the shared signals SHR0 and SHR1 is a boosted potential like the word line WL of the memory cell, and is not particularly limited, but the high potential side power supply V
It is set higher than cc by about 1.5 volts. In this way, the high level of the shared signals SHR0 and SHR1 is set higher than the high-potential-side power supply Vcc in the shared MOSs 71 to 78 and 81 to 88 because the write potential to the memory cell is caused by the threshold value. This is to prevent the deterioration. The sense amplifier SA1 shown as a representative is not particularly limited, but is a p-channel type MOS.
An inverter formed by connecting a transistor Qp1 and an n-channel type MOS transistor Qn11 in series and an inverter formed by directly connecting a p-channel type MOS transistor Qp2 and an n-channel type MOS transistor Qn12 are combined to form a shared MOS 71,
The signal level of the complementary data line selected by turning on 72 or 81, 82 is adapted to be amplified by this sense amplifier. Other sense amplifiers SA2
The SA4 also has the same configuration as that described above, and thus detailed description thereof will be omitted.

The direct peripheral circuits corresponding to other memory cell arrays have the same structure as above.

FIG. 5 representatively shows a configuration example of the memory cell array ARY0.

Representative memory cell array ARY
0 is a so-called 1-transistor type configuration, which is composed of a charge storage capacitor 91 and an n-channel MOS transistor 92 connected in series. WL0 to WL3 are word lines, and when this word line is driven to the selection level, data writing or data reading to the memory cell coupled thereto can be performed. BL and BL * are complementary data lines, and a plurality of memory cells are coupled to the complementary data lines BL and BL *, and data can be written to and read from the memory cells via the complementary data lines. To be done. Further, a precharge circuit PCMOS including n-channel MOS transistors 93 to 95 is coupled to the complementary data lines BL and BL *,
At the timing when the precharge control signal PC is asserted to the high level, the complementary data lines BL and BL * become Vcc.
It is designed to be precharged to / 2 (1/2 level of the power supply voltage Vcc).

FIG. 6 shows a circuit configuration example for generating the data line selection YS based on the column decode signal.

The high voltage Vch generated by the booster circuit 121 for boosting the high-potential-side power supply Vcc is applied to the p-channel type MOS transistors 111, 112, 113. An inverter is formed by connecting the n-channel MOS transistor 110 in series to the p-channel MOS transistor 111. The output of this inverter is the data line selection signal Y
S. p-channel type MOS transistor 111
Is turned off, the data line selection signal YS is set to a low level. At this time, in order to sufficiently turn off the p-channel type MOS transistor 111, a high voltage Vch is applied to the gate electrode of this p-channel type MOS transistor 111. P-channel MOS transistors 112 and 113 are provided for this purpose. That is, when the column control signal generated based on the column address strobe signal CAS * is at the low level, the p-channel MOS transistor 113 is turned on so that the high voltage Vch changes to the p-channel MOS transistor 11.
1 to the gate electrode. At this time, the data line selection signal YS becomes low level, and the data line selection signal YS is faded back to the p-channel type MOS transistor 112, so that the state is maintained.
An inverter 116 for inverting a part of the column decode signal is provided, and the output terminal of the inverter 116 is coupled to the gate electrodes of the MOS transistors 110 and 111 via the n-channel MOS transistor 114. The n-channel type MOS transistors 119 and 120 controlled by the column decode signal are connected in series with each other, and a p-channel type M transistor is used as a load thereof.
OS transistors 117 and 118 are provided. While the column control signal is asserted to high level,
When the n-channel MOS transistors 119 and 120 are turned on by the column decode signal, the output logic state of the inverter 115 is set to the high level, and the n-channel MOS transistor 114 is turned on, so that the data line selection signal YS. Is a high level.
Then, after the main amplifier (MA) is activated, the n-channel MOS transistor 114 is turned off, so that the data line selection signal YS is set to the low level.

Next, the operation of the circuit of this embodiment will be described in comparison with the conventional configuration shown in FIG.

In the conventional memory shown in FIG. 2, input / output selection circuits 2 to 5 are provided, and the input / output circuit is selected according to the combination of the addresses Y8 and Y9. The four data selected from one array are selected from the four data by the main amplifier control by the column addresses Y8 and Y9 during amplification by the main amplifier. Also in data writing, only one bit is written to the four data lines simultaneously selected for one array by the write buffer selected by the column addresses Y8 and Y9. On the other hand, in the array configuration of the device of the present embodiment, the column addresses Y8 and Y9 are used for array selection, and when writing (reading) data, one memory cell array of ARY0 to ARY7 is selected. Bit data is output, amplified by each main amplifier, transmitted to each input / output pin, and the selected 4 bits are written by each write buffer.

That is, in the conventional method, only one bit is actually written in the four data lines simultaneously selected by one data selection signal YS.
When only / O1 is written, the other common I / Os are precharged to the power supply potential and the sense amplifiers SA2 to SA4
The data line connected to the I / O transfer MOS is amplified by the sense amplifier for rewriting.
Since T101 to 108 are turned on, the sense amplifier pull-out MOS (for example, Qn
12) and the transfer MOS 101 connected to the common I / O line precharged to the high level attract each other. Therefore, in the conventional method, the mutual conductance gm of the transfer MOS 101 is
It is necessary to lower than Qn12, and it is necessary to invert the sense amplifier of the write data line by the driving force of the write buffer (WB), but in this embodiment, one column selection control is performed to select simultaneously. Since the input / output circuits are provided corresponding to the number of the plurality of data lines to be written and all the simultaneously selected data lines are rewritten, it is necessary to pay attention to the mutual conductance gm of the I / O transfer MOS and the sense amplifier SA. I / O for high speed writing
The gate input of the transfer MOS can be used as a boosted potential for full writing in the write buffer.

As described above, according to the present embodiment, the old data by the sense amplifier can be written by the write buffer (WB) having a sufficiently large driving force, so that the write cycle can be speeded up. In particular, it is particularly effective for a page mode of a synchronous DRAM or the like in which column addresses are continuously rewritten.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited thereto, and needless to say, various modifications can be made without departing from the scope of the invention. Yes.

For example, in the figure, a precharge circuit (PC) for precharging a data line is provided adjacent to a memory cell array.
MOS) is arranged, but this precharge circuit P
Needless to say, the CMOS can be shared between the two memory cell arrays by arranging the CMOS between the shared MOSs like the sense amplifier.

In the above description, the case where the invention made by the present inventor is mainly applied to the synchronous DRAM which is the background field of application has been described, but the present invention is not limited thereto and DRAM in general. Can be applied to.

The present invention can be applied on condition that at least the data line coupled to the memory cell is selectively coupled to the common data line.

[0034]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, a high voltage obtained by boosting the internal power supply voltage is used to drive the field effect transistor for selectively coupling the data line coupled to the memory cell to the common data line according to the column address. By using the voltage, it is possible to increase the transconductance of the field-effect transistor and prevent the level from being reduced by the threshold value, thereby speeding up the data read / write cycle. Also, a plurality of data lines simultaneously selected from one memory cell mat by one column selection control are assigned to different I / Os, and all of the simultaneously selected data lines are rewritable. The drive power of the write buffer can be increased with respect to the drive power of the sense amplifier, and the write data can be input / output without waiting for amplification by the sense amplifier. Can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram of an array configuration of a DRAM according to an exemplary embodiment of the present invention.

FIG. 2 is a block diagram of an array configuration of a conventional DRAM.

FIG. 3 is a block diagram of a configuration example of an input / output circuit in the above embodiment.

FIG. 4 is a circuit diagram of a configuration example of a column direct peripheral circuit in the above embodiment.

FIG. 5 is a circuit diagram of a configuration example of a memory cell in the above embodiment.

FIG. 6 is a configuration circuit diagram of a circuit that generates a data selection signal by using a high voltage in the above embodiment.

[Explanation of symbols]

 11-14 Input / output control circuit 17 Column decoder 21-24 Input / output circuit 31-34 Input / output circuit 41-44 Input / output circuit 51-54 Input / output circuit 60-67 Row decoder 71-78 Shared MOS 81-81 Shared MOS 91 Charge storage capacitors 101 to 108 for forming a memory cell Transfer MOS 121 Booster circuit SA1 to SA4 Sense amplifier PCMOS precharge circuit MA Main amplifier WB Write buffer WL0 to WL3 Word line BL, BL * Complementary data line

Claims (4)

[Claims] 1. A column system for driving a column system including a field effect transistor for selectively coupling a data line coupled to a memory cell to a common data line according to a column address, based on the column address. In the driving method, the field-effect transistor is driven by a high voltage obtained by boosting an internal power supply voltage. 2. A memory cell having a field effect transistor for selectively coupling a data line coupled to a memory cell to a common data line, and controlling the field effect transistor based on a column address. In a semiconductor memory device capable of reading and writing data, a booster circuit for generating a high voltage by boosting an internal power supply voltage, and the field effect transistor using the high voltage obtained by the booster circuit A semiconductor memory device comprising: a drive circuit for driving. 3. A plurality of data lines simultaneously selected from one memory cell mat by one column selection control are assigned to different I / Os so that all of the simultaneously selected data lines can be rewritten. The semiconductor memory device according to claim 2, wherein the semiconductor memory device is configured as described above. 4. The semiconductor memory device according to claim 2, wherein the field effect transistor is an n-channel MOS transistor.