JPH09213069A - Semiconductor memory - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor memory capable of making a dynamic RAM, etc., using a hierarchical bit line system highly integrated circuit and stabilizing its operation. SOLUTION: In a dynamic RAM, etc., which use a hierarchical bit line system, its memory arrays ARY0-ARY3 are made to have a so-called open-type array structure in which the non-inversion and inversion signal lines of the main bit lines MB0*-MBn* are arranged on the two sides of sense amplifiers SA0-SA3. In this structure, the lenths of the non-inversion and inversion signal lines of the main bit lines MB0*-MBn* are successively halved in the column direction to cancel the coupling noise between neighboring bit lines. And, subbit lines B0U*-BnU* and B0L*-BnL* are arranged with half the pitch of the main bit lines so that the two subbit lines are paired in correspondence with the main bit lines and one of the two paired subbit lines is connected to the alternatively corresponding line of the main bit lines MB0*-MBn*, and the other is connected to, for example, an intermediate potential supplying point to give a shield effect.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, for example, a dynamic RAM (random access memory) adopting a hierarchical bit line system, and a technique particularly effective when used for further high integration and stabilization of its operation. It is about.

[0002]

2. Description of the Related Art Information storage capacitor and address selection M
2. Description of the Related Art There is a dynamic RAM having a memory array in which dynamic memory cells composed of OSFETs are arranged in a lattice as its basic constituent element. Further, as one means for increasing the degree of integration and increasing the speed of such a dynamic RAM, a bit line forming a memory array is divided into a plurality of sub-bit lines in the extension direction thereof and main bits corresponding to these sub-bit lines are divided. There is a so-called hierarchical bit line system that selectively connects lines.

[0003]

In a conventional dynamic RAM adopting a hierarchical bit line system, main bit lines and sub bit lines forming a memory array are arranged adjacent to each other with their non-inversion and inversion signal lines folded back. A sense amplifier that adopts a so-called folded bit line system and amplifies a minute read signal of a selected memory cell is
Basically, it is arranged on one side of the main bit line. Further, all of these main bit lines have substantially the same length and are associated with the corresponding sub bit lines in a one-to-one correspondence in the column direction. Therefore, when attempting to further increase the integration density of the dynamic RAM, the structure of the memory cell is relatively complicated due to the folded bit line system, which restricts the high integration of the dynamic RAM, and Coupling noise between adjacent main bit lines and sub bit lines increases with integration, and the operation of the dynamic RAM becomes unstable.

An object of the present invention is to further increase the integration of a dynamic RAM adopting a hierarchical bit line system,
The aim is to stabilize the operation.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0006]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, in a dynamic RAM or the like adopting the hierarchical bit line system, the memory array has a so-called open type array structure in which the non-inverted and inverted signal lines of the main bit line are arranged on both sides of the sense amplifier, and the length of the main bit line is increased. Is sequentially halved in the column direction. In addition, the sub-bit lines are arranged at a pitch of one half of the main bit lines, and two sub-bit lines are formed corresponding to the main bit lines, and one of the two sub-bit lines forming the pair is selectively formed. The corresponding main bit line is connected, and the other is connected to, for example, an intermediate potential supply point.

According to the above-mentioned means, by adopting the open type array structure, the structure of the memory cell can be simplified, the memory array can be highly integrated by miniaturization, and the length of the main bit line can be determined by the column. By sequentially halving each direction, the coupling noises between adjacent main bit lines cancel each other out, and by connecting the sub-bit lines in the non-selected state to the intermediate potential supply point, these sub-bits are connected. The lines can shield the sub-bit lines in the selected state, and the coupling noise between the sub-bit lines can be suppressed. As a result, while enjoying the effect of adopting the hierarchical bit line system, it is possible to achieve higher integration of the dynamic RAM adopting the hierarchical bit line system and to stabilize the operation thereof.

[0008]

FIG. 1 is a block diagram showing an embodiment of a dynamic RAM (semiconductor memory device) to which the present invention is applied. First, an outline of the configuration and operation of the dynamic RAM according to this embodiment will be described with reference to FIG. The circuit elements forming each block in FIG. 1 are not particularly limited, but known MOSFETs (metal oxide semiconductor field effect transistors. In this specification, MOSFETs are generically called insulated gate field effect transistors. It is formed on one semiconductor substrate such as single crystal silicon by the manufacturing technology of integrated circuits.

In FIG. 1, the dynamic RAM of this embodiment is not particularly limited, but includes four memory arrays ARY0 to ARY3 and three sense amplifiers SA0 to SA2 arranged between these memory arrays. Equipped with. Of these, the memory arrays ARY0 to ARY3 include 3 × (m + 1) word lines arranged in parallel in the vertical direction in the figure and n + 1 main bit lines arranged in parallel in the horizontal direction in the figure. Including each. Although not particularly limited, these main bit lines are formed by the first metal wiring layer, and are arranged in the lower layer at a pitch of one half of the main bit lines and are substantially divided into three in the extension direction. A total of 3 × (n + 1) pairs of sub-bit lines are provided. These sub-bit lines are formed of a polysilicon layer, and three pairs of sub-bit lines provided corresponding to each main bit line are selectively connected to one of the main bit lines. Connected. At the intersections of the word lines and the sub-bit lines that form the memory arrays ARY0 to ARY3, 3 × (m + 1) × (n + 1) dynamic memory cells each including an information storage capacitor and an address selection MOSFET are arranged in a grid pattern. The specific configuration of the memory arrays ARY0 to ARY3 will be described in detail later.

Each of the 3 × (m + 1) word lines forming the memory arrays ARY0 to ARY3 is coupled to the corresponding X address decoder XD0 to XD3, and is selectively set to the selection level. These X address decoders XD0 to XD3 have X address buffers XB to i
+ 1-bit internal address signals X0 to Xi are commonly supplied, and an internal control signal XG (not shown) is commonly supplied from the timing generation circuit TG. The X address buffer XB has address input terminals A0 to Ai.
The X address signals AX0 to AXi are supplied in a time-divisional manner via, and the timing control circuit TG supplies the internal control signal XL.

The X address buffer XB has an address input terminal A when the dynamic RAM is selected.
X-address signals AX0-A supplied via 0-Ai
Xi is fetched and held according to the internal control signal XL, and internal address signals X0 to Xi are formed based on these X address signals, and X address decoders XD0 to XD0
Supply to XD3. Further, the X address decoders XD0 to XD0
The internal control signal XG is set to the high level and the internal address signals Xi-1 and Xi of the upper 2 bits are set to the high level or the low level in a corresponding combination to selectively activate the XD3, and the remaining internal The memory array ARY0 is decoded by decoding the address signals X0 to Xi-2.
The corresponding word lines of ~ ARY3 are alternatively set to the high level. The upper 2 bits of the internal address signal Xi-1
And Xi are also supplied to the timing generation circuit TG, and are used to selectively form internal control signals PC0 to PC2, PA0 to PA2 and DS0 to DS2 described later.

Next, the n + 1 main bit lines forming the memory arrays ARY0 to ARY3 are selectively halved in length in the column direction, in other words, doubled in sequence, as will be described later, and are selectively doubled. Becomes a non-inverted main bit line or an inverted main bit line, and the sense amplifier SA0
~ SA2 is coupled to the corresponding unit amplifier circuit. That is, for example, the even-numbered main bit lines of the memory array ARY0 become non-inverting main bit lines and are coupled to the non-inverting input / output nodes of the corresponding unit amplifier circuits of the sense amplifier SA0, and the even-numbered main bit lines of the memory array ARY1. The main bit line becomes an inverted main bit line and is coupled to the inverted input / output node of the corresponding unit amplifier circuit of sense amplifier SA0. Also, the odd-numbered main bit lines of the memory array ARY0 are extended as they are as the odd-numbered main bit lines of the memory array ARY1 to become non-inverted main bit lines, and the non-inverted input / output of the corresponding unit amplifier circuit of the sense amplifier SA1 is performed. Is bound to a node. On the other hand, the even-numbered main bit lines of the memory array ARY2 become non-inverted main bit lines and are coupled to the non-inverted input / output nodes of the corresponding unit amplifier circuit of the sense amplifier SA2, and the even-numbered main bit lines of the memory array ARY3. The line serves as an inverted main bit line and is coupled to the inverted input / output node of the corresponding unit amplifier circuit of sense amplifier SA2. Further, the odd-numbered main bit lines of the memory array ARY3 are extended as they are as the odd-numbered main bit lines of the memory array ARY2 to become the inverted main bit lines, and are connected to the inverted input / output nodes of the corresponding unit amplifier circuits of the sense amplifier SA1. Be combined.

The sense amplifiers SA0-SA2 are commonly supplied with an n + 1-bit bit line selection signal YS0-YSn (not shown) from the Y address decoder YD, and the corresponding internal control signals PC0-PC2 and the corresponding timing control circuit TG. PA0 to PA2 are supplied respectively. Further, the Y address decoder YD includes an i + 1-bit internal address signal Y from the Y address buffer YB.
0 to Yi are supplied, and the timing generation circuit T
An internal control signal YG (not shown) is supplied from G. Further, the Y address buffer YB has Y address signals AY0 to AYi via the address input terminals A0 to Ai.
Are supplied in a time division manner, and an internal control signal YL is supplied from the timing generation circuit TG.

The Y address buffer YB has an address input terminal A when the dynamic RAM is selected.
Y address signals AY0 to AY supplied via
Yi is fetched and held according to the internal control signal YL, and internal address signals Y0 to Yi are formed based on these Y address signals and supplied to the Y address decoder YD. Further, the Y address decoder YD is selectively activated by receiving the high level of the internal control signal YG.
The internal address signals Y0 to Yi supplied from the Y address buffer YB are decoded to generate the sense amplifiers SA0 to S0.
The bit line selection signals YS0 to YSn for A2 are alternatively set to the high level.

Sense amplifiers SA0-SA2 respectively include (n + 1) / 2 unit circuits provided corresponding to even-numbered or odd-numbered main bit lines of memory arrays ARY0-ARY3, and each of these unit circuits. Is a unit amplifier circuit in which a pair of CMOS (complementary MOS) inverters are cross-coupled, a pair of N-channel type switch MOSFETs, and three N-channel MOSs.
A unit precharge circuit including an FET is included. Among them, the unit amplifier circuit of each unit circuit is selectively activated by receiving the high level of the corresponding internal control signals PA0 to PA2, and is coupled to the selected word line of the memory arrays ARY0 to ARY3 (n + 1). The minute read signal output from the / 2 memory cells through the corresponding main bit line is amplified to be a high level or low level binary read signal.

On the other hand, the switch MOSFET of each unit circuit of the sense amplifiers SA0 to SA2 is selectively turned on in response to the high level of the corresponding bit line selection signals YS0 to YSn, and corresponds to the designated main bit line. Complementary common data lines CD0 * to CD2 * (here, for example, the non-inverted common data lines CD0T and CD0B are collectively denoted by * like the complementary common data line CD0 *. Also, it is validated. A so-called non-inverted signal or the like that is selectively set to a high level when it is turned on is represented by adding T to the end of the name, and a so-called inverted signal or the like that is selectively set to a low level when it is enabled , B is added to the end of the name. The same applies hereinafter) to selectively establish a connection state. In addition, the unit precharge circuit of each unit circuit is selectively activated by setting the corresponding internal control signals PC0 to PC2 to the high level, and the corresponding non-inverted and inverted main bit lines are connected to the power supply voltage of the circuit. And precharge to an intermediate potential between the ground potential and the ground potential. Note that specific configurations and operations of the sense amplifiers SA0 to SA2 will be described in detail later.

The complementary common data lines CD0 * to CD2 * are
The other side is coupled to the data input / output circuit IO.
The data input / output circuit IO includes one data input buffer, one data output buffer, a write amplifier, a main amplifier and a data selection circuit, respectively. Of these, the input terminal of the data input buffer is coupled to the data input terminal Din, and the output terminal thereof is coupled to the input terminal of the write amplifier. Further, the input terminal of the data output buffer is coupled to the output terminal of the main amplifier, and the output terminal thereof is coupled to the data output terminal Dout. The output terminal of the write amplifier and the input terminal of the main amplifier are selectively connected to the complementary common data lines CD0 * to CD2 * via the data selection circuit. An internal control signal WP (not shown) is supplied from the timing generation circuit TG to the write amplifier of the data input / output circuit IO. The data output buffer is supplied with the internal control signal OC, and the data selection circuit is supplied with internal control signals DS0 to DS2 (not shown).

The data selection circuit of the data input / output circuit IO, in accordance with the internal control signals DS0-DS2 supplied from the timing generation circuit TG, specifies the designated complementary common data lines CD0 * -CD2 * and the output terminal of the write amplifier or the main. The input terminals of the amplifier are selectively connected. The data input buffer is a dynamic RA.
When M is selected in the write mode, the write data input from the data input terminal Din is fetched and transmitted to the write amplifier. At this time, the write amplifier selectively operates in response to the high level of the internal control signal WP, and sets the write data transmitted from the data input buffer as a predetermined complementary write signal from the data selection circuit to the complementary common data line CD0. Write to one selected memory cell of the memory arrays ARY0 to ARY3 via * to CD2 *.

On the other hand, the main amplifier of the data input / output circuit IO has a complementary common data line CD0 from one selected memory cell of the memory arrays ARY0 to ARY3 when the dynamic RAM is selected in the read mode.
The binary read signal output via * to CD2 * and the data selection circuit is further amplified and transmitted to the data output buffer. At this time, the data output buffer receives the high level of the internal control signal OC and is selectively operated, and outputs the read signal transmitted from the main amplifier from the data output terminal Dout to the external device.

The timing generation circuit TG is provided with a row address strobe signal RASB and a column address strobe signal CASB which are supplied as an activation control signal from an external device.
Further, the various internal control signals and the like are selectively formed on the basis of the write enable signal WEB and the internal address signals Xi-1 and Xi of the upper 2 bits supplied from the X address buffer XB, and the dynamic RAM Supply to each part.

FIG. 2 shows an array configuration diagram of the first embodiment of the dynamic RAM of FIG. 1, and FIG.
Array ARY included in dynamic RAM
0 and ARY1 and a partial circuit diagram of one embodiment of the sense amplifier SA0 is shown. Further, FIG. 4 is a conceptual diagram for explaining noise interference between the main bit lines of the memory arrays ARY0 and ARY1 of FIG. 3, and FIG. 5 is a diagram for explaining a shield effect by the adjacent sub bit lines. The conceptual diagram of is shown. Further, FIG. 6 shows a signal waveform diagram of one embodiment in the read mode of the dynamic RAM of FIG. Based on these figures, the array configuration of the dynamic RAM of this embodiment, the specific configuration and operation of the memory array and sense amplifier, and their characteristics will be described. The following description regarding the memory arrays ARY0 to ARY3 will be given.
The memory arrays ARY0 and ARY1 will be taken as an example, but the memory arrays ARY2 and ARY3 have the same configuration as this, so please analogize. Further, in FIGS. 4 to 6, detailed description will be given by taking as an example the case where the memory cell arranged at the intersection of the word line W21 and the non-inversion sub-bit line B22LT of the memory array ARY0 is in the selected state. In the following circuit diagrams, the MOSFET whose channel (back gate) part is attached with an arrow is a P-channel type, and the N-channel MOSFE without an arrow is attached.
It is shown separately from T.

In FIG. 2, the dynamic RAM of this embodiment adopts a hierarchical bit line system using an open array structure, and four memory arrays ARY0 to ARY3.
It has three sense amplifiers SA0 to SA2 arranged between these memory arrays. Of these, each of the memory arrays ARY0 to ARY3 has a total of 3 × (m + 1) word lines W0 arranged in parallel in the vertical direction of the drawing.
0-W0m, W10-W1m and W20-W2m
And n + 1 main bit lines MB0 * to MBn * arranged in parallel in the horizontal direction of the drawing (here, each of the main bit lines MB0 * to MBn * is
Non-inverted or inverted main bit lines according to the correspondence with the memory arrays ARY0 to ARY3). The main bit lines MB0 * to MBn * forming the memory arrays ARY0 to ARY3 are formed by the first metal wiring layer, although not particularly limited thereto.

Under the main bit lines MB0 * to MBn *, the main bit lines are arranged at a pitch of ½ of these main bit lines and are divided into three in the extension direction of the main bit lines to form a pair of 3 ×. (N + 1) pairs, that is, 6 × in total
(N + 1) sub-bit lines B0U * to BnU * and B0L * to BnL * (here, sub-bit lines B0U *
~ BnU * and B0L * to BnL * respectively,
As will be described later, it becomes a non-inverted or inverted sub-bit line depending on the correspondence with the memory arrays ARY0 to ARY3. Also,
These sub-bit lines are actually word lines W00-W.
Corresponding to 0 m, W10 to W1 m and W20 to W2 m, sub-bit lines B00U * to B0nU *, B10U * to
B1nU * and B20U * to B2nU * or B
00L * to B0nL *, B10L * to B1nL * and B20L * to B2nL *, the sub-bit lines B0U * to BnU are simply described in the following description regarding the array configuration.
* And B0L * to BnL *) are arranged respectively. Sub bit lines B0U * to BnU * and B
Although not particularly limited, 0L * to BnL * are made of a polysilicon layer, and these sub-bit line and word line W00 are included.
.About.W0m, W10 to W1m, and W20 to W2m, a total of 3 × (m + 1) × (n +) including information storage capacitors and address selection MOSFETs, respectively.
1) Dynamic memory cells are arranged in a grid.

On the other hand, sense amplifiers SA arranged at both ends
0 and SA2 respectively include (n + 1) / 2 unit circuits provided corresponding to the even-numbered complementary main bit lines MB0 *, MB2 * to MBn-1 * of the memory arrays ARY0 and ARY1 or ARY2 and ARY3. , The sense amplifier SA1 arranged at the center includes memory arrays ARY0 and ARY1 and ARY2 and ARY.
3 odd numbered complementary main bit lines MB1 *, MB3 *
To (n + 1) / 2 unit circuits provided corresponding to MBn *. In addition, sense amplifiers SA0 and SA
Each unit circuit 2 includes unit amplifier circuits USA0, USA2 to USAAn each having a pair of CMOS inverters cross-coupled, as exemplified by the sense amplifier SA0 in FIG.
-1 and a pair of N-channel type switch MOSFETs
N5 and N6, and three N channel MO not shown
Each unit circuit of the sense amplifier SA1 includes a unit precharge circuit UPC0, UPC2 to UPCn-1 which is composed of an SFET and is shown in each unit amplifier circuit.
Similar unit amplifier circuits USA1, USA3 to USAAn
And N-channel MOSFETs N5 and N6 and unit precharge circuits UPC1, UPC3 to UPCn
Including and respectively.

The even-numbered main bit lines constituting the memory arrays ARY0 and ARY2 are non-inverted main bit lines MB0T, MB2T to MBn-1T, respectively, and the unit amplifier circuits USA0, SA0, SA2 corresponding to the sense amplifiers SA0 or SA2 are arranged on the right side thereof. USA2 to USA
It is coupled to the n-1 non-inverting input / output nodes. The even-numbered main bit lines forming the memory arrays ARY1 and ARY3 are respectively inverted main bit lines MB0.
B, MB2B to MBn-1B, and on the left side thereof are connected to the inverting input / output nodes of the corresponding unit amplifier circuits USA0, USA2 to USAn-1 of the sense amplifier SA0 or SA2. On the other hand, the odd-numbered main bit lines constituting the memory array ARY0 are extended in the memory array ARY1 as non-inverted main bit lines MB1T, MB3T to MBnT, respectively, and the corresponding unit amplifier circuit USA of the sense amplifier SA1 is provided at the right end thereof.
1, USA3 through USAAn are coupled to the non-inverting input / output nodes. The odd-numbered main bit lines forming the memory array ARY3 are extended in the memory array ARY2 as inverted main bit lines MB1B, MB3B to MBnB, respectively, and the unit amplifier circuits USA1 and USA3 corresponding to the sense amplifier SA1 at the left end thereof. Through USAAn.

As described above, the dynamic type R of this embodiment is used.
In AM, the lengths of the main bit lines forming the memory arrays ARY0 to ARY3 are sequentially halved in the column direction,
In other words, it is sequentially doubled in the column direction, which has an effect of suppressing noise interference between the main bit lines arranged adjacent to each other. Further, in this embodiment, as described above, the so-called hierarchical bit line system is adopted in which the bit line is divided into a plurality of sub bit lines in the extension direction and the corresponding main bit lines are selectively connected to each other. The dynamic RAM is made faster by shortening the length of the sub-bit line, which tends to increase the load capacitance to the cell, and the non-inversion and inversion signal lines of the main bit line and the sub-bit line are arranged on both sides of the sense amplifier. The open type array structure is adopted, the device structure of the memory cell is simplified, and the memory array and hence the dynamic RAM are highly integrated. The noise interference between the main bit lines and its suppression will be described later in detail.

As illustrated in FIG. 3, the drains of the address selection MOSFETs of the 3 × (m + 1) memory cells arranged in the same column of the memory arrays ARY0 to ARY3 sequentially correspond to every other non-inversion. Sub bit line B00
UT to B0nUT to B20UT to B2nUT or B00LT to B0nLT to B20LT to B2nL
T and inverted sub-bit lines B00UB to B0nUB to B20UB to B2nUB or B00LB to B0
nLB to B20LB to B2nLB are commonly coupled. In addition, n + 1 arranged in the same row of each memory array
The gates of the address selection MOSFETs of the memory cells correspond to the corresponding word lines W00 to W0m, W10 to W1m.
And W20 to W2m are commonly connected.

Next, one of the three pairs of sub bit lines (hereinafter referred to as the upper sub bit line of each main bit line) provided corresponding to each main bit line of the memory arrays ARY0 to ARY3, that is, the non-inverted sub bit line B00UT. ~ B
0nUT to B20UT to B2nUT and inverted sub-bit lines B00UB to B0nUB to B20UB to
B2nUB is an N-channel switch MOSFET
It is coupled to the corresponding main bit line via N1 or N3 and is a P-channel type switch MOSFET.
It is coupled to a predetermined potential supply point, that is, an internal voltage supply point HVC via P1 or P3. In addition, the memory array ARY
The other of the three pairs of sub bit lines (corresponding to the sub bit lines below the main bit lines) provided corresponding to the main bit lines of 0 to ARY3, that is, non-inverted sub bit lines B00LT to B0nLT to B20LT to B2nLT.
In addition, the inverted sub-bit lines B00LB to B0nLB to B20LB to B2nLB are coupled to the corresponding main bit line via the N-channel type switch MOSFET N2 or N4, and the internal voltage is supplied via the P-channel type switch MOSFET P2 or P4. It is connected to the point HVC. Of these, switch MOSFE
The X address decoder XD is provided at the gates of TN1 and P1.
0 to XD3 corresponding selection control signals S00U to S02
U to S30U to S32U are commonly supplied to the gates of the switch MOSFETs N2 and P2.
Corresponding selection control signals S00L to S02L to S30L to S32L are commonly supplied from the X address decoders XD0 to XD3.

The internal voltage HVC supplied to the internal voltage supply point HVC is set to an intermediate potential between the power supply voltage of the circuit and the ground potential. Further, the selection control signals S00U to S02
U to S30U to S32U and S00L to S02
L to S30L to S32L are not particularly limited,
When the dynamic RAM is in the non-selected state, all are at the low level, and when it is in the selected state, according to the internal timing signals Xi-1 and Xi of the upper 2 bits and the internal address signal X0 of the least significant bit at a predetermined timing. Alternately set to high level.

As a result, the memory arrays ARY0 to AR
The non-inverting and inverting sub-bit lines of Y3 correspond to the switch M when the dynamic RAM is in the non-selected state.
All internal voltage supply points H through OSFETs P1 to P4
It is connected to VC and is precharged to an internal voltage HVC, that is, an intermediate potential. Then, the dynamic RAM is set to the selected state, and the selection control signals S00U to S02U to S3.
0U to S32U or S00L to S02L to S3
When the corresponding bits of 0L to S32L are alternatively set to the high level, the switch MOSFET N1 in the ON state
To N4, any one of the three pairs is selectively connected to the corresponding main bit line, and then sense amplifiers SA0 to SA are connected via these main bit lines.
It is connected to the non-inverting or inverting input / output node of the corresponding unit amplifier circuit of A3.

Next, the unit amplifier circuits USA0, USA2 to USAAn-1 and USA1, USA3 to US which form the unit circuits of the sense amplifiers SA0 to SA2, respectively.
Corresponding internal control signals PA0 to PA2 are commonly supplied to An from the timing generation circuit TG. Further, the unit precharge circuits UPC0, UPC2 to U
PCn-1 and UPC1, UPC3 to UPCn
Corresponding common control signals PC0-PC2 are respectively supplied from the timing generation circuit TG to the gates of the switch MOSFETs N5 and N6 and corresponding bit line selection signals YS0-YS from the Y address decoder YD.
n are respectively supplied.

As a result, the sense amplifiers SA0-SA2
The unit amplifier circuit of each unit circuit selectively receives (n) the high level of the corresponding internal control signals PA0-PA2.
+1) / 2 cells are simultaneously activated, and (n + 1) / 2 memory cells coupled to the selected word line of the memory arrays ARY0 to ARY3 are output through the corresponding main bit line for minute reading. The signals are respectively amplified to be a high level or low level binary read signal. Also, the unit precharge circuit of each unit circuit is
Upon receiving the high level of the corresponding internal control signals PC0 to PC2, the corresponding non-inverting and inverting main bit lines are precharged to an intermediate potential such as the internal voltage HVC. Furthermore, the switch MOS of each unit circuit
FETs N5 and N6 have corresponding bit line selection signals YS
Upon receiving the high level of 0 to YSn, it is selectively turned on, and the corresponding non-inverted and inverted main bit lines and the complementary common data lines CD0 * to CD2 * are selectively connected.

By the way, the dynamic type R of this embodiment
As illustrated in FIG. 6, AM is selectively brought into a selected state by changing the row address strobe signal RASB to the low level. When a predetermined time has elapsed after the row address strobe signal RASB was set to the low level, the column address strobe signal CASB is set to the low level and the write enable signal WEB is kept at the high level to specify the read mode. The word line W2 is supplied to the address input terminals A0 to Ai in synchronization with the fall of the row address strobe signal RASB.
The X address signal is supplied to specify the row address ra corresponding to 1, and the column address strobe signal CAS is supplied.
In synchronization with the fall of B, the Y address signal is supplied to specify the column address ca corresponding to the bit line selection signal YS2.

In the dynamic RAM, in response to the fall of the row address strobe signal RASB, first, the selection control signal S02L of the memory array ARY0 corresponding to the row address ra is selectively set to the high level, and the sense amplifiers SA0 and SA1. The internal control signals PC0 and PC1 are set to the low level. The word line W21 of the memory array ARY0 corresponding to the row address ra is alternatively set to the high level after a predetermined time delay, and the internal control signals PA0 and PA1 to the sense amplifiers SA0 and SA1 are set to the high level after a predetermined time delay. To be done.

In the memory array ARY0, in response to the high level of the selection control signal S02L, there are n + 1 switches MO.
The SFETs P2 are turned off all at once, and the switch MOSFETs N2 are turned on all at once instead. Therefore, the non-inverted sub-bit line B2 below each main bit line
0LT to B2nLT are disconnected from the internal voltage supply point HVC, and the corresponding non-inverted main bit line MB0T
~ MBnT connected. Further, to the non-inverted sub-bit line and the non-inverted main bit line, minute read signals according to the held data are output from the n + 1 memory cells coupled to the selected word line W21, and the sense amplifier SA0 is output. Alternatively, it is transmitted to the non-inverting input / output node of the corresponding unit amplifier circuit of SA1. To the inverting input / output nodes of these unit amplifier circuits, the levels of the corresponding inverting main bit lines MB0B to MBnB are transmitted.
These inverted main bit lines are connected to the memory array ARY1.
To none of the sub-bit lines ARY3 are connected, the precharge voltage, that is, the internal voltage HVC of the intermediate potential
Will be transmitted.

On the other hand, in the sense amplifiers SA0 and SA1, there are a total of n + 1 bit line precharge circuits UPC.
0, UPC2 to UPCn-1 and UPC1, U
PC3 to UPCn are internal control signals PC0 and PC
When the low level of 1 is received, the non-inversion main bit lines MB0T to MBnT and the inversion main bit lines MB0B to MBnB are precharged. In addition, a total of n + 1 unit amplifier circuits U
SA0, USA2 to USAn-1 and USA
1, USA3 to USAAn receive the high level of the internal control signals PA0 and PA1, and are brought into operation all at once,
A small potential difference generated between the non-inverted main bit lines MB0T to MBnT and the inverted main bit lines MB0B to MBnB is amplified by the read signal from the selected memory cell to be a high level or low level binary read signal. Thereby, for example, the non-inverted main bit line MB2T of the memory array ARY0 and the memory array ARY1
The potential of the inverted main bit line MB2B is set to the high level or the low level in accordance with the data held in the selected memory cell, and the potential of the non-inverted sub bit line B22LT of the memory array ARY0 is also set to the high level. At this time, sub-bit lines B20UT to B2nUT provided above each main bit line of the memory array ARY0,
Sub bit lines B00UT to B0nUT, B00LT corresponding to the word lines W00 to W0m and W10 to W1m.
-B0nLT and B10UT-B1nUT, B10
LT to B1nLT are kept at the internal voltage HVC, that is, the intermediate potential.

Next, the column address strobe signal CA
When SB is set to the low level, in the dynamic RAM, the bit line selection signal Y corresponding to the column address ca
S2 is alternatively set to a high level at a predetermined timing,
After a predetermined time, the internal control signal OC for the data input / output circuit IO is set to the high level.

In the sense amplifier SA0, the pair of switch MOSFETs N5 and N6 corresponding to the high level of the bit line selection signal YS2 are selectively turned on,
A binary read signal according to the data held in the memory cell arranged at the intersection of the word line W21 and the non-inverting sub-bit line B22LT of the memory array ARY0, that is, (ra.c
a) is alternatively transmitted to the data input / output circuit IO via the complementary common data line CD0 *. This read signal is
After being further amplified by the main amplifier of the data input / output circuit IO, it receives the high level of the internal control signal OC and is output from the data output buffer to the external device via the data output terminal Dout.

In this embodiment, the memory array ARY
As described above, the non-inverted and inverted main bit lines forming 0 to ARY3 are arranged at a high density by using, for example, the first metal wiring layer, and their lengths are sequentially halved in the column direction. To be done. Therefore, for example, as shown in FIG. 4, the selected word line W21 of the memory array ARY0 is selected.
The read signal of the memory cell coupled to is amplified by the corresponding unit amplifying circuit of the sense amplifier SA0, and is generated in the even-numbered non-inverted main bit line MB2T + Δ.
The potential change of V is transmitted to the adjacent non-inverting main bit line MB1T via the parasitic capacitance CS0, and induces + δV noise on the non-inverting main bit line MB1T. However, noise of −δV having the same absolute value is induced on the non-inverted main bit line MB1T from the inverted main bit line MB2B of the memory array ARY1 paired with the non-inverted main bit line MB2T via the parasitic capacitance CS1. Offset each other. On the contrary, the read signal of the memory cell coupled to the selected word line W21 of the memory array ARY0 is amplified by the corresponding unit amplifier circuit of the sense amplifier SA1 to be generated in the odd-numbered non-inverted main bit line MB1T. For example, the potential change of −ΔV is caused by the non-inverted main bit line MB1T adjacent to the adjacent non-inverted main bit line MB1T via the parasitic capacitance CS0.
To the non-inverted main bit line MB1T.
V noise is induced, but the potential change of −ΔV in the non-inverted main bit line MB1T similarly induces −δV, that is, in-phase noise in the paired inverted main bit line MB2B via the parasitic capacitance CS1. . As is well known, the amplification operation by the unit amplifier circuit USA2 of the sense amplifier SA0 is so-called differential amplification, and the in-phase noise transmitted to the non-inverting and inverting input / output nodes is not amplified.

On the other hand, the non-inverted and inverted sub-bit lines forming the memory arrays ARY0 to ARY3 are densely arranged at a pitch of one half of the main bit lines using the polysilicon layer, as described above. Further, these sub-bit lines form two pairs corresponding to each main bit line, and one of them is selectively connected to the corresponding main bit line, and the other potential is internally The voltage HVC is fixed at an intermediate potential between the power supply voltage of the circuit and the ground potential. Therefore, for example, as indicated by the dotted line in FIG. 5, the selected non-inverted sub-bit line B22L is selected.
The non-inverting sub-bit lines B22UT and B23UT, which are arranged on both sides of T and whose potential is fixed to the internal voltage HVC, are
The non-inverted bit line B22LT acts as a shield line, so to speak, and suppresses coupling noise to the non-inverted bit line B22LT.

From the above, in the dynamic RAM of this embodiment, the open type array structure is adopted, and although the main bit lines and the sub bit lines are arranged at an extremely high density, the space between adjacent main bit lines and The coupling noise between the sub-bit lines can be sufficiently suppressed and the operation can be stabilized. By adopting the open type array structure, the device structure of the memory cell is simplified as compared with the conventional dynamic RAM adopting the folded bit line system, and the layout pattern of the memory arrays ARY0 to ARY3 is simplified. As described above, the dynamic RAM can be highly integrated. Further, as described above, the coupling noise between the adjacent main bit lines and the sub bit lines is suppressed, and the operation of the dynamic RAM is stabilized, thereby promoting miniaturization of the main bit lines and the sub bit lines, It is possible to further increase the integration of the dynamic RAM.

The operation and effect obtained from the above embodiment are as follows. That is, (1) In a dynamic RAM or the like adopting a hierarchical bit line system, its memory array has a so-called open type array structure in which non-inversion and inversion signal lines of a main bit line are arranged on both sides of a sense amplifier. The advantage of adopting the hierarchical bit line system is that the structure of the memory cell can be simplified and the miniaturization can be achieved to achieve high integration of the memory array. (2) In the above item (1), the lengths of the main bit lines are sequentially halved in the column direction, so that the coupling noises between the adjacent main bit lines can be canceled and suppressed. The effect is obtained. (3) In the above items (1) and (2), the sub-bit lines are arranged at a pitch of one half of the main bit lines, and two sub-bit lines are formed corresponding to the main bit lines, and pairs are formed. By selectively connecting one of the sub-bit lines to the corresponding main bit line and connecting the other to, for example, the intermediate potential supply point, the non-selected sub-bit line shields the selected sub-bit line. The effect that the coupling noise between the sub-bit lines can be suppressed is obtained. (4) According to the above items (1) to (3), it is possible to stabilize the read operation and the write operation and to further increase the integration density of the dynamic RAM adopting the hierarchical bit line system. To be

The invention made by the inventor of the present invention has been specifically described based on the embodiments, but the invention is not limited to the above-mentioned embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in FIG. 1, the dynamic RAM has four memory arrays ARY0 to ARY3 and three sense amplifiers S.
An arbitrary number of memory arrays and sense amplifiers can be provided in units of A0 to SA2. Further, the dynamic RAM can have any bit configuration such as x4 bits or x8 bits, and can take various embodiments such as the block configuration and the names and combinations of activation control signals.

In FIG. 2, memory arrays ARY0-ARY
The number of sub-bit line divisions in RY3 can take any value other than three. Further, the number of sub-bit lines paired with each main bit line may be four so that the layout pitch is, for example, one fourth of the main bit line. Further, in the same drawing, the lengths of the main bit lines are alternately halved, but the shielding effect of the adjacent sub-bit lines is the same when the main bit lines have the same length, as shown in FIG. 7, for example. Is also demonstrated. In FIG. 3, any potential other than the internal voltage HVC can be supplied to the potential supply point to which the non-selected sub bit line is connected. In addition, the memory array A
RY0 to ARY3 can include a predetermined number of redundant elements, and these memory arrays and sense amplifiers SA0 to SA0.
The specific configuration of SA2 and the conductivity type of the MOSFET are not limited by this embodiment. In FIG. 6, the specific time and potential relationship of each activation control signal, internal control signal, word line, etc. is not restricted by this embodiment, and its effective level is also the same.

In the above description, the case where the invention made by the present inventor was mainly applied to the dynamic RAM which is the field of application which was the background of the invention has been described.
The present invention is not limited to this, and can be applied to, for example, various memory integrated circuit devices such as a synchronous DRAM having a dynamic RAM as a basic configuration and a digital system such as a microcomputer incorporating such a memory integrated circuit device. The present invention is widely applicable to at least a semiconductor memory device adopting a hierarchical bit line system and an apparatus or system including such a semiconductor memory device.

[0046]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, in a dynamic RAM or the like adopting the hierarchical bit line system, its memory array is
The so-called open type array structure in which the non-inverted and inverted signal lines of the main bit line are arranged on both sides of the sense amplifier is used, and the length of the main bit line is sequentially halved in the column direction. In addition, the sub-bit lines are arranged at a pitch of one half of the main bit lines, and two sub-bit lines are formed corresponding to the main bit lines, and one of the two sub-bit lines forming the pair is selectively formed. The corresponding main bit line is connected, and the other is connected to, for example, an intermediate potential supply point. This allows
The structure of the memory cell can be simplified, the memory array can be highly integrated by miniaturization, the coupling noises between adjacent main bit lines can be canceled by each other, and the sub bit lines in the non-selected state can be canceled. As a result, the selected sub-bit line can be shielded and the coupling noise between the sub-bit lines can be suppressed. As a result, while achieving the effect of adopting the hierarchical bit line system, it is possible to achieve higher integration of the dynamic RAM adopting the hierarchical bit line system and to stabilize its operation.

[Brief description of drawings]

FIG. 1 is a block diagram showing one embodiment of a dynamic RAM to which the present invention is applied.

2 is an array configuration diagram showing a first embodiment of the dynamic RAM of FIG. 1. FIG.

3 is a partial circuit diagram showing an embodiment of a memory array and a sense amplifier included in the dynamic RAM of FIG.

FIG. 4 is a conceptual diagram for explaining noise interference between main bit lines of the memory array of FIG.

5 is a conceptual diagram for explaining a shield effect by adjacent sub-bit lines of the memory array of FIG.

FIG. 6 is a signal waveform diagram showing an embodiment of the dynamic RAM of FIG.

FIG. 7 is an array configuration diagram showing a second embodiment of a dynamic RAM to which the present invention is applied.

[Explanation of symbols]

ARY0 to ARY3 ... Memory array, XD0 to XD3
... X address decoder, XB ... X address buffer, SA0-SA2 ... sense amplifier, YD ... Y address decoder, YB ... Y address buffer, CD0 *
~ CD2 * ... Complementary common data line, IO ... Data input / output circuit, TG ... Timing generation circuit. W00-W0
m, W10-W1m, W20-W2m, W30-W3
m, W40 to W4m, W50 to W5m ... Word line, B
0U * to BnU *, B0L * to BnL * ... Non-inverting and inverting sub-bit lines, MB0 * to MBn * ... Non-inverting and inverting main bit lines. USA0-USAn ... Unit amplification circuit, UPC0-UPCn ... Unit precharge circuit,
B00U * to B0nU *, B10U * to B1nU *, B
20U * to B2nU * ... non-inverting and inverting sub-bit lines, P1 to P4 ... P-channel MOSFET, N1 to
N4 ... N-channel MOSFET. RAS ... row address strobe signal, CASB ... column address strobe signal, WEB ... write enable signal, A
0 to Ai …… Address input terminal, Dout …… Data output terminal.

Claims (8)

[Claims] 1. A main bit line whose non-inversion and inversion signal lines are arranged on both sides of a sense amplifier, and a plurality of non-inversion or inversion of corresponding main bit lines which are arranged in the extension direction of these main bit lines. A semiconductor memory device comprising: a sub-bit line that is selectively connected to a signal line. 2. The semiconductor memory device according to claim 1, wherein the lengths of the main bit lines are sequentially halved alternately. 3. The sub-bit lines are arranged at a pitch of one half of the main bit lines and are paired to accommodate two main bit lines each, and one of each pair is selected. 3. The main bit line according to claim 1, wherein the main bit line is connected to the corresponding main bit line.
Semiconductor storage device. 4. When one of the pair of two sub-bit lines is connected to the corresponding main bit line, the other is connected to a predetermined potential supply point. Item 3. The semiconductor memory device according to item 3. 5. A plurality of main bit lines and a plurality of pairs of main bit lines are arranged at a pitch of ½ of these main bit lines and in the extension direction thereof, and any one of the pairs is selected as a corresponding main bit line. And a sub-bit line that is electrically connected to the semiconductor memory device. 6. When one of the pair of two sub-bit lines is connected to the corresponding main bit line, the other is connected to a predetermined potential supply point. Item 5. The semiconductor memory device according to item 5. 7. The main bit line is characterized in that its non-inverted and inverted signal lines are arranged on both sides with a sense amplifier in between, and its length is alternately halved. The semiconductor memory device according to claim 5 or 6. 8. The semiconductor memory device is a dynamic RAM, and a predetermined internal voltage which is an intermediate potential between a power supply voltage of the circuit and a ground potential is supplied to the potential supply point. The semiconductor memory device according to claim 1, claim 2, claim 3, claim 4, claim 5, claim 6, or claim 7.