JP3276452B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, for example, a dynamic RAM (Random Access Mem) having a bit line precharge circuit.
ory: a random access memory).

[0002]

2. Description of the Related Art A memory array including a word line and a complementary bit line arranged orthogonally and a dynamic memory cell arranged in a lattice at an intersection of the word line and the complementary bit line, and a complementary bit line are supported. There is a dynamic RAM provided with a sense amplifier including a unit amplifier circuit provided as such. In these dynamic RAMs, as illustrated in FIG. 8, the sense amplifiers substantially correspond to complementary bit lines B00 * to B0n * and B10 * to B1n * (here, for example, non-inverting bit lines B00T and B00T). The inverted bit line B00B is also indicated by asterisks (*), like a complementary bit line B00 *, and the names of so-called non-inverted signal lines that are selectively set to a high level when they are enabled. , And a so-called inverted signal line or the like which is selectively set to a low level when the signal is valid is denoted by suffixed with B. The same applies hereinafter. N-channel type precharge M provided between inverted signal lines
OSFET (Metal Oxide Semiconductor)
ductor Field Effect Transi
Stor: metal oxide semiconductor field effect transistor.
In this specification, MOSFETs are collectively referred to as an insulated gate field effect transistor) N9, and substantially between a non-inverted and inverted signal line of a corresponding complementary bit line and a precharge potential supply point HV, respectively. A bit line precharge circuit including N channel type precharge MOSFETs N7 and N8 is provided.

A dynamic RAM having a bit line precharge circuit is disclosed, for example, in Japanese Patent Laid-Open No. Hei 3-2146.
No. 69, etc.

[0004]

In the conventional dynamic RAM as described above, a precharge MOSFET N7 constituting a bit line precharge circuit is used.
Precharge control signal PC supplied to the gates of N9 to N9
0, etc., as shown in FIG. 9, when the row address strobe signal RASB is at a low level and the dynamic type R
When AM is selected, the ground potential of the circuit, ie, 0
V, and the row address strobe signal RASB is set to the high level, and the dynamic RAM
Is set to an effective level such as power supply voltage VCC when is set to a non-selected state. When the precharge control signal PC0 or the like is set to an effective level, the bit line precharge circuit
The precharge MOSFETs N7 to N9 are simultaneously turned on. As a result, these precharge MOSFETs
, The non-inverting and inverting signal lines of the bit lines B00 * to B0n * are short-circuited and precharged, and the power supply voltage VCC
And a precharge potential HV such as an intermediate potential between the ground potentials of the circuit.

However, as the power supply voltage VCC of the dynamic RAM has been lowered, the inventors of the present application have found that the following problems occur in the above-mentioned conventional bit line precharge circuit. . That is, in the conventional bit line precharge circuit, as described above, the effective level of the precharge control signal PC0 and the like is set to the power supply voltage VCC, and the precharge MOSFETs N7 to N7
9, a gate-source voltage corresponding to the potential difference between the power supply voltage VCC and the precharge potential HV is applied. As is well known, the conductance of a MOSFET increases in proportion to the difference between its gate-source voltage and its threshold voltage. When the power supply voltage VCC of the dynamic RAM is lowered and the potential difference between the power supply voltage VCC and the precharge potential HV is reduced, the conductance of the precharge MOSFETs N7 to N9 is correspondingly reduced, and the complementary bit line by the precharge MOSFET is reduced. Precharge operation becomes slow. As a result,
The read operation margin of the dynamic RAM is reduced, the access time is delayed, and lowering the voltage of the dynamic RAM is restricted.

On the other hand, in order to cope with this, the present inventors set the effective level of the precharge control signal PC0 and the like to a high voltage VCH corresponding to the word line selection level and reduce the power supply voltage VCC to a lower voltage. But precharge MOS
A method of keeping the gate-source voltages of the FETs N7 to N9 at a relatively large value was considered. However, a signal line transmitting the precharge control signal PC0 and the like includes a complementary bit line B
The gates of the precharge MOSFETs N7 to N9, which are three times the number of sets n + 1 such as 00 * to B0n *, are coupled, and a relatively large parasitic capacitance corresponding to the gate capacitance of these MOSFETs is coupled. Therefore, the dynamic type R
When AM is selected again, a relatively long time is required until the potential of the precharge control signal PC0 or the like is reduced from the high voltage VCH to the ground potential of the circuit, thereby turning off the precharge MOSFETs N7 to N9. State transition to slow, dynamic RAM
Access time is slowed down.

An object of the present invention is to realize a semiconductor memory device such as a dynamic RAM capable of performing an equalizing operation of complementary bit lines and the like at high speed and reliably even when a power supply voltage is lowered. Another object of the present invention is
It is an object of the present invention to suppress the effect of lowering the power supply voltage on a read operation margin and access time of a dynamic RAM or the like, and to promote a lower voltage of a dynamic RAM or the like.

[0008] The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0009]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. More specifically, a dynamic RAM including a plurality of memory arrays selectively activated according to a predetermined array selection signal and a plurality of sense amplifiers provided corresponding to these memory arrays and including a bit line precharge circuit And the like, the effective level of the precharge control signal supplied to the gate of the precharge MOSFET constituting the bit line precharge circuit is set to a selected state in such a manner that a dynamic RAM or the like activates a corresponding memory array. Immediately after being set to a non-selected state, a predetermined high voltage corresponding to the selected level of the word line is set,
The power supply voltage of the circuit is used from the time when the dynamic RAM or the like is again selected to the time when the corresponding memory array is activated.

[0010]

According to the above means, when the dynamic RAM or the like is initially set to the non-selected state, the precharge MOSFET
, The equalizing operation of the complementary bit line can be performed quickly and reliably, and the time from when the dynamic RAM or the like is again selected to when the corresponding memory array is activated is activated. During that time, the potential of the precharge control signal is reduced to the power supply voltage of the circuit, and the time from when the corresponding memory array is activated to when the precharge MOSFET is turned off can be reduced. As a result, even when the power supply voltage is reduced, the equalizing operation of the complementary bit lines and the like can be performed quickly and reliably, and the read signal level can be increased. The influence on the read operation margin and the access time can be suppressed, and lowering the voltage of a dynamic RAM or the like can be promoted.

[0011]

FIG. 1 is a block diagram showing one embodiment of a dynamic RAM to which the present invention is applied. FIG. 2 is a circuit diagram of one embodiment of a memory array ARY0 included in the dynamic RAM of FIG. 1, and FIG. 3 is an embodiment of a sense amplifier SA0 included in the dynamic RAM of FIG. An example circuit diagram is shown. An outline of the configuration and operation of the dynamic RAM according to the present embodiment and the features thereof will be described with reference to these drawings. The circuit elements shown in FIGS. 2 and 3 and the circuit elements constituting each block shown in FIG. 1 are formed on a single semiconductor substrate such as single crystal silicon by a known MOSFET integrated circuit manufacturing technique. . Further, in the following circuit diagrams, MOSFETs having an arrow at the channel (back gate) portion are of a P-channel type, and are distinguished from N-channel MOSFETs without an arrow.
Further, the specific configurations of the memory array and the sense amplifier can be advanced by taking the memory array ARY0 of FIG. 2 and the sense amplifier SA0 of FIG. 3 as examples, but other memory arrays ARY1 to ARY7 and the sense amplifiers SA1 to SA1
Since A3 has the same configuration, it should be analogized.

In FIG. 1, the dynamic RAM of this embodiment employs a so-called shared sense system, and includes a total of eight memory arrays ARY0-ARY7 arranged so as to sandwich corresponding sense amplifiers SA0-SA3. And

The memory arrays ARY0 to ARY7 are shown in FIG.
Of the memory array ARY0, m + 1 word lines W arranged in parallel in the vertical direction in FIG.
00 to W0m (here, the word lines forming the memory array ARY0 are referred to as W00 to W0m, and the word lines forming the other memory arrays ARY1 to ARY7 are W1 respectively.
0 to W1m to W70 to W7m. Hereinafter, the same applies to complementary bit lines and the like) and n + 1 sets of complementary bit lines B00 * to B0n * arranged in parallel in the horizontal direction. At the intersection of the word line and the complementary bit line, an information storage capacitor Cs and an address selection MOSF
(M + 1) × (n + 1) dynamic memory cells composed of ETQa are arranged in a lattice.

Address selection MOSFET of n + 1 memory cells arranged in the same row of memory array ARY0
The gates of Qa are commonly coupled to corresponding word lines W00-W0m. Further, the address selection MO of (m + 1) memory cells arranged in the same column of the memory array ARY0.
The drain of the SFET Qa is connected to the corresponding complementary bit line B0.
Non-inverted or inverted signal lines of 0 * to B0n * are alternately coupled with a predetermined regularity. A predetermined plate voltage VP is supplied to the other electrodes of the information storage capacitors Cs of all the memory cells constituting the memory array ARY0.

The word lines W00 to W0m to W70 to W7m forming the memory arrays ARY0 to ARY7 are coupled to the corresponding word line drive circuits WD0 to WD7, and are selectively selected. Word line drive circuits WD0-W
D7 has corresponding X address decoders XD0 to XD7.
From the word line selection signals WS00 to WS0m (not shown)
Or WS70 to WS7m are supplied. Further, a predetermined high voltage VCH is supplied from a high voltage generation circuit (not shown), and an internal control signal WX is commonly supplied from the timing generation circuit TG. In this embodiment, the high voltage VCH
Has a positive potential such as +5 V whose absolute value is larger than the absolute value of the power supply voltage VCC by a predetermined value.
Is set to a positive potential such as + 3.3V.

On the other hand, X address decoders XD0 to XD7
, The i-bit internal address signals X0 to Xi-3 excluding the upper three bits are commonly supplied from the X address buffer XB, and the corresponding internal control signals XG0 to XG7 are supplied from the array selection circuit AS, respectively. . An X address signal AX0 to AXi is supplied to one input terminal of the X address buffer XB in a time-division manner via address input terminals A0 to Ai, and a refresh address from a refresh address counter RFC is supplied to the other input terminal. Signals R0 to Ri are supplied. The X address buffer further includes an internal control signal R from the timing generation circuit TG.
EF is supplied, and an internal control signal XL (not shown) is supplied. The internal control signal REF is selectively set to a high level when the dynamic RAM is set to the refresh mode.

When the dynamic RAM is selected in the normal operation mode and the internal control signal REF is at the low level, the X address buffer XB is supplied with the X address signal AX0 supplied through the address input terminals A0 to Ai.
AXi, and when the dynamic RAM is selected in the refresh mode and the internal control signal REF is set to the high level, the refresh address counter RFC
And fetches and holds the refresh address signals R0 to Ri supplied from the internal control signal XL, respectively, and forms the internal address signals X0 to Xi based on the X address signal or the refresh address signal. Among these, although not particularly limited, the internal address signals Xi-2 to Xi of the upper 3 bits are supplied to an array selection circuit AS described later, and the other internal address signals X0 to Xi are supplied.
Xi-3 is the X address decoder XD0 as described above.
To XD7.

The X address decoders XD0 to XD7 are selectively activated by the corresponding internal control signals XG0 to XG7 being set to the high level, and the internal address signals XD0 to XD7 are selectively activated.
0 to Xi-3, and the corresponding word line selection signals WS00 to WS0m to WS70 to WS7m are alternatively set to the high level. Further, the word line driving circuit W
D0 to WD7 are the word line selection signals WS00 to WS0m
In response to the high levels of WS70 to WS7m, the corresponding one word line of the corresponding memory arrays ARY0 to ARY7 is alternatively set to a selection level such as the high voltage VCH. That is, the dynamic RAM of this embodiment is
A so-called static word line selection method is employed, and the operation of selecting the word line is performed by a predetermined high voltage VCH.
Is selectively transmitted to a designated word line.

The array selection circuit AS decodes the internal address signals Xi-2 to Xi of the upper 3 bits supplied from the X address buffer XB, and outputs the internal control signals XG
0 to XG7 and array selection signals AS0 to AS7
High level, and the internal control signals SL0 to SL3 and SR
0 to SR3 are alternatively set to the low level. Among these, the internal control signals XG0 to XG7 are supplied to the corresponding X address decoders XD0 to XD7 as described above, and the internal control signals SL0 to SL3 and SR0 to SR3 are supplied to the corresponding sense amplifiers SA0 to SA3. You. Further, the array selection signals AS0 to AS7 are supplied to a later-described sense amplifier control circuit SC, and the data input / output circuit I
O is supplied. The high level of the internal control signals SL0 to SL3 and SR0 to SR3 is the high voltage VCH, and the low level is 0V.

Next, the even-numbered memory arrays ARY0 to ARY0
Complementary bit lines B00 * to B0n * to B60 * to B6n * constituting ARY6 are coupled to the corresponding unit circuits of the corresponding sense amplifiers SA0 to SA3 on the right side thereof to form odd-numbered memory arrays ARY1 to ARY7. Complementary bit lines B10 * to B1n * to B70 *
B7n * are coupled to the corresponding unit circuits of the corresponding sense amplifiers SA0 to SA3 on the left side. The sense amplifiers SA0 to SA3 receive corresponding internal control signals SL0 to SL3 and SR0 from the array selection circuit AS.
SR3 is supplied. Further, the sense amplifier control circuit SC
From the corresponding precharge control signals PCS0 to PCS3
(First precharge control signal) and PC0 to PC
3 (second precharge control signal) is supplied, and the power supply voltage and the ground potential of the circuit are selectively supplied via common source lines SP and SN (not shown). As described above, the sense amplifier control circuit SC includes the array selection circuit AS.
Supplies the array selection signals AS0 to AS7, supplies the internal control signal R1 from the timing generation circuit TG, and further supplies the high voltage VCH.

The sense amplifier control circuit SC includes array selection signals AS0 to AS7 supplied from the array selection circuit AS.
And precharge control signals PCS0 to PCS0 based on internal control signal R1 supplied from timing generation circuit TG.
S3 and PC0 to PC3 are selectively set to the effective level. In this embodiment, the precharge control signal PC0
PC3 is set to an effective level such as power supply voltage VCC when the dynamic RAM is in the non-selected state, and according to the internal address signals Xi-2 to Xi of the upper three bits when the dynamic RAM is in the selected state. Alternatively, it is set to an invalid level such as the ground potential of the circuit. The precharge control signals PCS0 to PCS3 are set to the high voltage VCH immediately after the dynamic RAM is set to the selected state in a state where the corresponding memory array ARY0 or ARY1 to ARY6 or ARY7 is activated and then to the non-selected state. And the dynamic type RAM is again selected, and the corresponding memory array ARY0 or ARY1 to ARY6 or AR
Until Y7 is activated, it is kept at an effective level such as power supply voltage VCC. Corresponding memory array ARY
0 or ARY1 to ARY6 or ARY7 are activated, the precharge control signals PCS0 to PCS
Numeral 3 is an invalid level such as the ground potential of the circuit. The specific configuration and operation of the sense amplifier control circuit SC will be described later in detail.

The sense amplifiers SA0 to SA3 are, as represented by the sense amplifier SA0 in FIG. 3, complementary bit lines B0 of the corresponding memory arrays ARY0 and ARY1.
0 * to B0n * and n + 1 unit circuits provided corresponding to B10 * to B1n *, each of which includes a P-channel MOSFET P1 and an N-channel MOSFET N1.
Channel MOSFET N1 and P-channel MO
It includes a unit amplifier circuit formed by cross-connecting a pair of CMOS inverters composed of an SFET P2 and an N-channel MOSFET N2. Hereinafter, the sense amplifiers SA0 to SA3 will be specifically described with the sense amplifier SA0 as an example.

The non-inverting and inverting input / output nodes of the unit amplifier circuit constituting each unit circuit of the sense amplifier SA0 have a corresponding N-channel switch MO on the left side thereof.
Coupled to corresponding complementary bit lines B00 * -B0n * of memory array ARY0 via SFETs N3 and N4,
On the right side, the memory array ARY is provided via corresponding N-channel type switch MOSFETs NA and NB.
Coupled to one corresponding complementary bit line B10 * -B1n *. The internal control signal SL0 is commonly supplied to the gates of the switch MOSFETs N3 and N4, and the internal control signal SR0 is commonly supplied to the gates of the switch MOSFETs NA and NB. The sources of the MOSFETs P1 and P2 constituting each unit amplifier circuit are commonly coupled to a common source line SP0, and the MOSFETs N1 and N2
The two sources are commonly coupled to a common source line SN0. As described above, the power supply voltage VCC and the circuit ground potential are selectively supplied to the common source lines SP0 and SN0 when the corresponding memory array ARY0 or ARY1 is activated.

From these facts, each unit amplifier circuit of the sense amplifier SA0 determines whether the internal control signal SR0 is at a high level.
When that is Luo low level, it arranged on the right side Memoria
The corresponding complementary bit line of Ray ARY1 B10 * ~Bln
Is selectively disconnected, and the internal control signal SL0 goes high.
When the level is changed from the bell to the low level , the corresponding complementary bit lines B00 * to B00 * of the memory array ARY0 arranged on the left side are set.
B0n * is selectively disconnected . At this time, each of the unit amplifier circuits is selectively and simultaneously activated by the supply of the power supply voltage VCC and the ground potential of the circuit via the common source lines SP0 and SN0.
N + coupled to a selected word line of 0 or ARY1
A small read signal output from one memory cell via a corresponding complementary bit line is amplified to supply a power supply voltage VCC.
, Or a low level binary read signal such as a circuit ground potential. The internal control signal S
The high level of L0 and SR0 is the high voltage VCH as described above. Therefore, the binary read signals established at the non-inverting and inverting input / output nodes of each unit amplifier circuit of the sense amplifier SA0 are output from the switch MOSFETs N3 and N3.
4 or the corresponding complementary bit lines B00 * -B0n * or B10 * of the memory array ARY0 or ARY1 without being reduced by the threshold voltages of NA and NB.
~ Bln *.

Each unit circuit of the sense amplifier SA further includes a pair of N-channel type switch MOSFETs N5 and N5 provided between the non-inverting and inverting input / output nodes of the unit amplifier circuit and the complementary common data lines CD0 * and CD1 *. N6, and between the non-inverting and inverting input / output nodes of the unit amplifier circuit, that is, substantially corresponding complementary bit lines B
N-channel type precharge MOSFET N9 (first MOSFET) provided between non-inverted and inverted signal lines of 00 * to B0n * and B10 * to B1n *, and complementary bit lines B00 * to B0n * substantially corresponding thereto. And two N-channel precharge MOSFETs N7 (second MOSFET) and N8 (third MOSFET) provided between the non-inversion and inversion signal lines of B10 * to B1n * and the precharge potential supply point HV, respectively. ) Respectively. Among them, the gates of the switch MOSFETs N5 and N6 are commonly coupled in pairs, and the corresponding bit line selection signals YS0 to YSp are supplied from the Y address decoder YD. The precharge control signal PCS0 is commonly supplied to the gate of the precharge MOSFET N9, and the precharge control signal PC0 is commonly supplied to the gates of the precharge MOSFETs N7 and N8. It is needless to say that the bit number p + 1 of the bit line selection signals YS0 to YSp has a relationship of p + 1 = (n + 1) / 2 with respect to the number n + 1 of complementary bit lines of the memory arrays ARY0 and ARY1.

The switch MOSFETs N5 and N6 constituting each unit circuit of the sense amplifier SA0 are selectively and simultaneously turned on by two sets when the corresponding bit line select signals YS0 to YSp are set to the high level. The non-inverting and inverting input / output nodes of the two unit amplifier circuits, that is, the corresponding two of the memory arrays ARY0 or ARY1
Set of complementary bit lines and complementary common data lines CD0 * and CD
1 * is selectively connected. On the other hand, a precharge MO constituting a bit line precharge circuit of each unit circuit
The SFET N9 is selectively and simultaneously turned on when the precharge control signal PCS0 is set to a high level such as the high voltage VCH, and the non-inverting and inverting input / output nodes of the corresponding unit amplifier circuit, that is, the memory array ARY0
Alternatively, the non-inversion and inversion signal lines of the corresponding complementary bit lines of ARY1 are short-circuited. Also, the precharge MOSFET N
7 and N8 are selectively turned on when the precharge control signal PC0 is set to a high level such as the power supply voltage VCC, and the non-inverted and inverted input / output nodes of the corresponding unit amplifier circuit, that is, the memory array ARY0 or ARY1
The precharge potential HV is supplied to the non-inversion and inversion signal lines of the corresponding complementary bit lines. As a result, the active memory array ARY coupled to the sense amplifier SA0
The non-inverted and inverted signal lines of the complementary bit lines B00 * to B0n * or B10 * to B1n * of 0 or ARY1 are equalized and both are precharged to a precharge potential HV such as an intermediate potential of the power supply voltage VCC.

By the way, the precharge MOSFET N9
Precharge control signal PCS0 supplied to the gate of
As described above, immediately after the dynamic RAM is set to the selected state in a state where the corresponding memory array ARY0 is activated and then to the non-selected state, the high voltage VCH
The power supply voltage VCC is maintained from when the dynamic RAM is again selected to when the corresponding memory array ARY0 is activated. Immediately before the equalization by the precharge MOSFETs N7 to N9 is performed, the complementary bit lines B00 * to B0n * and B10 * to B1 of the memory arrays ARY0 and ARY1 are used.
The n * non-inverting and inverting signal lines are at a binary read signal level, that is, a high level such as the power supply voltage VCC or a low level which is the ground potential of the circuit. From these facts, the equalizing effect of the precharge MOSFETs N7 to N9 largely depends on the precharge MOSFET N9 which has a function of short-circuiting the non-inverting and inverting signal lines of each complementary bit line. By setting the supplied precharge control signal PCS0 to an effective level such as the high voltage VCH, the voltage between the gate and the source of the precharge MOSFET N9 is increased, whereby the equalization of each complementary bit line is performed quickly and reliably. It will be. The signal waveforms of the respective parts of the dynamic RAM and the sense amplifiers SA0 to SA0
The equalizing operation by the SA3 bit line precharge circuit will be described later in detail.

The Y address decoder YD supplies an i + 1 bit internal address signal Y0 from the Y address buffer YB.
To Yi, and an internal control signal YG (not shown) from the timing generation circuit TG. The Y address buffer YB is supplied with Y address signals AY0 to AYi via address input terminals A0 to Ai, and an internal control signal YL (not shown) from the timing generation circuit TG.

The Y address buffer YB captures and holds the Y address signals AY0 to AYi supplied in a time-division manner via the address input terminals A0 to Ai in accordance with the internal control signal YL, and stores these Y address signals. Originally, internal address signals Y0 to Yi are formed and supplied to a Y address decoder YD. The Y address decoder YD is selectively activated when the internal control signal YG is set to a high level, and the internal address signals Y0 to Y
i, and decodes the corresponding bit line selection signal YS.
0 to YSp is alternatively set to a high level.

As is clear from the above description, the eight memory arrays ARY0 to ARY7 have the corresponding X address decoders XD0 to XD7 having the internal control signals XG0 to XG7.
That is, the internal address signals Xi-2 to Xi of the upper three bits
i and selectively actuated according to internal control signals SL0 to SL3 and SR0 to SR3, that is, corresponding sense amplifiers SA0 to SA3 in accordance with internal address signals Xi-2 to Xi of upper three bits. By being in the connected state, it is alternatively activated. Two sets of complementary bit lines designated by internal address signals Y0 to Yi are selected from one activated memory array, and two corresponding sets of complementary common data lines CD0 * and CD1 * to CD6 are selected. * And CD7
* Is selectively connected.

Complementary common data lines CD0 * to CD7 *, to which two designated complementary bit lines of memory arrays ARY0 to ARY7 are selectively connected, are coupled to data input / output circuit IO. Data input / output circuit IO is provided corresponding to complementary common data lines CD0 * to CD7 *.
Write amplifiers and main amplifiers, and 1
Data input buffers and data output buffers. Among these, the output terminal of each write amplifier and the input terminal of each main amplifier are connected to the corresponding complementary common data line CD0.
* To CD7 *, respectively. On the other hand, the input terminal of each write amplifier is commonly coupled to the output terminal of the data input buffer, and the input terminal of this data input buffer is coupled to the data input terminal Din. The output terminal of each main amplifier is commonly coupled to the input terminal of the data output buffer, and the output terminal of the data output buffer is coupled to the data output terminal Dout. Each write amplifier is commonly supplied with an internal control signal WP (not shown) from a timing generation circuit TG, and receives corresponding array selection signals AS0 to AS7 from an array selection circuit AS.
Are supplied respectively. The data output buffer is supplied with an internal control signal DOC (not shown) from the timing generation circuit TG, and the array selection circuit AS
Supplies the array selection circuits AS0 to AS7.

The data input buffer of the data input / output circuit IO receives the write data supplied via the data input terminal Din when the dynamic RAM is selected in the write mode, and is shared by the eight write amplifiers. To communicate. At this time, each of the write amplifiers is selectively activated by setting the internal control signal WP to the high level and the corresponding array selection signals AS0 to AS7 to the high level, and is transmitted from the data input buffer. The write data is a predetermined complementary write signal. These complementary write signals are supplied from a single write amplifier which is brought into operation to a corresponding set of complementary common data lines CD0 to CD0.
The data is transmitted to the selected memory cell of the memory arrays ARY0 to ARY7 via the CD7 * and written.

On the other hand, when the dynamic RAM is selected in the read mode, the main amplifier of the data input / output circuit IO outputs the corresponding complementary common data line from the two selected memory cells of the memory arrays ARY0 to ARY7. The binary read signal output via CD0 * to CD7 * is further amplified and transmitted to the data output buffer. At this time, the data output buffer outputs the internal control signal D
When OC is set to the high level, it is selectively activated, and the corresponding 1 according to the array selection signals AS0 to AS7.
The read signals output from the main amplifiers are alternatively selected and sent out of the dynamic RAM via the data output terminal Dout.

The timing generation circuit TG selectively forms the various internal control signals based on a row address strobe signal RASB, a column address strobe signal CASB, and a write enable signal WEB supplied from outside as a start control signal. , And to each part of the dynamic RAM.

FIG. 5 is a block diagram showing one embodiment of the sense amplifier control circuit SC included in the dynamic RAM of FIG. FIG. 6 is a circuit diagram of one embodiment of the unit sense amplifier control circuit USC0 included in the sense amplifier control circuit SC of FIG. 5, and FIG.
1 is a signal waveform diagram of one embodiment of the dynamic RAM. With reference to these figures, the specific configuration and operation of the sense amplifier control circuit SC included in the dynamic RAM of this embodiment and the features thereof will be described. The unit sense amplifier control circuits USC0 to USC
3 will be described below.
SC0 is taken as an example, but analogy should be made for the other unit sense amplifier control circuits USC1 to USC3.

Referring to FIG. 5, sense amplifier control circuit SC
Includes four unit sense amplifier control circuits USC0 to USC3 provided corresponding to the sense amplifiers SA0 to SA3. The internal control signal R1 and the high voltage VCH are commonly supplied to these unit sense amplifier control circuits, and the corresponding two-bit array selection signals AS0 and A
S1 to AS6 and AS7 are supplied respectively. The output signal of unit sense amplifier control circuit USC0 is supplied to corresponding sense amplifier SA0 as precharge control signals PCS0 and PC0, and the output signals of unit sense amplifier control circuits USC1 to USC3 are precharge control signals PCS1 to PCS3 and PC1. ＰＣPC3 are supplied to the corresponding sense amplifiers SA1 to SA3.

As shown in FIG. 7, the internal control signal R1 is selectively turned to a high level in response to a low level change of the row address strobe signal RASB. Further, the dynamic RAM is selectively selected by setting the row address strobe signal RASB to a low level and setting the internal control signal R1 to a high level. To the address input terminals A0 to Ai, X address signals AX0 to AXi are supplied in synchronism with the first falling edge of the row address strobe signal RASB, for example, in a combination designating the word line W00 of the memory array ARY0, The Y address signals AY0 to AYi are supplied in a combination designating a predetermined complementary bit line in synchronization with the first falling edge of the strobe signal CASB. Also, the row address strobe signal RASB 2
In synchronism with the second falling edge, for example, a combination specifying the word line W30 of the memory array ARY3 is set to X
The address signals AX0 to AXi are supplied, and the Y address signals AY0 to AYi are supplied in a combination that designates another predetermined complementary bit line in synchronization with the second falling edge of the column address strobe signal CASB.

In the dynamic RAM, upon receiving the first low-level change of the row address strobe signal RASB, that is, the first high-level change of the internal control signal R1,
The internal control signal SR0 corresponding to the memory array ARY1 is
It is set to the low level, and the memory array is
I ARY1 is disconnected and the memory array ARY
The array selection circuit AS0 corresponding to 0 is set to a high level like the power supply voltage VCC. At a predetermined timing, the word line W00 of the memory array ARY0 specified by the X address signals AX0 to AXi is alternatively supplied with the high voltage VC.
The power supply voltage VCC and the ground potential of the circuit are supplied to the common source lines SP0 and SN0 with a selection level such as H.

Thus, the complementary bit lines B00 * to B0n * of the memory array ARY0 are connected to the corresponding unit circuits of the sense amplifier SA0, and each complementary bit line is connected to the selected word line W00 of the memory array ARY0. A minute readout signal is output from the (n + 1) memory cells according to the held data. These minute read signals are supplied to the common source lines SP0 and SN0 by the power supply voltage V
When the CC and the ground potential of the circuit are supplied, the signal is amplified by the corresponding unit amplifier circuit of the sense amplifier SA0, and becomes a high-level or low-level binary read signal.

Next, the row address strobe signal RAS
B for the second low level change, that is, the internal control signal R1
Of the memory array AR
When the internal control signal SL1 corresponding to Y4 is
And the memory array ARY4 is disconnected from the sense amplifier SA1.
At the same time, the array selection circuit AS3 corresponding to the memory array ARY3 is set to a high level such as the power supply voltage VCC. The memory array ARY3 specified by the X address signals AX0 to AXi at a predetermined timing
Is set to a selection level such as the high voltage VCH, and the common source lines SP1 and S
The power supply voltage VCC and the ground potential of the circuit are supplied to N1.

As a result, the complementary bit lines B00 * to B0n * of the memory array ARY3 are connected to the corresponding unit circuits of the sense amplifier SA1, and each complementary bit line is connected to the selected word line W30 of the memory array ARY3. A minute readout signal is output from the (n + 1) memory cells according to the held data. These minute read signals are supplied to the common source lines SP1 and SN1 by the power supply voltage V
When the CC and the ground potential of the circuit are supplied, they are respectively amplified by the corresponding unit amplifier circuits of the sense amplifier SA1, and become a high-level or low-level binary read signal.

The unit sense amplifier control circuits USC0 to USC3 constituting the sense amplifier control circuit SC
Includes a NOR gate NOG1 for receiving corresponding array select signals AS0 and AS1, as representatively shown in unit sense amplifier control circuit USC0 of FIG. The output signal of the NOR gate NOG1 becomes a precharge control signal PC0 after passing through two inverters V6 and V7. As a result, as shown in FIG. 7, the precharge control signal PC0 is turned on when the array selection signals AS0 and AS1 are both at the low level, in other words, the memory arrays ARY0 and ARY1 corresponding to the sense amplifier SA0.
Are not in the active state, they are set to an effective level such as the power supply voltage VCC, and when the array selection signal AS0 or AS1 is set to the high level, that is, when the corresponding memory array ARY0 or ARY1 is activated, An invalid level such as the ground potential of the circuit.

The unit sense amplifier control circuit USC0 further includes P-channel MOSFETs P3 and P4 and N
It includes a clocked inverter CN1 composed of channel MOSFETs NC and ND. The internal control signal R1 is supplied to the gate of the MOSFET ND constituting the clocked inverter CN1, and the inverted signal of the inverter V1 is supplied to the gate of the MOSFET P3. The output signal of the NOR gate NOG1 is commonly supplied to the gates of the MOSFETs P4 and NC, and the output signal, that is, the potential at the commonly coupled drains of the MOSFETs P4 and NC is set to two inverters V2 and V3.
And V3 are supplied to an input node of a latch circuit LT1 which is cross-coupled.

Thus, the clocked inverter CN1
Are selected when the internal control signal R1 is at a high level and the output signal of the NOR gate NOG1 is at a low level, in other words, the dynamic RAM activates the corresponding memory array ARY0 or ARY1. And the output signal of the latch circuit LT1 is selectively set to the low level when the output signal of the clocked inverter CN1 is set to the high level. The array selection signal A
S0 to AS7 are alternatively set to the high level after the internal control signal R1 is set to the high level, and are returned to the low level after the internal control signal R1 is set to the low level. Therefore, latch circuit LT including inverters V2 and V3
The output signal of 1 remains at the low level until the dynamic RAM is selected by activating the other memory arrays ARY2 to ARY7.

The output signal of latch circuit LT1 is supplied to one input terminal of NOR gate NOG2. The other input terminal of the NOR gate NOG2 has a NAND gate NA.
The output signal of G1 is supplied. One input terminal of the NAND gate NAG1 is connected to the inverter V of the internal control signal R1.
1 and an output signal of the NOR gate NOG1 is supplied to the other input terminal. Thus, the output signal of the NAND gate NAG1 is output from the inverter V
1 and the output signal of the NOR gate NOG1 are both at the high level, in other words, the dynamic RA
When M is in the non-selected state and the memory array ARY0 or ARY1 is not in the active state, it is selectively set to the low level. The output signal of the NOR gate NOG2 is output when both the output signal of the NAND gate NAG1 and the output signal of the latch circuit LT1 are at low level, that is, the dynamic type R
The AM is set to the high level immediately after being set to the selected state in the form of activating the corresponding memory array ARY0 or ARY1 and then to the non-selected state, and returned to the low level by being set to the selected state again.

The output signal of the NOR gate NOG2 is supplied to a latch circuit LT2 composed of a pair of NOR gates NOG3 and NOG4 using the high voltage VCH as an operating power supply. The output signal of the latch circuit LT2 is a P-channel MOSF
The high voltage VCH is supplied to the gate of ETP5.
Is supplied to the gate of a P-channel MOSFET P7 via an inverter V8 having an operating power supply. MOSFET
The source of P5 is coupled to power supply voltage VCC, and its drain is coupled to the circuit ground via P-channel MOSFET P6 and N-channel MOSFET NE. The gates of these MOSFETs P6 and NE are:
An inverted signal of the output signal of the NOR gate NOG1 by the inverter V5 is supplied, and the potential of the commonly coupled drain becomes the precharge control signal PCS0. On the other hand, the source of the MOSFET P7 is coupled to the high voltage VCH, and the source is commonly coupled to the drains of the MOSFETs P6 and NE, that is, the precharge control signal line PCS0.

As described above, the output signal of the NOR gate NOG2, that is, the latch circuit LT2 is a dynamic RAM
Are set to the high level immediately after the corresponding memory array ARY0 or ARY1 is set to the selected state and then to the non-selected state in the active state, and returned to the low level by being set to the selected state again. When the output signal of the NOR gate NOG2, that is, the latch circuit LT2 is at a high level, M
OSFET P5 is turned off, and MOSFET P7 is turned on. Therefore, the high voltage VCH is connected to the precharge control signal line PCS0 via the MOSFET P7.
Is supplied, and the precharge control signal PCS0 is
It becomes an effective level like CH. On the other hand, NOR gate NO
When G2, that is, the output signal of the latch circuit LT2 is at a low level, the MOSFET P7 is turned off, and the MOSFET P5 is turned on instead. At this time,
While both the memory arrays ARY0 and ARY1 are not activated and the output signal of the NOR gate NOG1 is at high level, the MOSFET P6 is turned on and the precharge control signal PCS0 is at an effective level like the power supply voltage VCC. When the memory array ARY0 or ARY1 is activated again, the MOSFET NE is turned on instead, and the precharge control signal PCS0 becomes an invalid level such as the ground potential of the circuit.

As a result, the precharge control signal PC
S0 is a dynamic RAM as shown in FIG.
Is set to the selected state by activating the corresponding memory array ARY0 or ARY1 to an invalid level such as the ground potential of the circuit. And dynamic type R
The AM is set to a valid state such as the high voltage VCH immediately after the AM is set to the selected state in the form of activating the corresponding memory array ARY0 or ARY1 and then to the non-selected state, and the dynamic RAM is again set to the selected state. As a result, an effective level such as the power supply voltage VCC is set.

When the precharge control signal PCS0 is high voltage V
When set to CH, in the sense amplifier SA0, a precharge MOSFET constituting a bit line precharge circuit
N9 is turned on, whereby the memory array AR
The non-inverted and inverted signal lines of the complementary bit lines B00 * to B0n * of Y0 are short-circuited. At this time, the precharge control signal PC0 is set to a high level such as the power supply voltage VCC, and the other precharge MOSFE of the sense amplifier SA0.
TN7 and N8 are also turned on. Therefore, the non-inverted and inverted signal lines of the complementary bit lines B00 * to B0n * of the memory array ARY0 are connected to the precharge MOSFET N9.
And the precharge MOSFET N
When N7 and N8 are turned on, they are quickly precharged to the precharge potential HV and equalized.

As is well known, the conductance of a MOSFET increases in proportion to the difference between its gate-source voltage and its threshold voltage. Also, the sense amplifiers SA0 to SA0
In the bit line precharge circuit of SA3, the effect of the precharge MOSFET N9 for short-circuiting the non-inverting and inverting signal lines of the corresponding complementary bit line is particularly great.
The equalizing operation is sped up by increasing the conductance of the ETN 9. As described above, in this embodiment, the precharge control signals PCS0 to PCS3 corresponding to the memory array which has been activated immediately after the dynamic RAM is brought into the non-selected state are selectively applied to the high voltage VCH. The effective level is set. Therefore, the voltage between the gate and the source of the corresponding precharge MOSFET N9 increases by the potential difference between the high voltage VCH and the power supply voltage VCC, and the conductance of the precharge MOSFET N9 increases accordingly, and the equalizing operation by the bit line precharge circuit is performed. Is speeded up.

On the other hand, precharge control signals PCS0-P
CS3 is returned to the power supply voltage VCC when the dynamic RAM is selected again, and is set to an invalid level such as the ground potential of the circuit when the corresponding memory arrays ARY0 to ARY7 are activated again. . Therefore, in the bit line precharge circuits of the sense amplifiers SA0 to SA3, first, the precharge control signal PC
By setting S0 to PCS3 to the power supply voltage VCC, the conductance of the precharge MOSFET N9 is slightly reduced, and the precharge control signals PCS0 to PCS3 are further reduced.
Is set to the ground potential of the circuit, whereby the circuit is completely turned off. That is, in the dynamic RAM of this embodiment,
When the precharge control signals PCS0 to PCS3 are high voltage VC
H and the equalizing operation by the bit line precharge circuit is accelerated, but the dynamic RA
Precharge MO by M being selected again
Since the state transition of the SFET N9 to the off state is accelerated, the influence on the access time of the dynamic RAM due to the high voltage VCH of the precharge control signals PCS0 to PCS3 is suppressed.

As a result, in the dynamic RAM of this embodiment, the complementary bit lines B00 * to B0 are provided despite that the power supply voltage VCC is lowered to + 3.3V.
The equalizing operation of n * to B70 * to B7n * can be performed quickly and reliably, and a sufficient read signal level can be obtained in each complementary bit line. As a result, the effect of lowering the power supply voltage VCC on the read operation margin and access time of the dynamic RAM can be suppressed, and the lowering of the voltage of the dynamic RAM can be promoted.

As shown in the present embodiment, by applying the present invention to a semiconductor memory device such as a dynamic RAM having a bit line precharge circuit, the following operation and effect can be obtained. That is, (1) a plurality of memory arrays selectively activated according to a predetermined array selection signal, and a plurality of sense amplifiers provided corresponding to these memory arrays and including a bit line precharge circuit. Dynamic RAM
In such a case, the effective level of the precharge control signal supplied to the gate of the precharge MOSFET constituting the bit line precharge circuit is set to a predetermined high voltage corresponding to the selected level of the word line.
By increasing the voltage between the gate and the source of the FET, it is possible to obtain an effect that the equalizing operation of the complementary bit line by these precharge MOSFETs can be performed quickly and reliably.

(2) In the above item (1), the effective level of the precharge control signal is set to a selected state in such a manner that a memory array corresponding to a dynamic RAM or the like is activated, and then to a non-selected state. Immediately thereafter, a predetermined high voltage corresponding to the word line selection level is set, and the dynamic RA
By setting the power supply voltage of the circuit between the time when M and the like are again selected and the time when the corresponding memory array is activated, the corresponding memory array is activated after the dynamic RAM or the like is again selected. Until the state is changed, the potential of the precharge control signal is reduced to the power supply voltage of the circuit, and the time from when the corresponding memory array is activated to when the precharge MOSFET is turned off is shortened. The effect that it can be obtained is obtained. (3) According to the above items (1) and (2), even when the power supply voltage is lowered, the equalizing operation of the complementary bit lines and the like can be performed quickly and reliably, and a sufficient read signal level can be obtained. The effect is obtained. (4) By the above items (1) to (3), the effect of lowering the power supply voltage on the read operation margin and access time of a dynamic RAM or the like is suppressed, and the lowering of the voltage of a dynamic RAM or the like is promoted. The effect that it can be obtained is obtained.

Although the invention made by the inventor has been specifically described based on the embodiments, the invention is not limited to the above-described embodiments, and various modifications can be made without departing from the gist of the invention. Needless to say, there is. For example, in FIG. 1, the dynamic RAM can adopt a so-called multi-bit configuration in which a plurality of bits of storage data are simultaneously input or output. At this time, when the dynamic RAM has a so-called × 8-bit configuration and read signals are transmitted all at once via all the complementary common data lines CD0 * to CD7 *, that is, the sense amplifier SA0
In the case where .about.SA3 are always operated simultaneously, all the precharge control signals PCS0 to PCS3 may be changed in level as described above. The dynamic RAM does not require the use of the shared sense system and the address multiplex system, and its block configuration, the combination of the start control signal and the address signal, and the like can take various embodiments.

In FIG. 3, the dynamic RAM is
One set of complementary common data lines can be provided corresponding to each sense amplifier, or four or more sets of complementary common data lines can be provided. MOSFETs N7 to N7 forming bit line precharge circuits of sense amplifiers SA0 to SA3
9 are all connected to the gate as shown in FIG.
May be received. Further, various embodiments can be adopted for the specific circuit configuration of the memory array, the sense amplifier, the unit sense amplifier control circuit, the polarity and absolute value of the power supply voltage, the conductivity type of the MOSFET, and the like shown in FIGS. 2 to 6. .

In FIG. 7, a precharge control signal PC
S0 to PCS3 are high voltage VCs from when the dynamic RAM is deselected to when it is again selected.
However, for example, the high voltage VCH may be temporarily set for a predetermined time after the dynamic RAM is deselected. In this case, the precharge control signal P
CS0 to PCS3 are returned to the power supply voltage VCC without waiting for the dynamic RAM to be set to the selected state again, and the state transition of the precharge MOSFET constituting the bit line precharge circuit to the off state is further accelerated. You. The combination of the start control signal and the address signal in the dynamic RAM and the logic level of each internal control signal are not restricted by this embodiment.

In the above description, the case where the invention made by the present inventor is mainly applied to the bit line precharge circuit of the dynamic RAM, which is the application field as the background, has been described. For example, the present invention can be applied to a precharge circuit such as a complementary common data line or the like, and a multiport memory and a pseudo static RAM having a dynamic RAM as a basic configuration.
And the like, and a logic integrated circuit device incorporating such a memory integrated circuit. INDUSTRIAL APPLICABILITY The present invention can be widely applied to a semiconductor memory device having at least a complementary signal line and a semiconductor device incorporating such a semiconductor memory device.

[0059]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, a plurality of memory arrays selectively activated according to a predetermined array selection signal;
In a dynamic RAM or the like including a plurality of sense amplifiers including a bit line precharge circuit provided corresponding to these memory arrays, a precharge control supplied to the gate of a precharge MOSFET constituting the bit line precharge circuit The effective level of the signal is set to a predetermined high voltage corresponding to the selected level of the word line immediately after the dynamic RAM or the like is set to the selected state in a state where the corresponding memory array is activated and then to the non-selected state, The power supply voltage of the circuit is used from the time when the dynamic RAM or the like is again selected to the time when the corresponding memory array is activated. As a result, when the dynamic RAM or the like is initially set to the non-selected state, the precharge MOSFE
By increasing the voltage between the gate and source of T, the equalizing operation of the complementary bit line can be performed quickly and reliably, and from when the dynamic RAM or the like is again selected to when the corresponding memory array is activated. During this period, the potential of the precharge control signal is reduced to the power supply voltage of the circuit, and the time from when the corresponding memory array is activated to when the precharge MOSFET is completely turned off can be reduced. As a result, even when the power supply voltage is reduced, the equalizing operation of the complementary bit lines and the like can be performed quickly and reliably, and a sufficient read signal level can be obtained. And the like, which affect the read operation margin and the access time, so that the voltage of the dynamic RAM or the like can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a dynamic RAM to which the present invention is applied.

FIG. 2 is a circuit diagram showing one embodiment of a memory array included in the dynamic RAM of FIG. 1;

FIG. 3 is a circuit diagram showing a first embodiment of a sense amplifier included in the dynamic RAM of FIG. 1;

FIG. 4 is a circuit diagram showing a second embodiment of the sense amplifier included in the dynamic RAM of FIG. 1;

FIG. 5 is a block diagram showing one embodiment of a sense amplifier control circuit included in the dynamic RAM of FIG. 1;

FIG. 6 is a circuit diagram showing one embodiment of a unit sense amplifier control circuit included in the sense amplifier control circuit of FIG. 5;

FIG. 7 is a signal waveform diagram showing one embodiment of the dynamic RAM of FIG. 1;

FIG. 8 is a circuit diagram showing an example of a sense amplifier included in a conventional dynamic RAM.

FIG. 9 is a signal waveform diagram showing an example of a conventional dynamic RAM.

[Explanation of symbols]

ARY0 to ARY7: memory array, WD0 to WD
7 ... word line drive circuit, XD0 to XD7 ... X address decoder, XB ... X address buffer, RF
C: Reference address counter, AS: Array selection circuit, SA0 to SA3: Sense amplifier, S
S: sense amplifier control circuit, YD: Y address decoder, YB: Y address buffer, IO ...
Data input / output circuit, TG ... timing generation circuit. U
SC0 to USC3 ··· Unit sense amplifier control circuit. C
s: information storage capacitor, Qa: address selection MOSFET, P1 to P7: P-channel MOSF
ET, N1 to NE: N-channel MOSFET, V
1 to V8 ... inverter, NAG1 ... NAND (N
AND gates, NOG1 to NOG4... Noah (NO)
R) Gate, LT1 to LT2 ... Latch circuit, CN1
... Clocked inverter.

──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Kiyoshi Nakai 2326 Imai, Ome-shi, Tokyo Inside the Device Development Center, Hitachi, Ltd. (72) Masaya Murana 5-2-1, Josuihoncho, Kodaira-shi, Tokyo (56) References JP-A-5-62463 (JP, A) JP-A-64-46291 (JP, A) JP-A-62-51094 (JP, A) A) (58) Field surveyed (Int. Cl. ⁷ , DB name) G11C 11/409

Claims (6)

(57) [Claims] A first memory cell provided at an intersection of a first word line and a first bit line pair; a second memory cell provided at an intersection of a second word line and a second bit line pair; A pair of common bit lines connected to the first and second bit line pairs; and amplifying a signal read from the first and second memory cells to a first potential or a second potential higher than the first potential. The sense amplifier connected to the common bit line pair, first switch means for controlling connection between the first bit line pair and the common bit line pair, and the second bit line. A second switch for controlling connection between the pair and the common bit line pair; and a pre-switch connected to the common bit line pair for precharging the first and second bit line pairs to a precharge potential. A charge circuit; The storage circuit has an N-type first MOSFET having a source-drain path connected between one and the other of the common bit line pair.
When the precharge circuit is inputted to the gate of the MOSFET and the precharge circuit is put into an operation state, the third potential is set higher than the second potential , and the first or second word line is selected.
When the first or second word is set to the first potential.
When the line is changed from the selected state to the non-selected state, a predetermined time
The third potential, and after the lapse of the predetermined time, the second potential
A semiconductor memory device which is set to a potential . 2. The method according to claim 1, wherein the first and second word lines are connected to the third word line when selected.
A semiconductor memory device which is set to a potential. 3. The precharge circuit according to claim 1, wherein the precharge circuit includes an N-type second MOSFET having a source-drain path connected between one of the common bit line pair and the precharge potential. An N-type third MOSFET having a source-drain path connected between the other of the common bit line pair and the precharge potential; and a gate of the second and third MOSFETs,
A semiconductor memory device to which the control signal common to a MOSFET is input. 4. The device according to claim 1, wherein the first switch is an N-type fourth MOSFET pair, the second switch is an N-type fifth MOSFET pair, The third potential is input to the pair of gates when the first bit line pair and the common bit line pair are connected, and the first bit line pair and the common bit line pair are disconnected. The first potential is input when the state is set, and the third potential is input to the gate of the fifth MOSFET pair when the second bit line pair and the common bit line pair are connected. Wherein the first potential is input when the second bit line pair and the common bit line pair are disconnected. 5. In any one of claims 1 to 4, wherein the pre-charge potential, the semiconductor memory device which is a potential intermediate in the second potential and the first potential. 6. In any one of claims 1 to 5, wherein the first and second memory cell, the semiconductor memory device which is a dynamic memory cell.