JPH0750098A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To access at high speeds while carrying out a normal reading operation by providing, between a common data line and a ground potential of a read amplifier circuit, a leak MOSFET for controlling a high level of the common data line to not higher than a predetermined level. CONSTITUTION:A unit read amplifier URA0 has two N-channel MOSFETs N1 and N2 connected in series between a common data line CD0 and a ground potential of a circuit. A read signal R0 which is an output signal from a differential amplifier circuit DA0 is supplied to a gate of the N1. A gate of the N2 is connected to a drain of the N1. The N1 operates as a leak MOSFET and controls a high level of the common data line CD0 to a predetermined level along with the N2. Accordingly, influences of a parasitic capacitor to the level change can be suppressed, and an accessing speed of a mask ROM or the like is made high.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a technique which is particularly effective when used for a mask ROM (read only memory) or the like.

[0002]

2. Description of the Related Art There is a mask ROM in which fixed holding data is written in a memory cell during manufacturing. The memory cells that have completed writing are assumed to have different threshold voltages according to the held data, and read currents of different values flow when selected. The mask ROM includes a read amplifier that senses and amplifies a read current flowing from the selected memory cell via the corresponding bit line and common data line.

A mask ROM provided with a read amplifier is described, for example, in "Hitachi IC Memory Data Book 1", pages 754 to 761, published by Hitachi, Ltd. in September 1991.

[0004]

In the conventional mask ROM described above, the read amplifier RA has eight units provided corresponding to the common data lines CD0 to CD7 as shown in FIG. 5, for example. Read amplifier URA0
Each unit read amplifier is provided with a URA7, and each unit read amplifier is represented by a unit read amplifier URA0 as represented by an N-channel type charge MOSFET (metal oxide semiconductor field effect transistor. In this specification, MOSFET is used as an insulated gate. Type field effect transistor) N3
And a current sense circuit CS0 having a basic structure of the sense MOSFET N4 and a pair of N-channel differential MOS
Differential amplifier circuit DA based on FETs N8 and N9
0 and so on. The current sense circuit CS0 or the like causes a read current to flow from the charge MOSFET N3 to the selected memory cell via the common data line CD0 or the like, whereby the charge potential of the common data line CD0 or the like is selected according to the held data of the selected memory cell. Is set to a predetermined high level or low level. The potential of the common data line CD0 or the like is sensed and amplified by the sense MOSFET N4. As a result, the potential at the output terminal Va0 or the like of the current sense circuit CS0 or the like is selectively set to the high level or the low level. The output signal of the current sense circuit CS0 or the like, that is, the potential at the output terminal Va0 is compared and amplified with the reference potential VR by the corresponding differential amplifier circuit DA0 or the like, and becomes the read signal R0 or the like.

By the way, the sense MOSFET N4 such as the current sense circuit CS0 has a NAND gate N at its gate.
An N-channel type reset MOSFET N5 that receives the output signal of A1, that is, the internal signal CA is provided in parallel. Further, between the drains of the MOSFETs N4 and N5 that are commonly connected and the power supply voltage of the circuit, a P-channel MOSFETP that receives the internal signal CA at its gate is formed.
1 and a depletion MOSFET D1 having their gates and sources commonly coupled are provided in series. Further, the unit read amplifier URA0 and the like of the read amplifier RA include an N-channel type reset MOSFET N11 which is provided between the corresponding common data line CD0 and the like and the ground potential of the circuit and which receives the internal signal CA at its gate. The internal signal CA is a mask ROM when the internal control signal CE or ATD is at a low level.
Is set to the non-selected state or the mask ROM is set to the selected state and a level change of the address signals AY0 to AYj is detected by an address transition detection circuit (not shown), the signal is selectively set to the high level.

When the internal control signal CE or ATD is set to the low level and the internal signal CA is set to the high level, in the unit read amplifier URA0 and the like of the read amplifier RA, the MOSFET P1 is turned off and the MOSFET P1 is turned off.
Both N5 and N11 are turned on. For this reason,
The potential of the output terminal Va0 of the current sense circuit CS0 and the like is
As shown in FIG. 6, the reset MOSFET N5 is set to a low level like the ground potential of the circuit, and the potential of the common data line CD0 and the like is also set to the reset MOSFET N11.
To a low level like the ground potential of the circuit.

Next, when the mask ROM is selected or the level change of the address signals AY0 to AYj settles down and the internal signal CA is set to the high level, the unit read amplifier URA0 of the read amplifier RA and the like have MOSFE.
TP1 is turned on and MOSFETs N5 and N11
Are both turned off. Therefore, in the current sense circuit CS0 and the like, the potential of the output terminal Va0 and the like is first set to the MOSF.
The voltage is set to a high level close to the power supply voltage of the circuit via ETP1, and the charge MOSFET N3 is turned on in response to the high level of the output terminal Va0 and the like. However, the selected memory cell is supplied with the read current corresponding to the held data from the charge MOSFET N3 via the common data line CD0 and the like and the corresponding bit line, whereby the potential of the common data line CD0 and the like is selected. It is selectively set to a predetermined high level or low level according to the held data of the memory cell.

That is, depending on the selected memory cell, a logic "0" (in this specification, a MOS serving as a memory cell is
When the threshold voltage of the FET is made relatively small and a relatively large read current is made to flow, the held data is logically “0”.
And the data held in the opposite case is called logic "1")
When the data is stored, a relatively large read current flows through this memory cell, so that the common data line CD0 and the like are set to a relatively low level such as the potential V1. Therefore, the output terminal V of the current sense circuit CS0 or the like
a0 and the like are set to a level higher than the reference potential VR such as the potential V3, whereby the output signals R0 and the like of the differential amplifier circuit DA0 and the like are set to a low level such as the ground potential of the circuit. On the other hand, when the data of logic "1" is held by the selected memory cell, a relatively small read current is passed through this memory cell, so that the potential of the common data line CD0 or the like is the potential V5. It is a relatively high level. Therefore, the output terminals Va0 and the like of the current sense circuit CS0 and the like are set to a level lower than the reference potential VR such as the potential V6, whereby the output signals R0 and the like of the differential amplifier circuit DA0 and the like are high like the power supply voltage of the circuit. It is a level.

However, it has been made clear by the inventors of the present application that the conventional mask ROM as described above has the following problems as its integration and speed increase. That is, in the read amplifier RA of the mask ROM, as described above, the potentials of the output terminals Va0 and the like of the current sense circuit CS0 and the like are reset to a low level such as the ground potential of the circuit each time the memory cell selecting operation is performed. Further, the voltage is once set to a high level close to the power supply voltage of the circuit, and then set to a predetermined high level or low level according to the data held in the selected memory cell. A mask ROM is provided at the output terminal Va0 of the current sense circuit CS0 and the like.
A relatively large parasitic capacitance is coupled with the higher integration of the above, and these parasitic capacitances act to delay the above-mentioned level change of the output terminal Va0 and the like. As a result, the read operation of the mask ROM is delayed, and the increase in access time is restricted. Further, in order to deal with this, if the reset operation of the output terminal Va0 and the common data line CD0 performed during the memory cell selection operation is stopped, the levels of the output terminal Va0 and the common data line CD0 are charged up. , Read amplifier R
It becomes impossible to perform a normal read operation as A.

It is an object of the present invention to perform a normal read operation and to speed up access time in a mask ROM.
And other semiconductor memory devices.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0012]

The outline of the representative one of the inventions disclosed in the present application will be briefly described as follows. That is, in a mask ROM having a read amplifier including a current sense circuit and a differential amplifier circuit, the reset operation of the output terminal of the current sense circuit and the corresponding common data line by the output signal of the address transition detection circuit is stopped and A leak MOSFET is provided between the common data line and the ground potential of the circuit, which is selectively turned on according to a substantial output signal of the differential amplifier circuit and limits the high level of the common data line to a predetermined level.

[0013]

According to the above means, it is possible to limit the signal amplitude at the output terminal of the current sense circuit and prevent the influence of the parasitic capacitance on the level change while preventing the common data line from being charged up. As a result, it is possible to speed up the access time of the mask ROM or the like while performing the read operation normally.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows a mask RO to which the present invention is applied.
A block diagram of one embodiment of M is shown. First, the outline of the configuration and operation of the mask ROM of this embodiment will be described with reference to FIG. The circuit elements forming each block in FIG. 1 are formed on one semiconductor substrate such as single crystal silicon, though not particularly limited, by a well-known semiconductor integrated circuit manufacturing technique.

In FIG. 1, the mask ROM of this embodiment
Has as its basic structure a memory array MARY which occupies most of the surface of the semiconductor substrate. This memory array M
The ARYs are arranged in a grid pattern at a plurality of word lines arranged in parallel in the vertical direction and a plurality of bit lines arranged in parallel in the horizontal direction and at intersections of these word lines and bit lines. And a large number of memory cells. In this embodiment, each of the memory cells forming the memory array MARY is composed of an N-channel MOSFET, and the threshold voltage is selectively changed by selectively changing the amount of impurities ion-implanted into the channel portion. Is supposed to have. That is, when a relatively small amount of impurities are ion-implanted into the channel portion, the memory cell is assumed to have a relatively small threshold voltage, and becomes a so-called depletion type MOSFET. At this time,
The memory cell is supposed to hold data of logic "0", and a relatively large read current is flowed at the time of selection.
On the other hand, when a relatively large amount of impurities are ion-implanted into the channel portion, the memory cell has a relatively large threshold voltage, so to speak, it acts as a high threshold voltage N-channel MOSFET. At this time, the memory cell is supposed to hold the data of logic "1", and a relatively small read current flows when selected.

The word lines forming the memory array MARY are coupled to the X address decoder XD and are alternatively set to the high level selected state. The X address decoder XD is supplied with i + 1-bit internal address signals X0 to Xi from the X address buffer XB. Further, the X address buffer XB is supplied with X address signals AX0 to AXi via address input terminals AX0 to AXi.

The X address buffer XB takes in and holds the X address signals AX0 to AXi supplied via the address input terminals AX0 to AXi, and holds the internal address signals X0 to Xi based on these X address signals.
Are formed and supplied to the X address decoder XD. The X address decoder XD decodes the internal address signals X0 to Xi supplied from the X address buffer XB, and selectively sets the corresponding word lines of the memory array MARY to the high level selected state.

Next, the bit lines forming the memory array MARY are the switch MOSF corresponding to the Y switch YS.
It is coupled to ET and is selectively connected to the common data lines CD0 to CD7 by 8 lines via the Y switch YS. Y
The switch YS includes a plurality of switch MOSFETs provided corresponding to each bit line of the memory array MARY. The gates of these switch MOSFETs are sequentially 8
Each of them is commonly connected and the corresponding bit line selection signal is supplied from the Y address decoder YD. The Y address decoder YD is supplied with the j + 1-bit internal address signals Y0 to Yj from the Y address buffer YB, and the Y address buffer YB is supplied with the Y address signals AY0 to AYj via the address input terminals AY0 to AYj. It

The Y address buffer YB fetches and holds the Y address signals AY0 to AYj supplied via the address input terminals AY0 to AYj, and at the same time, based on these Y address signals, the internal address signals Y0 to Yj.
Are formed and supplied to the Y address decoder YD. The Y address decoder YD decodes the internal address signals Y0 to Yj supplied from the Y address buffer YB, and selectively sets the corresponding bit line selection signal to the high level selected state. Switch MOSF that constitutes the Y switch YS
ET is selectively turned on by eight by setting the corresponding bit line selection signal to the high level, and the corresponding eight bit lines of the memory array MARY and the common data line C
D0 to CD7 are selectively connected.

The common data lines CD0 to CD7 are coupled to the input terminals of the corresponding unit read amplifiers of the read amplifier RA. An internal control signal CE is commonly supplied from the timing generation circuit TG to these unit read amplifiers, and the output terminal thereof is coupled to the input terminal of the corresponding unit circuit of the data output buffer OB. Data output buffer OB
An internal control signal OE is commonly supplied to each unit circuit from the timing generation circuit TG, and its output terminal is coupled to the corresponding data output terminals D0 to D7. Here, the internal control signal CE is a chip enable signal CEB (here, a so-called inverted signal that is selectively brought to a low level when it is enabled is indicated by adding B to the end of its name. Similarly, the internal control signal OE is selectively set to the high level by receiving the low level of the output enable signal OEB.

The read amplifier RA has a common data line CD0.
8 unit read amplifiers URA0 to URA7 provided corresponding to CD7. These unit read amplifiers are selectively and simultaneously activated according to the internal control signal CE, and output from the selected eight memory cells of the memory array MARY through the corresponding common data lines CD0 to CD7. The read current is converted into a predetermined voltage signal and then amplified to form predetermined read signals R0 to R7, which are transmitted to the corresponding unit circuits of the data output buffer OB. Each unit circuit of the data output buffer OB is selectively and simultaneously operated in accordance with the internal control signal OE, and outputs the read signals R0 to R7 transmitted from the corresponding unit read amplifier of the read amplifier RA to the corresponding data output terminals. It is sent to the outside via D0 to D7. The specific configuration and operation of the read amplifier RA and its characteristics will be described later in detail.

The timing generation circuit TG is provided with a chip enable signal CEB supplied as an activation control signal from the outside.
Based on the output enable signal OEB and the output enable signal OEB, the above various internal control signals are formed and supplied to each part of the mask ROM.

FIG. 2 shows a circuit diagram of an embodiment of the read amplifier RA included in the mask ROM of FIG. 1, and FIG. 3 shows a signal waveform diagram of the embodiment. Based on these figures, the specific configuration and operation of the read amplifier RA of the mask ROM of this embodiment and its characteristics will be described. In the following circuit diagrams, the MOSFET having an arrow on its channel portion is a P-channel type (second conductivity type) and is distinguished from an N-channel type (first conductivity type) MOSFET without an arrow. Shown. Further, the N-channel MOSFET whose channel portion is shown by a thick line is a depletion MOSFET.

In FIG. 2, the read amplifier RA includes eight unit read amplifiers URA0 to URA7 provided corresponding to the common data lines CD0 to CD7. These unit read amplifiers include current sense circuits CS0 to CS7 and The differential amplifier circuits DA0 to DA7 are provided respectively. The input terminals of the unit read amplifiers URA0 to URA7 are coupled to the corresponding common data lines CD0 to CD7, and the output signals thereof are supplied as the read signals R0 to R7 to the corresponding unit circuits of the data output buffer OB. Hereinafter, a specific description will be given by taking the unit read amplifier URA0 as an example. Regarding the unit read amplifiers URA1 to URA7,
I would like to make an analogy.

The current sense circuit CS0 constituting the unit read amplifier URA0 is provided between the power supply voltage of the circuit (first power supply voltage) and the corresponding common data line CD0, and its gate is the circuit, that is, the current sense circuit CS0. N-channel type charge MOS coupled to the output terminal Va0
FET N3 (first MOSFET) and output terminal Va0
And a ground potential (second power supply voltage) of the circuit, and its gate is coupled to the corresponding common data line CD0. An N-channel type sense MOSFET N4 (second MO
SFET). Here, the power supply voltage of the circuit is not particularly limited, but is a positive power supply voltage such as +5 V (volt).

The sense MOSFET N4 includes an N-channel type reset MOSFET N5 (sixth MOSFET).
T) are provided in parallel, and a P-channel MOSFET P1 (fourth MOSFET) and a depletion MOSFET D are provided between the power supply voltage of the circuit and the output terminal Va0.
1 (fifth MOSFET) is provided in series. Of these, the internal control signal CE is supplied to the gates of the MOSFETs P1 and N5, and the gate of the MOSFET D1 is coupled to the sources thereof. The internal control signal CE
As described above, when the chip enable signal CEB is at the low level and the mask ROM is in the selected state, it is selectively set to the high level.

On the other hand, the differential amplifier circuit DA0 forming the unit read amplifier URA0 includes a pair of N-channel type differential MOSFETs N8 and N9. These MOSFE
The drain of T has N-channel MOSFETs N6 and N
Coupled to the power supply voltage of the circuit through 7, and its commonly coupled source coupled to the ground potential of the circuit through N-channel MOSFET N10. Differential MOSFET N8
Is coupled to the output terminal Va0 of the corresponding current sense circuit CS0, and the gate of the other differential MOSFET N9 is supplied with a predetermined reference potential VR from a constant voltage generating circuit (not shown). Further, the internal control signal VG is supplied to the gate of the MOSFET N10,
The gates of 6 and N7 are connected together and then
Commonly coupled to the drains of TN9. This makes MO
SFETs N6 and N7 are differential MOSFETs N8 and N
Acts as an active load on 9. MOSFE
The drain potential of TN8 is supplied to the corresponding unit circuit of the data output buffer OB as an output signal of the differential amplifier circuit DA0, that is, a read signal R0. The reference potential VR is set to an approximately intermediate level between the high level and the low level at the output terminal Va0 of the current sense circuit CS0, and the internal control signal VR is set to the mask ROM when the internal control signal CE is set to the high level. Is set to a high level selectively when is selected.

In this embodiment, the unit read amplifier U
RA0 further includes two N-channels M provided in series between the common data line CD0 and the ground potential of the circuit.
It includes OSFETs N1 (third MOSFET) and N2. Of these, the output signal of the differential amplifier circuit DA0, that is, the read signal R0 is supplied to the gate of the MOSFET N1, and the gate of the MOSFET N2 is coupled to the drain thereof. As a result, the MOSFET N1 acts as a so-called leak MOSFET, and together with the MOSFET N2 constitutes a level limiting means for limiting the high level of the common data line CD0 to a predetermined level.

When the mask ROM is deselected by the chip enable signal CEB being high level and the internal control signal CE is low level, the read amplifier R
In the unit read amplifier URA0 of A, the current sense circuit C
The MOSFET P1 of S0 is turned off, and the reset M
The OSFET N5 is turned on. Therefore, the output terminal Va0 of the current sense circuit CS0 is set to a low level like the ground potential of the circuit as shown in FIG. 3, whereby the charge MOSFET N3 is turned off. At this time, in the differential amplifier circuit DA0, the MOSFET
N10 is turned off and brought into a non-operation state, and its output signal, that is, the read signal R0 is set to a high level like the power supply voltage of the circuit. As a result, the leak MOSF
The ETN1 is turned on, and the common data line CD0 is set to a predetermined low level higher than the ground potential of the circuit by the threshold voltage of the MOSFET N2.

Next, when the chip enable signal CEB is set to the low level to bring the mask ROM into the selected state and the internal control signal CE is set to the high level, the unit read amplifier URA0 of the read amplifier RA has the current sense circuit CS0. Reset MOSFET N5 is turned off,
Instead, the MOSFET P1 is turned on. Therefore, as shown in FIG. 3, the output terminal Va0 of the current sense circuit CS0 is temporarily set to a high level close to the power supply voltage of the circuit, and the charge MOSFET N3 is turned on in response to the high level of the output terminal Va0. It is said that At this time, in the differential amplifier circuit DA0, the MOSFET N10 is turned on, whereby the amplifying operation of the read signal by the differential MOSFETs N8 and N9 is started. A read current is supplied to the selected memory cell of the memory array MARY from the charge MOSFET N3 through the common data line CD0 and the corresponding bit line, whereby the potential of the common data line CD0 holds data of the selected memory cell. In accordance with this, a predetermined high level or low level is selectively set.

That is, when the selected memory cell holds the data of logic "0" and its threshold voltage is made relatively small, the common data line CD0 is connected to the selected memory cell via the selected memory cell. A relatively large current is applied. Therefore, the potential of the common data line CD0 changes from the ground potential of the circuit to the charge MOSFE, as shown in FIG.
It rises to a relatively low potential V1 commensurate with the conductance ratio of TN3 and the selected memory cell. In addition, when the potential V1 of the common data line CD0 is received, the sense MOSFET N
4 is turned on weekly, whereby the potential of the output terminal Va0 of the current sense circuit CS0 changes to the reference potential V0.
It drops to a predetermined potential V3 higher than R. The potential V3 at the output terminal Va0 is compared and amplified with the reference potential VR in the differential amplifier circuit DA0, whereby the output signal of the differential amplifier circuit DA0, that is, the read signal R0 is at a low level like the ground potential of the circuit. . At this time,
The leak MOSFET N1 is turned off in response to the low level of the read signal R0, and has no effect on the common data line CD0.

On the other hand, the selected memory cell has a logic "1".
When the threshold voltage of the data is held relatively high, a relatively small current is passed through the common data line CD0 through the selected memory cell. Therefore, the potential of the common data line CD0 tends to rise from the ground potential of the circuit to a relatively high potential commensurate with the conductance ratio of the charge MOSFET N3 and the selected memory cell, as shown in FIG. In addition, the conductance of the sense MOSFET N4 is increased in response to the rise in the potential of the common data line CD0, whereby the potential of the output terminal Va0 of the current sense circuit CS0 drops to a predetermined potential V4 lower than the reference potential VR. This output terminal Va0
The potential V4 at is compared and amplified with the reference potential VR in the differential amplifier circuit DA0, whereby the output signal of the differential amplifier circuit DA0, that is, the read signal R0 is set to a high level like the power supply voltage of the circuit. At this time, the leak MOSFET N1 is turned on in response to the high level of the read signal R0, and acts as a level limiting means together with the MOSFET N2. As a result, the common data line C
The increase in the potential of D0 is limited to the potential V2 corresponding to the conductance ratio between the charge MOSFET N3 and the leak MOSFETs N1 and N2, thereby preventing the common data line CD0 from being charged up.

Hereinafter, in the read amplifier RA, while the chip enable signal CEB is at the low level, the same read operation is repeated in response to changes in the Y address signals AY0 to AYj, and these are output to the output terminal of the read amplifier RA. The read signal R0 of the memory cell designated by the Y address signal is sequentially output. During this time, the level of the common data line CD0 is changed with a relatively small amplitude between the potential V1 and the potential V2, and the current sense circuit CS0
The level of the output terminal Va0 of is also changed with a relatively small amplitude between the potential V3 and the potential V4. As a result, the charge-up of the common data line CD0 can be prevented, the read operation of the mask ROM can be normally performed, and the common data line CD0 and the current sense circuit CS can be performed.
It is possible to suppress the influence of the parasitic capacitance on the level change of the output terminal Va0 of 0 and accelerate the access time of the mask ROM.

By applying the present invention to a semiconductor memory device such as a mask ROM as shown in the above embodiment, the following operational effects can be obtained. That is, (1) In a mask ROM having a read amplifier including a current sense circuit and a differential amplifier circuit, the reset operation of the output terminal of the current sense circuit and the corresponding common data line by the output signal of the address transition detection circuit is stopped. Along with the corresponding common data line and the ground potential of the circuit, a leak MOSFET that is selectively turned on according to the substantial output signal of the differential amplifier circuit and limits the high level of the common data line to a predetermined level. With the provision, the effect that the signal amplitude at the common data line and the output terminal of the current sense circuit can be limited while preventing the charge-up of the common data line is obtained. (2) According to the item (1), it is possible to suppress the influence of the parasitic capacitance on the level change of the common data line and the output terminal of the current sense circuit. (3) According to the above items (1) and (2), it is possible to obtain the effect that the access time of the mask ROM or the like can be shortened while the reading operation is normally performed.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in FIG. 1, the mask ROM may read the storage data in 1-bit units, or may read the storage data of 9 bits or more at the same time. Further, the memory array MARY can be divided into a plurality of sub memory arrays, and the block configuration of the mask ROM is not restricted by this embodiment.

In FIG. 2, the level limiting means including the leakage MOSFET N1 may not include the MOSFET N2, or may include a plurality of MOSFETs in the diode form such as the MOSFET N2. Further, in this embodiment, the leak MOSF is generated by the output signal of the differential amplifier circuit DA0, that is, the read signal R0.
Although the ETN1 is selectively turned on, as shown in FIG. 4, the leak MOSFE is generated by the inverted signal of the output signal of the current sense circuit CS0 by the inverter INV1.
The TN1 may be selectively turned on. Mask ROM
If the read amplifier is provided corresponding to the bit line without including the Y switch, it is necessary to provide the level limiting means including the MOSFET N1 for each bit line. Furthermore, FIG.
Also, various embodiments such as a specific circuit configuration of the read amplifier RA shown in FIG. 4, the polarity and absolute value of the power supply voltage, and the conductivity type of the MOSFET can be adopted.

In the above description, the case where the invention made by the present inventor is mainly applied to the mask ROM which is the field of application which is the background of the invention has been described. However, the present invention is not limited to this and, for example, a mask ROM is used. It is also applicable to various memory integrated circuits including a built-in single-chip microcomputer and similar read amplifiers. The present invention can be widely applied to a semiconductor memory device including a read amplifier including at least a current sense circuit and a differential amplifier circuit, and a digital integrated circuit device including such a semiconductor memory device.

[0038]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, in a semiconductor memory device such as a mask ROM having a read amplifier including a current sense circuit and a differential amplifier circuit, the reset operation of the output terminal of the current sense circuit and the corresponding common data line by the output signal of the address transition detection circuit is stopped. In addition, the leakage MOSFET that is selectively turned on between the corresponding common data line and the ground potential of the circuit according to the substantial output signal of the differential amplifier circuit to limit the high level of the common data line to a predetermined level. By providing the above, it is possible to limit the signal amplitude at the output terminal of the current sense circuit and prevent the influence of the parasitic capacitance on the level change while preventing the common data line from being charged up. As a result, it is possible to speed up the access time of the mask ROM or the like while performing the read operation normally.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a mask ROM to which the present invention is applied.

FIG. 2 is a circuit diagram showing a first embodiment of a read amplifier included in the mask ROM of FIG.

FIG. 3 is a signal waveform diagram showing an embodiment of the read amplifier of FIG.

4 is a circuit diagram showing a second embodiment of the read amplifier included in the mask ROM of FIG.

FIG. 5 is a circuit diagram showing an example of a read amplifier included in a mask ROM developed by the inventors of the present application prior to the present invention.

FIG. 6 is a signal waveform diagram showing an example of the read amplifier of FIG.

[Explanation of symbols]

MARY ... Memory array, XD ... X address decoder, XB ... X address buffer, YS ... Y
Switch, YD ... Y address decoder, YB ...
Y address buffer, RA ... Read amplifier, OB
..Data output buffer, TG ... Timing generation circuit URA0 to URA7 ... Unit read amplifier, CS
0-CS7 ... Current sense circuit, DA0-DA7 ...
.Differential amplifier circuit, P1 ... P channel MOSFE
T, D1 ... Depletion MOSFET, N1 to N
11 ... N-channel MOSFET, INV1 ...
Inverter.

Claims (3)

[Claims] 1. A read amplifier for amplifying a read signal output from a selected memory cell through a corresponding bit line or a corresponding bit line and a common data line,
2. A semiconductor memory device, comprising: level limiting means which is selectively enabled according to a substantial output signal of the read amplifier and limits the potential of the bit line and / or the common data line to a predetermined level. 2. The read amplifier is provided between a first power supply voltage and the bit line or the common data line and has a gate coupled to an output terminal of the circuit. A current sense circuit including a second MOSFET of a first conductivity type, the second sense MOSFET being provided between an output terminal of the circuit and a second power supply voltage and having a gate coupled to the bit line or the common data line; And a differential amplifier circuit that receives a predetermined reference potential and the level limiting means is provided between the bit line or common data line and the second power supply voltage, and the gate thereof is provided. 2. The semiconductor according to claim 1, further comprising a third MOSFET of a first conductivity type which receives an inverted signal of the output signal of the current sense circuit or an output signal of the differential amplifier circuit. Storage device. 3. The semiconductor memory device is a mask ROM, wherein the current sense circuit is provided in series between a first power supply voltage and an output terminal of the circuit, and the mask ROM is in a selected state. The fourth of the second conductivity type that is turned on for a while.
And a depletion-type fifth MOSFET whose gate and source are commonly coupled, and a mask RO provided in parallel with the second MOSFET.
3. The semiconductor memory device according to claim 1, further comprising a sixth MOSFET of the first conductivity type which is turned on while M is in a non-selected state.