JP2995230B2 - Bit line sense amplifier and control method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an offset (off)
set) Bit line (Bit-li) having a compensation function
ne) It relates to a sense amplifier and a control method thereof.

[0002]

2. Description of the Related Art In general, MOS (Metal Oxid)
The memory using the e-semiconductor element is a scale-down (Sc) of a MOS transistor.
Aled-down) results in a dramatic increase in the degree of integration and an improvement in access time. In fact, due to the advancement of such technology, around 2002, 1GB DRA
M (Dynamic Random Access M)
emory) is expected to become commonplace.

In a Giga-bit DRAM, it is expected that a 0.18 μm transistor will be used for a 1 GB DRAM cell and a 0.13 μm transistor will be used for a 4 GB DRAM cell.
The most important part of the M design, the bit line sense amplifier, also has a deep submicron (Deep Submicron).
The use of a MOS transistor of a micron type causes many problems in the conventional megabit DRAM.

That is, the bit line sense amplifier is a circuit (for example, a differential amplifier or a dynamic CMOS latch) including symmetric transistors in order to quickly amplify a small voltage difference between the bit lines (BL & / BL). Circuit provided), but a short channel (Sh
ort Channel) extent is transistor, a change in the process, the threshold voltage between adjacent transistors _{(ThresholdVoltage; V} T), the transfer conductance (Transconductance; mismatch such as Gm) is to increase.

[0005] The offset due to the mismatch lowers the sensitivity of the bit line sense amplifier, not only greatly reducing the sensing speed but also causing a malfunction. In addition, since a gigabit DRAM has a very large number of bit line sense amplifiers, in order to ensure that all sense amplifiers used in a memory device do not malfunction and always perform a sensing operation properly,
The conditions of the worst case become very severe.

For example, in a 1 Gbit DRAM,
More than 2 × 10 ⁶ bit line sense amplifiers will be used, and to ensure that all sense amplifiers operate correctly, a mismatch distribution of V _T , G _m of 6
The sensing operation must be correct for fluctuation conditions of σ or more. Here, σ is the standard deviation of the mismatch distribution.

Therefore, in a gigabit DRAM, offset of a sense amplifier due to transistor mismatch is an unavoidable fundamental problem, and a circuit solution to this problem is necessarily required.

The operation speed of the DRAM has not been improved as compared with the dramatic increase in the degree of integration. Therefore, recently, DRAM
High-speed operation has become very important in order to improve the performance of the device.
For high-speed operation of the DRAM, the sensing operation must be done at high speed, various attempts for this have been made. Dynamic CMOS latch (Latch) bit line sense amplifiers have been commonly used in mega-bit DRAMs due to their simplicity and high sensitivity.

However, the sensitivity is considerably reduced due to the mismatch existing between the transistors having a symmetric structure, and a sufficient timing margin is required for a stable sensing operation.

In a recently developed 64-Mbit and 256-Mbit DRAM, a direct sense amplifier (Direct Se) using a differential amplifier circuit for high-speed operation is used.
nse Amplifier) is often applied.
A circuit diagram of such an existing bit line direct sense amplifier is shown in FIG.

In the drawing, NA1 to NA9 are NMOS
Transistors, BL and / BL are bit lines, SA
N and SAP are control signals of a reproduction amplifier, GYi is an output of a column decoder, GWi is an output of a write column decoder, PC is a precharge control signal, and HV is a half drive voltage (Harf-Vcc, ie, Vcc / 2). Show.

The operation of the direct sense amplifier will now be described with reference to FIG. First, the transistors (NA7, NA8, NA9) are used to set the bit line (B
L & / BL) are precharged with Vcc / 2 and the word line (WL) and the output (GY) of the column decoder
i) is activated.

As the cell data is transmitted to the bit line, a small voltage difference between the bit lines is amplified by the transistors (NA1 and NA2), and the amplified signal is transmitted to the sense amplifier of the read data bus to be sensed. . Cell data is sufficiently transmitted to the bit line and sensed. When the cell data is sufficiently transmitted to the bit line, the control signals (SAP and SAN) are activated to operate the regenerative amplifier and further write data to the cell (WRIT).
E). When the reproduction of the cell data is completed, a further precharge state is set.

In the operation of the direct sense amplifier, a sensing operation is performed without a signal transmission time from a cell to a bit line, and thus, high-speed sensing is possible. However, the conventional direct sense amplifier described above has a reduced sensitivity due to a mismatch between the transistors (NA1 and NA2) performing the sensing, and cannot guarantee a more stable operation. It involves many difficulties.

[0015]

SUMMARY OF THE INVENTION Accordingly, the present invention devised to solve the above-mentioned problems has a gigabit class DRA.
It is an object of the present invention to provide a bit line sense amplifier that operates stably at high speed under worst-case conditions by compensating for the offset of the sense amplifier due to mismatch between transistors with M and a method of controlling the same.

On the other hand, the reason why the conventional direct sense amplifier or the sense amplifier of the dynamic CMOS latch is sensitive to the offset is that the sensing operation is performed by the race between the symmetric transistors. That is, in the direct sense amplifier of FIG. 1, the voltage difference (Δv) between the bit lines is amplified and sensed by the transistors (NA1 and NA2) due to the current difference. A race occurs during the sensing operation.

The most commonly used dynamic CM
In the case of the OS latch bit line sense amplifier, a race occurs between cross-coupled transistors.

Therefore, there is a need for a new concept of a sensing scheme without a race. It is another object of the present invention to provide a bit line sense amplifier that satisfies such a demand.

[0019]

In order to achieve the above object, a first aspect of the present invention is a bit line sense amplifier of a memory device having a reproducing amplifier, wherein data of a first bit line (BL) is inverted. First inverter to output: Inverts and outputs data of second bit line (/ BL) Second inverter: Output signal of column decoder (G
First and second switching means for respectively switching between the output terminals of the first and second inverters and the data bus according to Yi): respectively, between the input / output terminals of the first and second inverters according to an offset compensation signal (CMP). Switching third and fourth switching means: and an offset compensation signal (CMP) generating means for generating the offset compensation signal (CMP) according to an internal signal including an output signal (GYi) of the external column decoder. And

Further, the present invention provides a pull-up drive signal (PD) generating means for generating a pull-up drive signal (PD): a pull-down control signal (GZ).
i) generating means for generating a pull-down control signal (GZi): the first and second inverters each include a pull-up and pull-down transistor, and a source terminal of the pull-up transistor is connected to the pull-up driving signal (GZi). PD), and the source end of the pull-down transistor receives the pull-down control signal (GZi).
In accordance with (1) and (2) are connected to the ground end.

Further, according to a third aspect of the present invention, in the first or second aspect, the offset compensation signal (CM
P) The generating means activates the offset compensation signal (CMP) so that data can be transmitted from the data bus to the first bit line (BL) and the second bit line (/ BL) at the time of writing. It is characterized by comprising.

According to a fourth aspect of the present invention, in the third aspect, (GZi) is deactivated, and the pull-up drive signal (PD) generating means includes a write-time pull-up drive signal (P
D) is configured to be loaded.

According to a fifth aspect of the present invention, in the third aspect, when the external RAS (RAS) signal is activated low, the offset compensating signal (CMP) generating means sets the offset after a predetermined time delay. After the compensation signal (CMP) is output high, the offset compensation signal (CMP) is further shifted to low and output after delaying for a predetermined time.

According to a sixth aspect of the present invention, in the fifth aspect, the offset compensating signal (CMP) generating means includes a first delay unit for delaying an external lath signal for a predetermined time,
A second delay device for delaying the inverted value of the output of the delay device for a predetermined time;
And an AND gate for inputting the output of each of the first and second delay devices.

According to a seventh aspect of the present invention, in the fourth aspect, the pull-down control signal (GZi) generating means includes only the inverter of the sense amplifier connected to the data bus among the first and second inverters. The pull-down control signal (GZi) is generated to operate.

According to an eighth aspect of the present invention, in the fourth aspect, the pull-up drive signal (PD) generating means is configured to provide a voltage V _K [= main power supply (Vcc) -the first and the second at the time of precharge. 2 inverters respectively provided by the threshold voltage of the pull-up transistor and (V _T)] is output as pull-up driving signal (PD), the output of the main power supply (Vcc) when sensing the offset compensation as a pull-up driving signal (PD) It is characterized by having comprised so that it may perform.

According to a ninth aspect of the present invention, in the eighth aspect , the pull-up drive signal (PD) generating means is configured to output a signal when the offset compensation signal (CMP) is activated to a high level.
_K is output as a pull-up drive signal (PD), and when the precharge control signal (PC), which is an internal signal of the memory element, transitions from high to low, the main power supply (Vcc) is output as a pull-up drive signal (PD). Then, after maintaining the main power supply (Vcc) at the pull-up drive signal (PD) for a certain period of time, the ground potential is output as the pull-up drive signal (PD).

According to a tenth aspect of the present invention, in the ninth aspect , the pull-up drive signal (PD) generating means includes a NAND gate for inputting the offset compensation signal (CMP) and a precharge control signal (PC). A fourth delay unit for delaying the inverted value of the precharge control signal (PC) by a predetermined time; an OR gate for receiving the output of the fourth delay unit and the precharge control signal (PC); OR gate and the second 2AND gate for inputting the imagewise signal respective outputs, the NAND gate and the first transistor configured to output a V _K as a pull-up driving signal (PD) according to the output of said OR gate of the main power source in accordance with the output ( Vcc) as a pull-up drive signal (PD), and the second transistor A third transistor configured to output a ground potential as a pull-up drive signal (PD) in accordance with an output of the ND gate.

According to claim 11 of the present invention, in claim 10 , the first bit line (BL) and the second bit line (/) are controlled according to the precharge control signal (PC).
BL) is provided.

According to a twelfth aspect of the present invention, in the eleventh aspect , the precharge means is configured to control the first bit line (BL) according to the precharge control signal (PC).
And a fifth switching means for switching between the first bit line and the second bit line (/ BL).

According to a thirteenth aspect of the present invention, in the twelfth aspect , the precharge means comprises a half drive voltage application terminal: the first bit line (BL) is half driven in accordance with the precharge control signal (PC). Sixth switching means for switching between voltage application terminals: and the second bit line (/ B) according to the blur charge control signal (PC).
L) and a seventh switching means for switching between the half drive voltage application terminal.

According to a fourteenth aspect of the present invention, there is provided a bit line sense amplifier of a memory device having a reproducing amplifier, wherein a first inverter for inverting and outputting data input from a first bit line (BL) is provided. Second inverter for inverting and outputting data output from bit line (/ BL): output signal (GY) of external column decoder
first and second switching means for respectively switching between the output terminals of the first and second inverters and a predetermined data bus according to i): and an external offset compensation signal (C
MP) according to the present invention, wherein third and fourth switching means for switching between the input / output terminals of the first and second inverters, respectively, are provided.

[0033] Further, Claim 15 of the present invention, first and second inverters for inverting and outputting the data input from the first bit line (BL) and second bitline (/ BL):
And the first signal according to the offset compensation signal (CMP).
And the first for switching between the input / output terminals of the second inverter
And controlling the bit line sense amplifier including the second switching means and precharging the bit line: the first and second inverters are connected to connect the input terminal and the output terminal of each of the first and second inverters. Switching the switching means to compensate for the offset; and activating the word line so that only the voltage of the bit line connected to the cell is changed, so that the first and second voltages are changed.
One of the inverters performs an amplifying operation, and the other includes a step of maintaining an input / output voltage after offset compensation.

According to a sixteenth aspect of the present invention, in the fifteenth aspect , the pull-up drive voltage of the first and second inverters is provided between the main power supply (Vcc) and the first and second inverters during precharge. The threshold voltage (V _T ) of the pull-up transistor to be controlled is controlled.

A seventeenth aspect of the present invention is characterized in that, in the sixteenth aspect , the pull-up driving voltage of the first and second inverters is controlled to be a main power supply during offset compensation and sensing operation. I do.

According to claim 18 of the present invention, in claim 15 , the first and second inverters are controlled to be inactive during a write operation.

According to a nineteenth aspect of the present invention, in the sixteenth aspect , the offset compensation signal (CMP) is generated so that data is transmitted from the data bus to the bit line.

[0038]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to FIGS. FIG. 2 is a conceptual circuit diagram for explaining a basic principle applied to the present invention, and FIG. 3 is an input / output transmission curve (Trans) shown in FIG.
fercurve) Ru Der. In the figure, 21 indicates an inverter, and 22 indicates a switch.

The inverter 21 exhibits an input / output transmission curve as shown in FIG. 3, but when the input terminal and the output terminal are connected by the switch 22, the amplification of the inverter 21 is performed irrespective of the offset due to the fluctuation of the transistor. The input and output are determined in the state where the degree is the highest. In this state, the currents flowing through the PMOS and NMOS transistors of the inverter 21 are the same.

After the switch 22 is turned off, the input becomes Δv
The output of the inverter 21 becomes Δi = ( _GmN
+ G _mP ) Δv. Here, G _mN , G _mP
Is the transmission conductivity of the NMOS and PMOS transistors, respectively. The principle of offset compensation of the inverter 21 is applied to the present bit line sense amplifier.

FIGS. 4 and 5 are conceptual diagrams for explaining the operation principle of the bit line sense amplifier having the offset compensation function according to the present invention. FIG. 4 shows a state in which the word line (WL) is inactive ['LOW'] and the switch (S) is inactive.
1, S2) are turned "on" to compensate the inverter offset for the pre-charged bit lines (BL & / BL) respectively.

FIG. 5 is a conceptual diagram for explaining a sensing operation. As shown, after offset compensation is performed as shown in FIG. 4 according to the present invention, the switches (S1, S2) are turned off and the switches are turned off. (S3, S4) is turned on, and the word line (WL) is activated ['high' (High)
) '], The data of the cell capacitor (Cs) induces a small voltage difference on the bit line (BL), and this signal is amplified through the inverter 31.

On the other hand, since the voltage of the input voltage / BL does not change, the inverter 32 maintains the input / output voltage after offset compensation. Accordingly, the sensing method applied to the present invention performs a stable sensing operation without being affected by an offset because there is no race between transistors unlike the existing sense amplifier.

FIG. 6 is a circuit diagram of a bit line sense amplifier having an offset compensation function according to an embodiment of the present invention. This is a circuit diagram of the conceptual diagrams of FIGS. 4 and 5. In this embodiment, each of the transistors (N
B1 and PB1) and an inverter 42 having transistors NB2 and PB2 to perform offset compensation and sensing.

In the drawing, GZi is a pull-down control signal of the inverter, which becomes high only when the column decoder output GYi is activated at the time of data read, and unnecessary power consumption in the entire inverter sense amplifier array. So that there is no

At the time of writing, GZi is inactivated at "low", the pull-up drive signal (PD) of the inverter is in a floating state, and the inverter 41 and the inverter 42 are inactive (inactive), while the offset is offset. The compensating signal (CMP) is activated to be "high" so that data can be transmitted from the data bus to the bit line.

The above PC, WL, GYi, SAP,
Signals such as SAN are internal signals unique to DRAM,
The MP, PD, and GZi signals are signals newly generated to implement the present invention, and a detailed circuit for generating these signals will be described below with reference to FIGS. . The bit line sense amplifier having the offset compensation function according to the present invention uses an existing precharge circuit (NA in FIG. 1) in order to reduce a layout area.
7, NA8, NA9) and a new precharge circuit, such a precharge circuit is shown in FIG.

FIG. 7 is a diagram of a precharge circuit applied to the present invention. In general, a DRAM changes to a precharged state after reproducing cell data. At this time, since the bit lines are “high” and “low”, the P
The transistor NB8 is turned on by C, and the voltages of the bit lines BL and / BL are set to an intermediate voltage (half driving voltage) between high and low.

Thereafter, the CMP is activated to connect the transistors PB1 and PB2 in a diode form to reduce the voltage BL and / B from the PD voltage (V _k ) to a voltage lower than the threshold voltage of the PMOS.
L is precharged. As an example, Vcc = 4V _T
In the case of “V _K = Vcc−V _T ”, the bit line (BL & / BL) becomes Vcc / V
It is precharged to a voltage of about 2 (half drive voltage). Precharging by an existing precharge circuit is also possible.

FIG. 8 is a timing chart of the main signals in the bit line sense amplifier of the present invention at the time of reading. In the drawing, Vpp is a bootstrapped voltage (Boo).
tstrappdvoltage), _{V K} denotes respectively the voltage level of the PD for precharge.

As shown, the read operation is roughly divided into precharge (a), offset compensation (b), sensing (C), storage (Restore), and (d). The PC, creating an intermediate voltage of the BL and / BL "high" and "low", to precharge the bit line to _V K -V _T by CMP.

Next, PD and GZi are activated to "Vcc" to perform offset compensation, and the word line WL
And GYi are activated to start sensing. The bit line connected to the cell is sensed by gradually inducing a smaller voltage difference in the transmitted cell data, and this signal is amplified by the inverter and transmitted to the data bus sense amplifier.

When the cell data is sufficiently transmitted to the bit line, the regenerative amplifier operates by SAP and SAN, and data is further written to the cell. When the cell data is completely stored, the cell enters the precharge state again.

GZi is all GZi at the time of offset compensation.
(1 ≦ i ≦ n) must be “high”, and only the GZi of the sense amplifier selected by the column decoder must be “high” at the time of reading.

FIG. 9 is a circuit diagram of a CMP generator for generating an offset compensation signal CMP. The CMP generator includes a RAS (Row Address Strong) as shown in the figure.
be) for a fixed time, and a delay device (7) for delaying the inverted value of the output of the delay device (71) for a certain time.
2) and receives the output of each of the delay units (71, 72)
An AND gate (73) for performing D operation and outputting the result to the CMP is provided.

Here, when the RAS signal is activated at a low level, the CMP goes high after the delay by the delay unit (71), and further transitions to low after the delay by the delay unit (72).

Therefore, a CMP having the width of the delay time of the delay unit (72) is generated. FIG. 10 is a circuit diagram of a PD generator for generating the pull-up drive signal PD. As shown in the figure, the PD generator has an NA for inputting CMP and PC.
An ND gate (74), a delay unit (75) for delaying the inverted value of PC for a predetermined time, an OR gate (76) for inputting the output of the delay unit (75) and PC, and a NAND gate (7)
4) and an OR gate (76) that inputs the respective outputs
And D gate (77), and configured PMOS transistor to output a _{V K} to the PD in accordance with the output of the NAND gate (74) (78), is configured to output Vcc to the PD in accordance with the output of the OR gate (76) PMOS
It comprises a transistor (79) and an NMOS transistor (80) configured to output a ground potential to the PD according to the output of the AND gate (77).

The voltage levels of PD are “V _K ” and “Vc”.
c "," a three ground potential ", which as shown, is produced by CMP and PC. That is, when the CMP is activated high, after the PD becomes _{V K,} PC is When transitioning from high to low, it is driven to Vcc.
After maintaining Vcc for the delay time of the delay unit (75), the NMOS transistor (80) is turned on by the AND gate (77), and the PD is set to the ground potential.

FIGS. 11 and 12 are a circuit diagram and a signal timing diagram for explaining the driving of the regenerative amplifier for reducing the power line noise induced by the sense amplifier. An operation of a regenerative amplifier for reducing noise of a power line (Vcc & GND) induced by an operation of a bit line sensing width device. As a plurality of regenerative amplifiers operate simultaneously, from Vcc to a bit line to a bit line to a ground. Since a large amount of current flows, the voltage of the power line greatly oscillates.

In the present invention, as shown in FIGS. 11 and 12, the control signals SAN and SAP are divided into two parts and a time difference is set therebetween in order to eliminate noise induced on the power line when the regenerative amplifier operates. Apply a method that works. That is, the SAP1 and SAN1 control signals are activated, and after a delay (Delay) for a certain time Td, the SA1 and SAN1 control signals are activated.
Activation of the P2 and SAN2 control signals can significantly reduce noise induced on the power line.

At this time, the SAP1 and SAN1 control signals and S
In order to provide a difference between the activation times of the AP2 and SAN2 control signals, the delay of the activation time is adjusted by adjusting the size of the transistors of the drivers of the SAP1 and SAN1 control signals and the driver of the SAP2 and SAN2 control signals. Give.

[0062]

The present invention configured as described above has an effect that it can operate stably at high speed even under worst case conditions by compensating for the offset of the sense amplifier due to mismatch between transistors.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an existing bit line sense amplifier.

FIG. 2 is a conceptual circuit diagram for explaining a basic principle applied to the present invention.

FIG. 3 is a characteristic diagram showing an input / output transmission curve of FIG.

FIG. 4 is a conceptual diagram illustrating an operation principle of a bit line sense amplifier having an offset compensation function according to the present invention.

FIG. 5 is a conceptual diagram illustrating an operation principle of a bit line sense amplifier having an offset compensation function according to the present invention.

FIG. 6 is a circuit diagram of a bit line sense amplifier having an offset compensation function according to an embodiment of the present invention.

FIG. 7 is a precharge circuit diagram applied to the present invention.

FIG. 8 is a timing diagram of main signals in the bit line sense amplifier of the present invention during a read.

FIG. 9 is a circuit diagram of an offset compensation signal CMP generator.

FIG. 10 is a circuit diagram of a pull-up drive signal PD generator.

FIG. 11 is a circuit diagram illustrating driving of a regenerative amplifier for reducing power line noise induced by a sense amplifier.

FIG. 12 shows the same timing.

[Explanation of symbols]

 NA1 to NA9 NMOS transistor NB1 to NB9 NMOS transistor PB1, PB2 PMOS transistor S1, S2, S3, S4 Switch 31, 32, 41, 42 Inverter BL, / BL Bit line SAN, SAP Control signal of regenerative amplifier Output of GYi column decoder GWi Write column decoder output PC precharge control signal HV Half drive voltage (Vcc / 2) Cs Cell capacitor WL Word line

Claims (19)

(57) [Claims] 1. A bit line sense amplifier for a memory device having a reproduction amplifier means, wherein a first bit line (BL) data is inverted and output.
Inverter: A second inverter that inverts and outputs data of a second bit line (/ BL): A first and a second that respectively switch between the output terminals of the first and second inverters and the data bus according to an output signal (GYi) of a column decoder. 2 switching means: third and fourth switching means for switching between the input / output terminals of the first and second inverters respectively according to an offset compensation signal (CMP): and an internal signal including an output signal (GYi) of the external column decoder A bit line sense amplifier comprising an offset compensation signal (CMP) generating means for generating the offset compensation signal (CMP) according to the following. 2. A pull-up drive signal (PD) generating means for generating a pull-up drive signal (PD), comprising: a pull-down control signal (GZi) generating means for generating a pull-down control signal (GZi). The first and second inverters have pull-up and pull-down transistors, respectively. A source terminal of the pull-up transistor receives the pull-up driving signal (PD), and a source terminal of the pull-down transistor controls the pull-down. Signal (GZ
A bit line sense amplifier configured to be connected to a ground terminal according to i). 3. The method according to claim 1, wherein said offset compensation signal (CMP) generating means transfers data from a data bus to said first bit line (BL) and said second bit line (/ BL) during writing. A bit line sense amplifier configured to activate an offset compensation signal (CMP) so that it can be transmitted. 4. The pull-down control signal (GZi) generating means according to claim 3, wherein said pull-down control signal (GZi) deactivates said pull-down control signal (GZi) during writing, and said pull-up driving signal (PD) generating means generates said pull-up driving signal during writing. Drive signal (P
A bit line sense amplifier, characterized in that D) is loaded. 5. The offset compensation signal (CMP) generating means according to claim 3, wherein when the external RAS (RAS) signal is activated to be low, the offset compensation signal (CMP) is made high after delaying for a predetermined time. A bit line sense amplifier, characterized in that the bit line sense amplifier is configured to output the output signal after further delaying the offset compensation signal (CMP) to a low level after outputting the output signal for a predetermined time. 6. The apparatus according to claim 5, wherein said offset compensating signal (CMP) generating means comprises: a first delay unit for delaying the external lath signal for a predetermined time; and a second delay unit for delaying the inverted value of the output of the first delay device for a predetermined time. A bit line sense amplifier, comprising: a delay circuit; and an AND gate for receiving an output of each of the first and second delay devices. 7. The pull-down control signal (GZi) generating means according to claim 4, wherein said pull-down control signal (GZi) generating means operates only an inverter of a sense amplifier connected to a data bus among said first and second inverters.
a bit line sense amplifier configured to generate i). 8. The method according to claim 4, wherein said pull-up driving signal (PD) generating means generates a voltage V _K during precharge.
Outputs - [= main power (Vcc) of the first and second inverters respectively provided by the threshold voltage of the pull-up transistor (V _T)] as a pull-up driving signal (PD), the main power supply when sensing the offset compensation (Vcc) is output as a pull-up drive signal (PD). 9. The method according to claim 8, wherein the pull-up drive signal (PD) generating means includes an offset compensation signal (CM).
When P) is activated to a high outputs when V _k as a pull-up driving signal (PD), the precharge control signal is an internal signal of the memory device (PC) transitions from high to low, the main power supply ( Vcc) to pull-up drive signal (PD)
After the main power supply (Vcc) is maintained at the pull-up drive signal (PD) for a predetermined time, the ground potential is output as the pull-up drive signal (PD). Line sense amplifier. 10. The precharge control signal (PD) according to claim 9, wherein the pull-up drive signal (PD) generating means includes a NAND gate for inputting the offset compensation signal (CMP) and a precharge control signal (PC). A fourth delayer for delaying the inverted value of the PC by a predetermined time; an output of the fourth delayer and the precharge control signal (P
An OR gate for inputting the imagewise signal and C), the first configured to output a first 2AND gate allowed to enter the output of s the NAND gates and OR gates respectively, as _{V K} pull-up driving signal according to the output of the NAND gate (PD) A transistor; a second transistor configured to output a main power supply (Vcc) as a pull-up drive signal (PD) according to the output of the OR gate; and a ground-up pull-up drive signal (PD) according to the output of the second AND gate. And a third transistor configured to output the bit line sense amplifier. 11. The first bit line (B) according to claim 10, wherein the first bit line (B) is controlled according to the precharge control signal (PC).
L) and a precharge means for precharging the second bit line (/ BL). 12. The precharge means according to claim 11, wherein said precharge means controls said first bit line (BL) and said second bit line (/) according to said precharge control signal (PC).
A bit line sense amplifier, comprising: fifth switching means for switching between BL and BL. 13. A precharge means according to claim 12, wherein said precharge means switches between said first bit line (BL) and said half drive voltage application terminal according to said precharge control signal (PC). Switching means: A bit line sense amplifier comprising: a seventh switching means for switching between the second bit line (/ BL) and a half drive voltage application terminal according to the precharge control signal (PC). 14. A bit line sense amplifier for a memory device having a reproduction amplifier means, wherein a first inverter inverts and outputs data input from a first bit line (BL): an output from a second bit line (/ BL). A second inverter for inverting and outputting the data to be output: first and second switching means for respectively switching between the output terminals of the first and second inverters and a predetermined data bus according to the output signal (GYi) of the external column decoder: A third method for switching between the input / output terminals of the first and second inverters according to an external offset compensation signal (CMP);
And a fourth switching means. 15. A first and second inverter for inverting and outputting data input from a first bit line (BL) and a second bit line (/ BL), and the first and second inverters according to an offset compensation signal (CMP). In a method of controlling a bit line sense amplifier having first and second switching means for switching between an input / output terminal of a second inverter, precharging the bit line: input terminals of each of the first and second inverters Switching the first and second switching means to connect the first terminal and the output terminal to compensate for the offset; and activating only the word line to change only the voltage of the bit line connected to the cell, And one of the second inverters performs an amplification operation, and the other one uses the input / output voltage after offset compensation as it is. The method of the bit line sense amplifier, characterized in that it comprises a step to maintain. 16. The pull-up driving voltage of the first and second inverters according to claim 15, wherein a pull-up driving voltage of the first and second inverters is a main power supply (Vcc) during precharge minus a threshold voltage of a pull-up transistor provided in the first and second inverters. (V _T ). A method for controlling a bit-in sense amplifier, comprising: 17. The method of claim 16, wherein the pull-up driving voltages of the first and second inverters are controlled to be a main power supply during an offset compensation and a sensing operation. 18. Oite to claim 15, said first and second inverters, a control method of a bit line sense amplifier, characterized in that it is controlled inactive during a write operation. 19. The method according to claim 16, wherein the offset compensation signal (CMP) is generated so that data is transmitted from the data bus to the bit line.