JPH0785696A - Semiconductor memory - Google Patents

Abstract

PURPOSE:To relieve the burden of a user and to make easy to use by making exchangeable an address region being a partially operating product of a dynamic type RAM and the like in its inside. CONSTITUTION:In a dynamic type RAM constituted with plural unit storage regions MARY 0-3 selectively specified according to address signals supplied in time-division manner from address signal input terminals A0-Ai, address conversion circuits XB, YB which fixes an internal address signal in accordance with address signals Xi, Yi are provided. And when a device in which a part of a normal storage region is a partial operation product is shipped, an address region is made changeable arbitrarily by an address conversion circuit. Thereby, the burden of a user can be relieved and the device can be made easy to use.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, for example, a so-called partial operation product (partial product).
The present invention relates to a technology which is particularly effective when used for a dynamic RAM (random access memory) etc.

[0002]

2. Description of the Related Art There is a semiconductor memory device such as a dynamic RAM having a plurality of memory arrays (memory mats). Further, as the scale and capacity of such dynamic RAMs are increasing, as one of effective means for increasing the product yield, for example, only the storage area corresponding to a part of the memory array is normally dynamic. A method of shipping a type RAM or the like as a partial operation product with a reduced storage capacity is adopted.

A dynamic RAM provided with a plurality of memory arrays is disclosed in, for example, Japanese Patent Laid-Open No. 3-214669.
No. etc.

[0004]

In a dynamic RAM or the like having a plurality of memory arrays, its storage area is divided into a plurality of unit storage areas with the memory array as a unit, and each unit storage area is divided into address signals, for example. Is selectively specified according to the upper predetermined bits of. Conventionally,
An address area such as a dynamic RAM, which is a partially operating product with a normal part of the memory area, is the same as a so-called all operating product in which all memory areas are normal,
There is a storage area that cannot be accessed depending on the combination of the upper predetermined bits of the address signal. Therefore, in order to access only a normal storage area such as a dynamic RAM which is shipped as a partial operation product, the logical level of the upper predetermined bits of the address signal is fixed externally by hardware or software. I have to do it. This increases the burden on the user and deteriorates the usability of the dynamic RAM or the like, especially in the dynamic RAM or the like that adopts the address multiplex system.

An object of the present invention is to provide a semiconductor memory device such as a dynamic RAM in which an address area as a partial operation product can be arbitrarily converted therein.
Another object of the present invention is to reduce the burden on the user of a dynamic RAM, which is shipped as a partially operating product, and to improve its usability.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0007]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows. That is, a nonvolatile memory element such as a fuse is added to a dynamic RAM or the like, which has a plurality of unit storage areas selectively designated according to a predetermined bit of an address signal and is a partially operating product with a normal partial unit storage area. And an address conversion circuit for fixing the internal address signal corresponding to the predetermined bit of the address signal to the high level or the low level.

[0008]

According to the above means, the address area of the dynamic RAM or the like shipped as the partial operation product is set to a desired address including, for example, the head address regardless of the logical level of the predetermined bit of the address signal given from the outside. Can be converted to a region. As a result, it is possible to reduce the burden on the user of the dynamic RAM, which is shipped as a partial operation product, and improve its usability.

[0009]

1 is a block diagram of an embodiment of a dynamic RAM to which the present invention is applied. Further, FIG. 4 shows an address allocation diagram of an embodiment in which the dynamic RAM of FIG. 1 is shipped as a so-called all-operation product. Based on these figures, the outline of the configuration and operation of the dynamic RAM of this embodiment will be described first. The circuit elements forming each block in FIG. 1 are not particularly limited, but are formed on one semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique.

In FIG. 1, the dynamic RAM of this embodiment is not particularly limited, but four memory arrays MARY0 to MARY arranged so as to occupy most of the semiconductor substrate surface.
Let ARY3 be its basic component. These memory arrays, together with the corresponding peripheral circuits, will be described later.
Each of the unit storage areas is selectively designated according to the X address signal AXi and the Y address signal AYi of the most significant bit and corresponds to one quarter of the storage area of the dynamic RAM. In this embodiment, the dynamic RAM in which the memory arrays MARY0 to MARY3 and the peripheral circuits can all function normally is shipped as an all-operation product, and the dynamic RAM in which a part thereof can function normally is a partially-operation product. Shipped. As a result, the dynamic RAM having a partial defect can be commercialized without being discarded as a defective product, and the product yield can be increased.

The memory arrays MARY0 to MARY3 are
A plurality of word lines arranged in parallel in the vertical direction in the figure, a plurality of sets of complementary bit lines arranged in parallel in the horizontal direction, and a plurality of pairs of complementary bit lines arranged in a grid pattern at the intersections of these word lines and complementary bit lines. And a large number of dynamic memory cells.

The word lines forming the memory arrays MARY0 to MARY3 are associated with the corresponding X address decoder XD0.
To XD3, and each of them is alternatively set to the selected state. The X address decoders XD0 to XD3 have i-bit complementary internal address signals X0 * to Xi-1 * (here, for example, the non-inverted internal address signal X0T and the inverted internal address signal X0B, excluding the most significant bit) from the X address buffer XB. Is also expressed as a complementary internal address signal X0 *, and a non-inverted signal or the like which is selectively set to a high level when it is validated has T added to the end of its signal name. An inverted signal or the like that is selectively brought to a low level when it is made valid is represented by adding B to the end of the signal name. The same applies hereinafter). Further, corresponding memory array selection signals M0 to M3 are respectively supplied from the memory array selection circuit MS,
An internal control signal XDG (not shown) is commonly supplied from the timing generation circuit TG. X address signals AX0 to AXi are supplied to X address buffer XB via address input terminals A0 to Ai in a time division manner, and internal control signal XL is supplied from timing generation circuit TG.

The X address buffer XB has an X address signal AX supplied via address input terminals A0 to Ai.
0 to AXi are fetched and held according to the internal control signal XL, and complementary internal address signals X0 * to Xi * are formed based on these X address signals. this house,
The most significant bit complementary internal address signal Xi * is supplied to the memory array selection circuit MS, and the other complementary internal address signals X0 * to Xi-1 * are X address decoder XD.
Is supplied to. The X address decoders XD0 to XD3 are
When the internal control signal XDG is set to the high level and the corresponding memory array selection signals M0 to M3 are set to the high level, the operation state is selectively made. In this operation state, the X address decoders XD0 to XD3 decode the complementary internal address signals X0 * to Xi-1 * and selectively change the corresponding word lines of the memory arrays MARY0 to MARY3 to the high level selected state. To do.

In this embodiment, the X address buffer XB fixes the logic level of the complementary internal address signal Xi * of the most significant bit to a high level or a low level regardless of the corresponding X address signal AXi, and is shipped as a partial operation product. An address conversion circuit for converting the address area of the dynamic RAM is included. The configuration and operation of this address conversion circuit will be described in detail later.

Next, the memory arrays MARY0 to MARY
Complementary bit lines constituting the three are sense amplifiers SA0-S0.
It is coupled to the corresponding unit circuit of A3. Sense amplifier S
An internal control signal PA (not shown) is supplied from the timing generation circuit TG to A0 to SA3. In addition, the corresponding memory array selection signal M from the memory array selection circuit MS
0 to M3 are respectively supplied to the Y address decoder YD
Bit line selection signals for selectively designating complementary bit lines are supplied from 0 to YD3, respectively.

Each of the unit circuits constituting the sense amplifiers SA0 to SA3 has memory arrays MARY0 to MARY.
It includes a unit amplifier circuit and a switch MOSFET pair provided corresponding to each complementary bit line of Y3. Among them, the unit amplifier circuits of the respective unit circuits are selectively and simultaneously activated by setting the internal control signal PA and the corresponding memory array selection signals M0 to M3 to a high level, and the memory arrays MARY0 to MARY3. The minute read signal output from the plurality of memory cells coupled to the selected word line via the corresponding complementary bit line is amplified to be a high level or low level binary read signal. On the other hand, the switch MOSFET pair of each unit circuit is alternatively turned on by setting the corresponding bit line selection signal to the high level, and the memory arrays MARY0 to MARY3.
Corresponding complementary bit line and complementary common data line CD0 * to
CD3 * is selectively connected.

The Y address decoders YD0 to YD3 include
From the Y address buffer YB, i-bit complementary internal address signals Y0 * to Yi-1 * excluding the most significant bit are commonly supplied. Further, corresponding memory array selection signals M0 to M3 are respectively supplied from the memory array selection circuit MS, and an internal control signal YDG (not shown) is commonly supplied from the timing generation circuit TG. Y address buffer Y
Y address signals AY0 to AYi are time-divisionally supplied to B via address input terminals A0 to Ai, and an internal control signal YL is supplied from the timing generation circuit TG.

The Y address buffer YB is supplied with the Y address signal AY via the address input terminals A0 to Ai.
0 to AYi are fetched and held according to the internal control signal YL, and complementary internal address signals Y0 * to Yi * are formed based on these Y address signals. this house,
The most significant bit complementary internal address signal Yi * is supplied to the memory array selection circuit MS, and the other complementary internal address signals Y0 * to Yi-1 * are supplied to the Y address decoder Y.
It is commonly supplied to D0 to YD3. The Y address decoders YD0 to YD3 are selectively operated by setting the internal control signal YDG to the high level and the corresponding memory array selection signals M0 to M3 to the high level, and the complementary internal address signals Y0 * to Decode Yi-1 *,
The corresponding bit line selection signal is alternatively set to the high level.

In this embodiment, the Y address buffer YB fixes the logic level of the complementary internal address signal Yi * of the most significant bit to a high level or a low level regardless of the corresponding Y address signal AYi, and is shipped as a partial operation product. An address conversion circuit for converting the address area of the dynamic RAM is included. The configuration and operation of this address conversion circuit will be described in detail later.

The memory array selection circuit MS has the most significant bit complementary internal address signals Xi * and Yi supplied from the X address buffer XB and the Y address buffer YB.
* Is decoded and the corresponding memory array selection signal M0
~ M3 is alternatively set to high level. These memory array select signals correspond to the corresponding X address decoders XD0 to XD0.
It is supplied to the XD3 and the sense amplifiers SA0 to SA3 and the Y address decoders YD0 to YD3, respectively, and to the corresponding unit circuits of the write amplifier WA and the main amplifier MA, respectively.

In this embodiment, in the memory array selection signal M0, the complementary internal address signals Xi * and Yi * are both logic "0" (here, the non-inverted signal thereof is at low level and the inverted signal thereof is at high level). State is logical "0"
And the opposite state is called logic "1". The same applies hereafter) and is selectively set to a high level,
The memory array selection signal M1 is the complementary internal address signal X.
i * is logic "1" and complementary internal address signal Yi
It is selectively set to a high level on the condition that * is set to logic "0". Similarly, the memory array selection signal M2 is selectively set to a high level on condition that the complementary internal address signal Xi * is logic "0" and the complementary internal address signal Yi * is logic "1". The memory array selection signal M3 is selectively set to the high level on condition that the complementary internal address signals Xi * and Yi * are both set to the logic "1".

When the inverted internal address signals XiB and YiB are set to the high level and the memory array selection signal M0 is set to the high level, in the dynamic RAM, the memory array MARY0 and its peripheral circuits operate as shown in FIG. Then, the corresponding unit storage area is set to the selected state. When the non-inverted internal address signal XiT and the inverted internal address signal YiB are set to the high level and the memory array selection signal M1 is set to the high level, the memory array MARY1 and its peripheral circuits are activated and the corresponding unit storage area Is selected. Further, the inverted internal address signal XiB and the non-inverted internal address signal Y
When iT is set to the high level and the memory array selection signal M2 is set to the high level, the memory array MARY2 and its peripheral circuits are activated and the corresponding unit storage area is set to the selected state. Then, the non-inverted internal address signal X
When iT and YiT are set to the high level and the memory array selection signal M3 is set to the high level, the memory array MAR
Y3 and its peripheral circuits are activated, and the corresponding unit storage area is selected.

Complementary common data lines CD0 * -CD3 *, to which designated complementary bit lines of memory arrays MARY0-MARY3 are selectively connected, are coupled to the output terminals of the corresponding unit circuits of the write amplifier WA, and It is coupled to the input terminal of the corresponding unit circuit of main amplifier MA. The input terminal of each unit circuit of the write amplifier WA is commonly coupled to the output terminal of the data input buffer DIB, and the output terminal of each unit circuit of the main amplifier MA is commonly coupled to the input terminal of the data output buffer DOB. The input terminal of the data input buffer DIB is coupled to the data input terminal Din, and the output terminal of the data output buffer DOB is coupled to the data output terminal Dout. Light amplifier WA
An internal control signal WP (not shown) is commonly supplied from the timing generation circuit TG to each of the unit circuits, and the corresponding memory array selection signal M0 is supplied from the memory array selection circuit MS.
~ M3 are respectively supplied. Also, the main amplifier MA
The corresponding memory array selection signals M0 to M3 are supplied from the memory array selection circuit MS to the respective unit circuits, and an internal control signal DOC (not shown) is supplied from the timing generation circuit TG to the data output buffer DOB.

The data input buffer DIB is used when the dynamic RAM is selected in the write mode.
The write data supplied via the data input terminal Din is fetched and transmitted to each unit circuit of the write amplifier WA. Each unit circuit of the write amplifier WA has an internal control signal W
When P is set to the high level and the corresponding memory array selection signals M0 to M3 are set to the high level, the operation state is alternatively performed. In this operating state, each unit circuit of the write amplifier WA forms a predetermined complementary write signal based on the write data transmitted from the data input buffer DIB, and the corresponding complementary common data lines CD0 * -CD0.
Write to the selected memory cell of the memory arrays MARY0 to MARY3 via 3 *.

On the other hand, each unit circuit of the main amplifier MA is
When the dynamic RAM is brought into the selected state in the read mode, the corresponding memory array selection signals M0 to M3 are brought to the high level to selectively bring it into the operating state.
In this operating state, each unit circuit of the main amplifier MA has the corresponding complementary common data lines CD0 * to C from the selected memory cells of the memory arrays MARY0 to MARY3.
The read signal output via D3 * is further amplified and transmitted to the data output buffer DOB. The data output buffer DOB is selectively activated by receiving the high level of the internal control signal DOC, and outputs the read signal transmitted from the main amplifier MA to the outside of the dynamic RAM via the data output terminal Dout.

The timing generation circuit TG selectively forms the above various internal control signals based on the row address strobe signal RASB, the column address strobe signal CASB, and the write enable signal WEB which are externally supplied as start control signals. And dynamic RA
Supply to each part of M.

2 and 3 are circuit diagrams of one embodiment of the X address buffer XB and the Y address buffer YB included in the dynamic RAM of FIG. 1, respectively.
FIG. 4 shows an array selection condition diagram of fuses included in the X address buffer XB and the Y address buffer YB of FIGS. 2 and 3. Further, FIG. 6 shows an address allocation diagram of an embodiment in an untreated state of the dynamic RAM of FIG. 1 which is shipped as a partially operating product.
FIG. 7 shows an address allocation diagram of the embodiment in the treated state. Based on these drawings, the specific configuration and operation of the X address buffer XB and the Y address buffer YB included in the dynamic RAM of this embodiment, the address conversion method, and the characteristics thereof will be described. 2 and 3, a MOSFET (metal oxide semiconductor type field effect transistor) whose channel (back gate) part is indicated by an arrow. In this specification, MOSFET is a generic term for an insulated gate field effect transistor. Is a P-channel type and is shown separately from an N-channel MOSFET without an arrow. Further, in FIGS. 6 and 7, the shaded portion of the storage area indicates a unit storage area which is inaccessible because the corresponding memory array or peripheral circuit has some defect.

In FIG. 2, X address buffer XB
Are i + 1 unit X address buffers UXB0 to UXBi provided corresponding to the address input terminals A0 to Ai.
Equipped with. Of these, the i unit X address buffers UXB0 to UXBi-1 corresponding to the lower i bits are shown in FIG.
Of the unit X address buffer UXB0, one input terminal of the unit X address buffer UXB0 is coupled to the corresponding address input terminal A0 or the like and the other input terminal receives the internal signal R0.
And a NAND gate NA1 for receiving in common. Here, the internal signal R0 is selectively set to a high level in response to the falling edge of the row address strobe signal RASB when the dynamic RAM is selected. As a result, the output signal of the NAND gate NA1 is normally at a high level like the power supply voltage of the circuit, and when the dynamic RAM is in the selected state and the internal signal R0 is at a high level, the corresponding X address signal AX0 or the like is generated. Logical "1"
On the condition that it is, a low level like the ground potential of the circuit is selectively made.

The output signal of the NAND gate NA1 is output via the inverter N2 to the corresponding clocked inverter CN1.
Is supplied to the data input terminal of. The internal control signal XL is connected to the control terminals of these clocked inverters CN1.
Are commonly supplied, and their output terminals are commonly coupled to the output terminals of the corresponding clocked inverter CN2. The data input terminal of the clocked inverter CN2 is supplied with its output signal, that is, the inverted signal of the inverted internal address signal X0B or the like by the inverter N3, that is, the non-inverted internal address signal X0T, and its control terminal is supplied with the internal control signal XL. Inverted and non-inverted signals are commonly supplied.

As a result, the clocked inverter CN1
Is in a transmission state in which an inversion signal of the output signal of the corresponding NAND gate NA1 by the inverter N2 is transmitted as an inversion internal address signal X0B or the like while the internal control signal XL is at a low level, and the internal control signal XL is at a high level. When it is said that it is in a non-transmission state. The clocked inverter CN2 forms a latch circuit together with the corresponding inverter N3 by feeding back the output signal of the corresponding inverter N3 to its input terminal while the internal control signal XL is at the high level. Therefore, the transmission state is set, and the non-transmission state is set when the internal control signal XL is set to the low level. As a result, address input terminal A
0-Ai-1 input X address signal AX0
.About.AXi-1 are transmitted from the corresponding NAND gate NA1 through the inverter N2 and the clocked inverter CN1 from the time when the internal signal R0 is set to the high level until the internal control signal XL is set to the high level, and the complementary internal signals are transmitted. The address signals X0 * to Xi-1 * are obtained. Then, from the time when the internal control signal XL is set to the high level to the time when it is returned to the low level, the logic level immediately before that is held by the latch circuit including the clocked inverter CN2 and the inverter N3.

On the other hand, the unit X address buffer UXBi of the X address buffer XB includes a NAND gate NA2 corresponding to the NAND gate NA1 and inverters N2 and N.
3 and inverters N4 and N5 corresponding to 3 and clocked inverters CN3 and CN4 corresponding to clocked inverters CN1 and CN2. The output signal of the clocked inverter CN4 is supplied to the input terminal of the inverter N5 and further to one input terminal of the NAND gate NA3. The output signal of the inverter N5 is supplied to the data input terminal of the clocked inverter CN4 and also to one input terminal of the NOR gate NO1. The output signal of the NAND gate NA3 is supplied to one input terminal of the NAND gate NA4, and the NOR gate NO3
The output signal of 1 is supplied to one input terminal of the NOR gate NO2.

The other input terminal of the NOR gate NO1 is
The non-inverted output signal FC1T of the fuse circuit FC1 is supplied, and the inverted output signal FC1B thereof is supplied to the other input terminal of the NAND gate NA3. Also, NOR Gate N
The non-inverted output signal FC2T of the fuse circuit FC2 is supplied to the other input terminal of O2, and the inverted output signal FC2B thereof is supplied to the other input terminal of the NAND gate NA4. The output signal of the NOR gate NO2 is the non-inverted internal address signal XiT of the most significant bit, and the output signal of the NAND gate NA4 is the inverted internal address signal XiB.

The fuse circuit FC1 includes a fuse F1 (nonvolatile memory element) provided between the power supply voltage of the circuit and the input terminal of the inverter N6, although not particularly limited thereto. Between the input terminal of the inverter N6 and the ground potential of the circuit, there is a resistor R1 and an N-channel MOSFET Q1 whose gate receives the output signal of the inverter N6.
And are provided in parallel form. The output signal of the inverter N6 becomes the inverted output signal FC1B of the fuse circuit FC1 via the inverter N7, and further becomes the non-inverted output signal FC1T via the inverter N8. This causes the non-inverted output signal FC1T and the inverted output signal F of the fuse circuit FC1.
C1B is set to the low level and the high level when the fuse F1 is in the connected state, and is set to the high level and the low level when the fuse F1 is in the disconnected state.

Similarly, the fuse circuit FC2 includes a fuse F2 (nonvolatile memory element) provided between the power supply voltage of the circuit and the input terminal of the inverter N9. A resistor R2 and an N-channel MOSFET Q2 for receiving the output signal of the inverter N9 at its gate are provided in parallel between the input terminal of the inverter N9 and the ground potential of the circuit. The output signal of the inverter N9 becomes the inverted output signal FC2B of the fuse circuit FC2 through the inverter N10, and further passes through the inverter N11 and the non-inverted output signal FC.
It becomes 2T. As a result, the non-inverted output signal FC2T and the inverted output signal FC2B of the fuse circuit FC2 are set to the low level and the high level, respectively, when the fuse F2 is in the connected state, and to the high level and the low level, respectively, when the fuse F2 is in the disconnected state. It

In this embodiment, the fuse circuit FC1
The fuses F1 and F2 included in FC2 and FC2 are both connected in the initial state in which the dynamic RAM is formed on the silicon wafer, and only one of them is selectively cut in response to the result of the probe test in the wafer state. To be in a state. In the initial state of the dynamic RAM in which the fuses F1 and F2 are both connected, the non-inverted output signal FC1T of the fuse circuits FC1 and FC2
And FC2T are both at low level, and the inverted output signals FC1B and FC2B are both at high level. Therefore, in the unit X address buffer UXBi, the NOR gates NO1 and NO2 and the NAND gates NA3 and NA4 are both in the transmission state, and the complementary internal address signal Xi * is input through the address input terminal Ai as shown in FIG. In accordance with the X address signal AXi.

Upon receiving the result of the probe test, the fuse F1
When only one is cut, the non-inverted output signal FC1T of the fuse circuit FC1 is set to the high level and the inverted output signal FC1B is set to the low level. Therefore, in the unit X address buffer UXBi, the output signal of the NOR gate NO1 is forcibly set to the low level and the output signal of the NAND gate NA3 is forcibly set to the high level. At this time, the non-inverted output signal FC2T and the inverted output signal FC2B of the fuse circuit FC2 remain at the low level and the high level, respectively, and the NOR gate NO2 and the NAND gate NA4.
Are left in a transmitting state. As a result, the non-inverted internal address signal XiT and the inverted internal address signal XiB are fixed to the high level and the low level, respectively, and the complementary internal address signal Xi * is fixed to the logic "1" as shown in FIG.

On the other hand, when only the fuse F2 is cut off in response to the result of the probe test, the fuse circuit FC2
The non-inverted output signal FC2T is set to the high level and the inverted output signal FC2B is set to the low level. Therefore, in the unit X address buffer UXBi, the output signal of the NOR gate NO2, that is, the non-inverted internal address signal XiT is forcibly set to the low level, and the output signal of the NAND gate NA4, that is, the inverted internal address signal XiB is forcibly set to the high level. . At this time, the non-inverted output signal FC1T and the inverted output signal FC1B of the fuse circuit FC1 are kept at the low level and the high level, respectively, and the NOR gate N
O1 and NAND gate NA3 are left in the transmitting state. However, since the output signals of the subsequent NOR gate NO2 and NAND gate NA4 are fixed to low level and high level, respectively, the complementary internal address signal Xi * is fixed to logic "0" as shown in FIG.

Next, the Y address buffer YB includes, as shown in FIG. 3, i + 1 unit Y address buffers UYB0 to UYBi provided corresponding to the internal signals a0 to ai, that is, the address input terminals A0 to Ai. , NOR gate NO added to the unit Y address buffer UYBi
3, NO4 and NAND gates NA7 and NA8, and fuse circuits FC3 and FC4. These circuits have exactly the same configuration as the corresponding circuits of the X address buffer XB, take in Y address signals AY0 to AYi input via address input terminals A0 to Ai in accordance with internal control signal YL, and complement each other. Address signal Y0
As shown in FIG. 5, the fuses F3 and F4 are selectively cut off in accordance with the result of the probe test of the dynamic RAM, and the complementary internals of the most significant bit are transmitted. It operates to selectively fix the address signal Yi * to the logic "1" or "0".
That is, the complementary internal address signal Yi * is supplied to the fuse F.
Dynamic type R in which both 3 and F4 are connected
In the initial state of AM, it is according to the Y address signal AYi input through the address input terminal Ai. However, when only the fuse F3 is cut off in response to the result of the probe test, the logic "1" is output. Fixed to fuse F
When only 4 is disconnected, it is fixed to logic "0".

As described above, the X address buffer XB of this embodiment has NOR gates NO1 and NO provided at the subsequent stage of the most significant bit unit X address buffer UXBi.
2 and NAND gates NA3 and NA4, and fuse circuits FC1 and FC2 that form an address conversion circuit together with these logic gates. Further, the Y address buffer YB is provided with NOR gates NO3 and N3 provided in the subsequent stage of the most significant bit unit Y address buffer UYBi.
O4 and NAND gates NA7 and NA8 are included, and fuse circuits FC3 and FC4 that form an address conversion circuit together with these logic gates are included.

As illustrated in FIG. 6, the memory array M
When a dynamic RAM in which only the unit storage area corresponding to ARY3 normally functions is shipped as a partially operating product, the fuse F that constitutes the fuse circuits FC1 to FC4
In the unprocessed state in which all of 1 to F4 are left in the connected state, the X address signal AXi and the Y address signal AYi are respectively the complementary internal address signals Xi * and Yi.
Memory array MA transmitted as * and not functioning normally
RY0 to MARY2 may be selected. Therefore, the user of the dynamic RAM is
It is necessary to take measures by hardware or software so that the address signal AXi and the Y address signal AYi do not become a combination designating these memory arrays.

However, as shown in FIG. 7, after the cutting process of the fuses F1 and F3 included in the fuse circuits FC1 and FC3 is performed in view of the above defect, the complementary internal address of the most significant bit is set. Signal Xi *
And Yi * are fixed to logic "1" regardless of the X address signal AXi and the Y address signal AYi, and only the memory array MARY3 is always selected. That is, the user of the dynamic RAM needs to use the most significant bit X address signal AXi and Y address signal A.
Ignoring the address input terminal Ai corresponding to Yi, that is, i-1 bit X address signals AX0 to AXi-1
In addition, only by inputting the Y address signals AY0 to AYi-1, in other words, it is possible to recognize and access the address area of the partially normal unit storage area as the same address area including the head address. , Is released from the address conversion process for each partial operation product. As a result, it is possible to reduce the burden on the user of the dynamic RAM shipped as a partial operation product and improve its usability.

As shown in the above embodiment, the dynamic RA which is shipped as a partial operation product of the present invention.
When applied to a semiconductor memory device such as M, the following operational effects can be obtained. That is, (1) a nonvolatile RAM such as a fuse is added to a dynamic RAM or the like which has a plurality of unit storage areas selectively designated according to a predetermined bit of an address signal and which has a normal partial unit storage area as a partial operation product. Address conversion circuit for fixing the internal address signal, which includes the memory storage element and corresponds to the above-mentioned predetermined bit of the address signal, to the high level or the low level, so that the address area of the dynamic RAM or the like shipped as a partial operation product can be reduced. An effect is obtained that, for example, the desired address area including the start address can be converted regardless of the logical level of the predetermined bit of the address signal given from the outside. (2) According to the above item (1), it is possible to reduce the burden on the user of the dynamic RAM and improve the usability.

The invention made by the inventor of the present invention has been specifically described based on the embodiments, but the invention is not limited to the above-mentioned embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in FIG. 1, memory arrays MARY0 to MARY3 corresponding to respective unit storage areas of the dynamic RAM are shown.
Can be divided into a plurality of sub memory arrays, or a plurality of memory arrays can be associated with one unit storage area. The number of unit storage areas, that is, the number of memory arrays can be set arbitrarily, and the selection condition thereof is also arbitrary. The dynamic RAM can be a partial operation product having a plurality of normal memory arrays. In this embodiment, memory array selection signals M0-M3
According to the above, the memory arrays MARY0 to MARY3 and the peripheral circuits are selectively activated, but these may always be simultaneously activated, and only the unit circuits of the write amplifier WA and the main amplifier MA may be alternatively activated. . However, in this case, it is necessary to provide a means for selectively making the portion corresponding to the inaccessible unit storage area of the dynamic RAM, which is a partial operation product, inactive. Furthermore, the dynamic RAM has an X address signal and a Y address.
It is possible to adopt a so-called address non-multiplex system in which address signals are input from separate address input terminals, and the block configuration, start control signals and internal control signals, and the names and combinations of address signals are variously implemented. It can take any form.

In FIGS. 2 and 3, the fuse circuit FC
The fuses F1 to F4 provided in 1 to FC4 can be replaced with, for example, wiring cut by a laser beam or the like, and for fixing the logic level of the complementary internal address signals Xi * and Yi * of the most significant bit. As the non-volatile storage element, for example, EPROM or EEPROM
It is also possible to use a read-only memory such as. The NAND gates NA5 and NA6 provided at the input stage of the unit Y address buffers UYB0 to UYBi can share the NAND gates NA1 and NA2 of the unit X address buffers UXB0 to UXBi. An address signal for designating a memory array, that is, a unit storage area is an X address signal AXi and a Y address signal A of the most significant bit.
The address area is not limited to Yi, and it is not essential that the address area after the address conversion includes the start address. Further, various embodiments such as specific configurations of the X address buffer XB and the Y address buffer YB, the polarity and absolute value of the power supply voltage, and the conductivity type of the MOSFET can be adopted.

In the above description, the case where the invention made by the present inventor was mainly applied to the dynamic RAM which is the field of application which was the background of the invention has been described.
It is not limited to that, static RAM
The present invention can also be applied to various memory integrated circuit devices such as the above and digital integrated circuit devices incorporating such memory integrated circuit devices. The present invention can be widely applied to a semiconductor memory device having at least a plurality of unit storage areas and shipped as a partial operation product.

[0046]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, a nonvolatile memory element such as a fuse is added to a dynamic RAM or the like, which has a plurality of unit storage areas selectively designated according to a predetermined bit of an address signal and is a partially operating product with a normal partial unit storage area. By providing an address conversion circuit for fixing the internal address signal corresponding to the above-mentioned predetermined bit of the address signal to the high level or the low level, the address area of the dynamic RAM etc. shipped as a partial operation product is It can be converted into a desired address area including, for example, the head address regardless of the logical level of the predetermined bit of the applied address signal. As a result, it is possible to reduce the burden on the user of the dynamic RAM, which is shipped as a partial operation product, and improve its usability.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a dynamic RAM to which the present invention is applied.

2 is a circuit diagram showing an embodiment of an X address buffer included in the dynamic RAM of FIG.

3 is a circuit diagram showing an embodiment of a Y address buffer included in the dynamic RAM of FIG.

FIG. 4 is an address allocation diagram showing an embodiment in which the dynamic RAM of FIG. 1 is shipped as a fully operating product.

5 is an array selection condition diagram of fuses included in an X address buffer and a Y address buffer of the dynamic RAM of FIG.

FIG. 6 is an address allocation diagram showing an example in an untreated state when the dynamic RAM of FIG. 1 is shipped as a partially operating product.

7 is an address allocation diagram showing an embodiment in a treated state when shipped as a partially operating product of the dynamic RAM of FIG.

[Explanation of symbols]

MARY0 to MARY3 ... Memory array, SA0
SA3 ... Sense amplifier, XD0 to XD3 ... X address decoder, YD0 to YD3 ... Y address decoder, MS ... Memory array selection circuit, XB ... X
Address buffer, YB ... Y address buffer, W
A ... Light amplifier, MA ... Main amplifier, DIB
... Data input buffer, DOB ... Data output buffer, TG ... Timing generation circuit. UXB0-U
XBi ... Unit X address buffer, UYB0 to UY
Bi ... Unit Y address buffer, FC1 to FC4
..Fuse circuits NA1-NA8 ... Nand (NA
ND) gate, NO1 to NO4 ... NOR gate, CN1 to CN8 ... Clocked inverter, N
1-N22 ... Inverter, F1-F4 ... Fuse, R1-R4 ... Resistor, Q1-Q4 ... N-channel MOSFET.

Claims (5)

[Claims] 1. A semiconductor comprising an address conversion circuit for converting an address area which is a partially operating product with a normal part of the storage area and which is assigned to the normal part of the storage area. Storage device. 2. The semiconductor device according to claim 1, wherein the converted address area assigned to a normal part of the storage area is the same address area including a substantial start address. Storage device. 3. The semiconductor memory device comprises a plurality of unit storage areas selectively designated according to a predetermined bit of an address signal, and a normal part of the storage area is the unit storage area. The semiconductor memory device according to claim 1 or 2, wherein the semiconductor memory device is set as a unit. 4. The address conversion circuit includes a non-volatile memory element for fixing an internal address signal corresponding to the predetermined bit of the address signal to a high level or a low level. Item 2
Alternatively, the semiconductor memory device according to claim 3. 5. The semiconductor memory device is a dynamic RAM, and the substantial writing to the nonvolatile memory element is performed during a probe test of the dynamic RAM. The semiconductor memory device according to claim 1, claim 2, claim 3, or claim 4.