JP2000030487A - Semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the reliability by enhancing the product yield of a dynamic tape RAM, etc., provided with a lot of banks and by achieving a memory module of the dynamic type RAM, etc., which cannot be accessed to. SOLUTION: A dynamic type RAM, etc., provided with a lot of banks BNK0- BNKn containing redundant elements for defect relief is provided with a bank- enable register BR in which each of the banks detects more defective elements than the number of redundant elements to be installed and stores the unrelievable and unaccessible state and product-ships the dynamic RAM, etc., as mostly good memories. Moreover, prescribed pieces of this are combined in a chip state to form a memory module, this module is provided with a memory controller in which the memory contents of the bank-enable register BR of the each dynamic RAM, etc., are read and the address allocation is performed to the each bank and the each dynamic RAM, etc., is provided with a bank selecting circuit BS which selectively prohibits access to the each bank according to the storage contents of the bank-enable register BR.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, for example, a dynamic memory device having a large number of banks.
The present invention relates to an AM (random access memory) or the like and a technique particularly effective for improving the product yield.

[0002]

2. Description of the Related Art A dynamic RAM or the like whose basic components are a memory array including word lines and bit lines arranged orthogonally and dynamic memory cells arranged in a grid at the intersections of these word lines and bit lines. Semiconductor storage device. Further, a predetermined number of redundant word lines and redundant bit lines are provided in a memory array such as a dynamic RAM, and these redundant word lines and redundant bit lines are selectively used as a word line or a bit line in which a failure is detected. A so-called defect remedy method that enhances the product yield of a dynamic RAM or the like by replacing it is known.

On the other hand, in recent years, the technology for miniaturization and high integration of semiconductor integrated circuits has been remarkably advanced, and dynamic RAMs and the like have also benefited from them, and are increasing in capacity and scale. Under such circumstances, a so-called multi-bank approach, in which a memory array and peripheral circuits are divided into a large number of banks and accessed in parallel, is becoming common as one means for promoting a high-speed dynamic RAM or the like. 8
A dynamic RAM having a relatively large number of banks such as 16 or 16 banks is being commercialized. Each of the banks provided in the dynamic RAM includes a row address register for holding a row address for selecting a word line, a row address decoder for decoding a row address and selectively selecting a designated word line. In each bank, the word line selection operation is performed independently, and the word lines to which different row addresses are assigned are simultaneously selected.

[0004]

Prior to the present invention, the present inventors engaged in the development of the above-described multi-bank type dynamic RAM, and noticed the following problems. That is, the dynamic RAM has a large number of banks, each of which includes a predetermined number of redundant word lines and redundant bit lines for defect relief. However, defect relief by redundant word lines and redundant bit lines
Since it is performed on a bank-by-bank basis, if a defective word line or bit line cannot be repaired in any bank,
Even if a redundant word line or a redundant bit line not used for another bank is left, it cannot be repaired. As a result, the dynamic RAM becomes defective and cannot be shipped, thereby reducing the product yield of the dynamic RAM.

An object of the present invention is to improve the yield of products such as a dynamic RAM having a large number of banks. Another object of the present invention is to realize a memory module which can be configured by combining inaccessible dynamic RAMs and the like in a chip state, for example, and to improve the reliability of the memory module.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[0007]

The following is a brief description of an outline of a typical invention among the inventions disclosed in the present application. That is, in a dynamic RAM or the like having a large number of banks each including a redundant element for repairing a defect, a defective element in each bank is detected, for example, in which the number of redundant elements is larger than the number of installed redundant elements. Is provided, and a dynamic RAM or the like including a bank that has become inaccessible can be stored in a most-good memory (M
The product is shipped as GM (Mostly Good Memory). Also, such a dynamic RAM
A memory module is constructed by combining a predetermined number of such devices in a chip state, reading the stored contents of a bank enable register of each dynamic RAM and the like, and assigning addresses to each bank of each dynamic RAM and the like. A memory controller is provided. Further, each dynamic RAM or the like is provided with a bank selection circuit for selectively inhibiting access to each bank in accordance with the contents stored in the bank enable register.

According to the above-described means, it is possible to ship a dynamic RAM or the like including a bank that has become inaccessible, and to increase the product yield of the dynamic RAM or the like. In addition, by combining such dynamic RAMs and the like with arbitrary address assignment, a memory module having a desired storage capacity can be easily configured, and the reliability of the memory module can be improved.

[0009]

FIG. 1 is a block diagram showing a first embodiment of a dynamic RAM according to the present invention. An outline of the configuration and operation of the dynamic RAM according to this embodiment will be described with reference to FIG. Although the circuit elements constituting each block in FIG. 1 are not particularly limited, a known MOSFET (metal oxide semiconductor type field effect transistor; in this specification, MOSFET
(Referred to as an insulated gate field effect transistor) on a single chip (semiconductor substrate) surface such as single crystal silicon by an integrated circuit manufacturing technique. Further, the memory array MARY of the banks BNK0 to BNKn
Actually takes a shared sense system, and the memory array MARY and its peripheral circuits are divided into a number of sub-memory arrays, but this is not shown because it is not directly related to the gist of the present invention.

In FIG. 1, the dynamic RAM of this embodiment includes n + 1 banks BNK0 to BNKn. Each bank occupies most of the layout area, and a memory array MARY and a row serving as a peripheral circuit are arranged. It includes an address register RA, a row address decoder RD, a sense amplifier SA, a column address decoder CD, a write amplifier WA, and a main amplifier MA.

The memory arrays MARY forming the banks BNK0 to BNKn have a predetermined number of word lines and a predetermined number of redundant word lines for relieving defects arranged in parallel in the vertical direction in FIG. It includes a predetermined number of sets of complementary bit lines and a predetermined number of sets of redundant bit lines for repairing defects. At the intersection of these word lines and bit lines, an information storage capacitor and an address selection MO
A large number of dynamic memory cells composed of SFETs are arranged in a grid.

The word lines and redundant word lines constituting the memory array MARY of the banks BNK0 to BNKn are coupled to the corresponding row address decoder RD, and each of them is selectively selected. To the row address decoders RD of the banks BNK0 to BNKn, an internal X address signal of a predetermined bit is supplied from the corresponding row address register RA, and an internal control signal RG is commonly supplied from the timing generation circuit TG. Further, a row address register RA of each bank is commonly supplied with an X address signal of a predetermined bit from an address buffer AB, and commonly supplied with an internal control signal RL from a timing generation circuit TG. Further, the address buffer A
B has an address input terminal A0 from an external access device.
Through Aj through j + 1-bit address signals A0-Aj
And an internal control signal CE (not shown) is supplied from the timing generation circuit TG.

The address buffer AB takes in address signals A0 to Aj supplied from external access devices via address input terminals A0 to Aj in accordance with an internal control signal CE, and outputs them as input address signals. Upper predetermined bits of the input address signal are supplied to the bank address register BA as a bank address signal. The lower predetermined bit is used as an X address signal in bank B.
It is supplied commonly to the row address registers RA of NK0 to BNKn, or supplied to the column address register CA as a Y address signal. An internal control signal BL is further supplied to the bank address register BA from the timing generation circuit TG, and an internal bank address signal as an output signal thereof is supplied to the bank selection circuit BS.

The bank address register BA takes in and holds a bank address signal input via an address buffer AB in accordance with an internal control signal BL, and, as an internal bank address signal, a bank selection circuit BS.
To communicate. Further, the bank selection circuit BS decodes the internal bank address signal supplied from the bank address register BA, and selectively sets the corresponding bits of the bank selection signals BS0 to BSn to high level. These bank selection signals BS0 to BSn are supplied to corresponding bank BNK.
0 to BNKn, and a row address register RA, a row address decoder RD,
It is used as a drive selection signal for selectively turning on the column address decoder CD, the sense amplifier SA, the write amplifier WA, the main amplifier MA, and the like.

The row address register RA, which is a substantial row address holding means, includes bank selection signals BS0 to BS
When the corresponding bit of n is set to the high level, the X address signal transmitted from the address buffer AB is taken in and held according to the internal control signal RL, and the internal X address signal is formed based on these X address signals. , To the corresponding row address decoder RD. The row address decoder RD, which is a decoding means, is selectively activated when the internal control signal RG is set to the high level and the corresponding bits of the bank selection signals BS0 to BSn are set to the high level. The internal X address signal supplied from the address register RA is decoded or compared with a defective address assigned to each redundant word line to select a designated word line or redundant word line of the corresponding memory array MARY. To the selected state. Thereby, the banks BNK0 to BNK0
The BNKn can fetch different X address signals into its row address register RA and perform independent word line selection operations.

Next, the complementary bit lines and the redundant bit lines forming the memory array MARY of the banks BNK0 to BNKn are respectively coupled to the corresponding sense amplifiers SA. A sense amplifier SA of each bank is supplied with a bit line selection signal and a redundant bit line selection signal of a predetermined bit (not shown) from a corresponding column address decoder CD, and an internal control signal PA from a timing generation circuit TG.
And an internal control signal PC (not shown) are commonly supplied. A column address register CA commonly supplies an internal Y address signal of a predetermined bit to the column address decoders CD of the banks BNK0 to BNKn, and an internal control signal CG from the timing generation circuit TG. The column address register CA is supplied with a predetermined address Y address signal from the address buffer AB, and is supplied with an internal control signal CL and an internal clock signal CU (not shown) from the timing generation circuit TG.

Column address register CA includes a binary counter that performs a stepping operation according to internal clock signal CU. This binary counter converts the Y address signal supplied from the address buffer AB into an internal control signal C.
L, the Y address signals are taken in accordance with L, and the Y address signals are used as count initial values to perform a stepping operation in accordance with the internal clock signal CU, thereby sequentially forming internal Y address signals, and the column address decoders CD of the banks BNK0 to BNKn. To supply.

The column address decoders CD of the banks BNK0 to BNKn are selectively activated when the internal control signal CG is at a high level and the corresponding bits of the bank selection signals BS0 to BSn are at a high level.
The internal Y address signal supplied from the column address register CA is decoded or compared with a defective address assigned to each redundant bit line to select a corresponding bit of the bit line select signal or the redundant bit line select signal. High level.

The sense amplifiers SA of the banks BNK0 to BNKn include a predetermined number of unit circuits provided corresponding to the respective complementary bit lines of the memory array MARY. Each of these unit circuits is a bit line precharge circuit and a unit. It includes an amplifier circuit and a pair of switch MOSFETs. Among them, the bit line precharge circuit of each unit circuit selectively and simultaneously operates in response to the high level of the internal control signal PC, and the non-inverted and inverted signal lines of the corresponding complementary bit lines of the memory array MARY. Are respectively precharged to a predetermined intermediate potential. The unit amplifier circuit of each unit circuit is selectively and simultaneously operated by the internal control signal PA being at a high level and the corresponding bits of the bank selection signals BS0 to BSn being at a high level. A small read signal output from a predetermined number of memory cells coupled to a selected word line of the memory array MARY to be output via a corresponding complementary bit line is amplified to produce a high level or low level binary read signal.

On the other hand, in the switch MOSFET of each unit circuit of the sense amplifier SA, the bit corresponding to the bit line selection signal or the redundant bit line selection signal supplied from the column address decoder CD is alternatively set to a high level. And k + 1 sets are selectively turned on, and k + 1 sets of complementary bit lines or redundant bit lines and complementary common data lines CD0 * to CDk * of the memory array MARY (here, for example, the non-inverted common data line CD0 and the inverted The common data line CD0B is indicated by asterisks (*) like a complementary common data line CD0 *, and the so-called inverted signal or the like which is selectively made low when it is enabled is referred to by its name. The connection state is selectively set to a state between the suffix B and the same hereinafter).

The complementary common data lines CD0 * to CDk * are
It is coupled to the write amplifier WA and the main amplifier MA.
The write amplifier WA is connected to the data input buffer I via write data buses WDB0 to WDBk on the other side.
B, and the other side of the main amplifier MA is coupled to the data output buffer OB via read data buses RDB0 to RDBk. The write amplifier WA and the main amplifier MA of each bank are connected to a complementary common data line CD.
It includes k + 1 unit write amplifiers and unit main amplifiers provided corresponding to 0 * to CDk *, and has k + 1 data input buffers IB and data output buffers OB provided corresponding to data input / output terminals D0 to Dk. Of unit input buffers or unit output buffers.

The output terminals of the unit write amplifiers of the write amplifiers WA of the banks BNK0 to BNKn and the output terminals of the unit main amplifiers of the main amplifier MA are commonly coupled to the corresponding complementary common data lines CD0 * to CDk *, respectively. . The input terminals of each unit write amplifier of the write amplifier WA are connected to the write data buses WDB0 to WDB.
k, the output terminal of each unit main amplifier of the main amplifier MA is connected to the read data bus R.
The data output buffer OB is coupled to an output terminal of a corresponding unit output buffer via DB0 to RDBk. An input terminal of each unit input buffer of the data input buffer IB and an output terminal of each unit output buffer of the data output buffer OB are commonly coupled to corresponding data input / output terminals D0 to Dk, respectively.

An internal control signal WP is commonly supplied from a timing generation circuit TG to each unit write amplifier of the write amplifier WA, and an internal control signal RP (not shown) is supplied to each unit main amplifier of the main amplifier MA. An internal control signal CE (not shown) is commonly supplied from the timing generation circuit TG to each unit input buffer of the data input buffer IB, and an internal control signal OC (not shown) is supplied to each unit output buffer of the data output buffer OB.
Are commonly supplied.

When the dynamic RAM is selected in the write mode, each unit input buffer of the data input buffer IB is selectively activated by receiving the high level of the internal control signal CE. K + 1 input via data input / output terminals D0 to Dk
The bit write data is taken in, held, and transmitted to the corresponding unit write amplifiers of the write amplifiers WA of the banks BNK0 to BNKn via the write data buses WDB0 to WDBk. At this time, each unit write amplifier of the write amplifier WA is selectively activated by setting the internal control signal WP to the high level and the corresponding bits of the bank selection signals BS0 to BSn to the high level. After the write data transmitted from buffer IB is converted into a predetermined complementary write signal, memory array M is supplied via complementary common data lines CD0 * -CDk *.
The data is written into the (k + 1) selected memory cells of ARY.

On the other hand, when the dynamic RAM is selected in the read mode, the internal control signal RP is set to the high level and the unit main amplifiers of the main amplifier MA of each bank are set to the high level and correspond to the bank selection signals BS0 to BSn. Is set to a high level to selectively operate, and complementary common data lines CD0 * to CDk * are selected from the (k + 1) selected memory cells of the memory array MARY.
After amplifying the read signal output via the data output buffer OB, the read signal is transmitted to the corresponding unit output buffer of the data output buffer OB via the read data buses RDB0 to RDBk. At this time, each unit output buffer of the data output buffer OB selectively operates in response to the high level of the internal control signal OC, and reads data supplied from the main amplifier MA via the data input / output terminals D0 to Dk. Output to the outside.

In this embodiment, the dynamic RA
M further includes a bank enable register BR. The bank enable register BR is supplied with an internal control signal BRR from the timing generation circuit TG, and its output signal is output to the read data buses RDB0 to RDBk as bank enable signals BR0 to BRn. The internal control signal BRR is normally at a low level when the dynamic RAM is in a non-selected state, and at a predetermined timing when the dynamic RAM is selected in a predetermined operation mode, that is, in a bank enable register read mode. Is selectively set to a high level.

The bank enable registers BR include (n + 1) unit bank enable registers provided corresponding to the banks BNK0 to BNKn. Each of these unit bank enable registers is, for example, a corresponding bank BNK0 to BNKn in the inspection process. A fuse which is selectively cut when a defective word line or a defective bit exceeding the number of redundant word lines or redundant bit lines is detected and cannot be repaired and becomes inaccessible; When the RAM is set to the bank enable register read mode and the internal control signal BRR is set to the high level, the cutoff state of the corresponding fuse is replaced with a logic signal, and a clock signal output to the read data buses RDB0 to RDBk as the bank enable signals BR0 to BRn. Inva And a motor. These bank enable signals BR0-BRn are connected to read data bus RDB
0 to RDBk to the external access device via the data output buffer OB and the data input / output terminals D0 to Dk.

As a result, the dynamic RAM of this embodiment can be shipped as a most-good memory while including the bank in an inaccessible state, and the external access device is provided with a bank enable register. It is possible to identify whether or not each bank of the dynamic RAM is accessible by the read mode. As a result, the product yield of the dynamic RAM can be increased, and a predetermined number of these dynamic RAMs can be combined in a chip state to configure a memory module having a desired storage capacity. In addition, dynamic RAM
Bank enable register BR and dynamic type R
The specific configuration and operation of the memory module formed by combining the AM and the features thereof will be described later in detail.

The timing generation circuit TG selectively selects the various internal control signals based on a row address strobe signal RASB, a column address strobe signal CASB, and a write enable signal WEB supplied from an external access device as a start control signal. And supply it to each part of the dynamic RAM.

FIG. 2 is a circuit diagram showing one embodiment of the bank enable register BR included in the dynamic RAM of FIG. The specific configuration and operation of the bank enable register BR included in the dynamic RAM of this embodiment will be described with reference to FIG. In the following description regarding the bank enable register BR, the unit bank enable registers UBR0 to UBRn will be described using the unit bank enable register UBR0. In the following circuit diagrams, all illustrated MOSFETs are N-channel MOSFETs.

In FIG. 2, bank enable registers BR include (n + 1) unit bank enable registers UBR0 to UBR0 provided corresponding to banks BNK0 to BNKn.
UBRn, and each of these unit bank enable registers is a unit bank enable register UBR.
As represented by 0, one fuse F1 is included. The upper terminal of this fuse F1 is coupled to the supply voltage of the circuit, and its lower terminal is connected to two N-channel MOSFETs.
Coupled to the ground potential of the circuit via N1 and N2 and to the input terminal of inverter V1. MOS
The gate of FET N1 is coupled to the supply voltage of the circuit and
The gate of SFET N2 is coupled to the output terminal of inverter V1. The output terminal of inverter V1 is further coupled to the input terminal of clocked inverter G1, and the output signal of clocked inverter G1 provides data output buffer O as corresponding bank enable signals BR0-BRn.
B, that is, output to the read data buses RDB0 to RDBk.

Unit bank enable registers UBR0 to UBR0
The internal control signal BRR is commonly supplied from the timing generation circuit TG to the non-inverted control terminal of the clocked inverter G1 constituting the UBRn, and the inverted control terminal receives the inverted signal of the internal control signal BRR by the inverter V2 in common. Supplied to As a result, the clocked inverter G1 of each unit bank enable register receives the high level of the internal control signal BRR and selectively enters a transmission state,
The input signal, that is, the output signal of the inverter V1 is logically inverted to obtain bank enable signals BR0 to BRn.

In this embodiment, the unit bank enable registers UBR0 to UBR0 of the bank enable register BR are used.
As described above, for example, the fuses F1 constituting the UBRn are connected to the corresponding banks BNK0 to BNK0-B
A defective word line or a defective bit exceeding the number of redundant word lines or redundant bit lines installed in NKn is detected, and when the defective word line or the defective bit becomes inaccessible and cannot be repaired, it is selectively cut off. When the dynamic RAM is set to the bank enable register read mode, the internal control signal BRR is set to a high level at a predetermined timing.

When the corresponding banks BS0 to BSn are in an accessible state and the fuse F1 is not in a disconnected state,
In the unit bank enable registers UBR0 to UBRn of the bank enable register BR, the input signal of the inverter V1 becomes high level, and the output signal thereof becomes low level. Therefore, the dynamic RAM is set to the bank enable register read mode and the internal control signal B
When RR is set to the high level, the output signal of the corresponding clocked inverter G1, that is, the bank enable signal B
R0 to BRn are each at a high level.

On the other hand, when the corresponding bank BS0-BSn is inaccessible and the corresponding fuse F1 is cut off, the input signal of the inverter V1 becomes low in the unit bank enable registers UBR0-UBRn of the bank enable register BR. , And the output signal becomes high level. Therefore, the dynamic type R
When AM is set to the bank enable register read mode and the internal control signal BRR is set to the high level, the output signal of the corresponding clocked inverter G1, that is, the bank enable signals BR0 to BRn are set to the low level.

As described above, the bank enable register BR stores the bank BNK0-BNK of the dynamic RAM.
NKn acts as a non-volatile memory for storing that the NKn has become inaccessible, and selectively reads the storage contents of the unit bank enable registers UBR0 to UBRn in response to the high level of the internal control signal BRR. It acts to output to an external access device as BRn. In addition, the external access device outputs the read bank enable signals BR0 to BRn.
Based on the dynamic RAM banks BNK0-BNK
It is possible to easily determine whether or not NKn is in an accessible state, thereby stopping access to the inaccessible bank of the dynamic RAM, combining a predetermined number of these dynamic RAMs in a chip state, A memory module having a desired storage capacity can be easily configured.

FIG. 3 is a block diagram showing one embodiment of a memory module including the dynamic RAM of FIG. The specific configuration, operation, and characteristics of the memory module of this embodiment will be described with reference to FIG.

In FIG. 3, the memory module has m + 1 dynamic RAs combined in a chip state.
M (DRAM0-DRAMm) and one memory controller MCTL commonly provided for these dynamic RAMs. Among them, k + 1-bit data DB0 to DBk are input to or output from the memory controller MCTL via a data bus DB0 to DBk from an unillustrated central processing unit or the like. Further, an address strobe signal ASB and a read / write signal R / WB are supplied via an address strobe signal line ASB and a read / write signal line R / WB, respectively, which serve as a control bus, and p + 1 via address buses AB0 to ABp.
Bit address signals AB0 to ABp are supplied.

On the other hand, a dynamic RAM (DRAM 0
To DRAMm), k + 1-bit data is commonly input or output from the memory controller MCTL to the data input / output terminals D0 to Dk.
Aj is commonly supplied with j + 1-bit address signals A0 to Aj. The external terminals RASiB and CASiB of each dynamic RAM are provided with a corresponding row address strobe signal R from the memory controller MCTL.
AS0B to RASmB and column address strobe signals CAS0B to CASmB are supplied, respectively, and a write enable signal WEB is commonly supplied to the external terminal WEB. Needless to say, dynamic R
AM (DRAM0 to DRAMm) is selectively designated according to a corresponding row address strobe signal RAS0B to RASmB or a column address strobe signal CAS0B to CASmB, and is activated.

In this embodiment, a dynamic RAM (DRAM0-DRAM) constituting a memory module
m) is, as described above, n + 1 banks BNK0-BNK
NKn, all or some of which are, for example, a most-good memory including a bank in which a defective word line or a defective bit in excess of the number of redundant word lines or redundant bit lines is detected and becomes inaccessible; Is done. Also, each dynamic RAM is stored in a bank BNK.
A bank enable register BR for storing whether or not each of the bank enable registers 0 to BNKn is in an accessible state, reading the stored contents of the bank enable register BR, and reading the bank enable register that can be output from the data input / output terminals D0 to Dk Mode.

Therefore, the memory controller MCTL of the memory module first accesses the dynamic RAMs (DRAM0-DRAMm) in the bank enable register read mode at the time of power-on, and determines which bank of each dynamic RAM can access. Is determined. Further, based on the information, the address space specified by the address signals AB0 to ABp is sequentially allocated to each bank of each dynamic RAM without waste, and the row address strobe signals RAS0B to RASm are allocated.
B and column address strobe signal CAS0B ~
The data is written into an address table (not shown) to correspond to CASmB. Then, the address strobe signal ASB is set to the low level by the central processing unit at the preceding stage, and the device code input as the upper predetermined bits of the address signals AB0 to ABp is set to a combination given to the memory module, thereby selectively performing dynamic control. Type R
Normal access to the AM (DRAM0 to DRAMm) is started, and a read or write operation is selectively executed according to the read / write signal R / WB.

As described above, in the memory module of this embodiment, any one of the banks BNK0 to BNKn is inaccessible, and the dynamic RAM (DRAM0) shipped as a most-good memory is shipped.
To DRAMm) in a chip state, each bank of each dynamic RAM is provided with a memory controller M which has read the access enable / disable state in a bank enable register read mode.
The address space is allocated without waste by the CTL. As a result, it is possible to increase the product yield of the dynamic RAM, and to improve
A memory module having a desired storage capacity can be easily configured by combining dynamic RAMs, which are shipped as products, with arbitrary addresses.

FIG. 4 is a block diagram showing a second embodiment of the dynamic RAM to which the present invention is applied. FIG. 5 shows one of the bank enable registers BR included in the dynamic RAM of FIG. A circuit diagram of the embodiment is shown. The dynamic RAM according to this embodiment basically follows the embodiment shown in FIGS. 1 and 2, and therefore, a description will be added only for parts different from this.

In FIG. 4, the dynamic RAM of this embodiment has n + 1 banks BNK0 to BNKn,
Bank enable register BR and bank selection circuit BS
And Among them, the bank enable register BR
Are output from the bank enable signals BR0-BR
Rn is supplied to the data output buffer OB via the read data buses RDB0 to RDBk, and the other output signal is supplied to the bank selection circuit BS as bank enable signals BE0 to BEn. An internal control signal BRR is supplied from the timing generation circuit TG to the bank enable register BR, and a bank address signal of a predetermined bit is supplied from the bank address register BA to the bank selection circuit BS.

In this embodiment, as shown in FIG. 5, the bank enable register BR stores the bank BNK0.
To BNKn are provided in correspondence with n + 1 unit bank enable registers UBR0 to UBRn, and each of these unit bank enable registers has an input terminal as shown by the unit bank enable register UBR0 in FIG. Includes an inverter V3 coupled to the output terminal of inverter V1. This inverter V3
Are supplied to the bank selection circuit BS as bank enable signals BE0 to BEn. As a result, the bank enable signals BE0 to BEn are set to the high level when the corresponding banks BNK0 to BNKn are accessible and the corresponding fuse F1 is not in the cut state, and the corresponding banks BNK0 to BNKn are inaccessible. And when the corresponding fuse F1 is in the cut state, it is set to the low level.

On the other hand, the bank selection circuit BS decodes the internal bank address signal supplied from the bank address register BA, and selectively sets the corresponding bits of the bank selection signals BS0 to BSn to high level, thereby setting the bank BNK.
0 to BNKn are the corresponding bank selection signals BS0 to BS
In response to the alternate high level of n, it is selectively activated. However, in the case of this embodiment, the bank selection circuit BS
Is selectively provided on condition that the corresponding bank enable signals BE0 to BEn are at a high level, in other words, on condition that the bank specified by the internal bank address signal is accessible. The selection signals BS0 to BSn are set to a high level. As a result, in this embodiment, while obtaining the same operation and effect as those of the embodiments of FIGS. 1 and 2, even when an inaccessible bank is designated by an external access device, access to the bank is selectively prohibited. Thus, the reliability of the dynamic RAM and the memory module can be improved.

The operation and effect obtained from the above embodiment are as follows. That is, (1) In a dynamic RAM or the like having a large number of banks each including a redundant element for repairing a defect, a state is detected in which a defective element in each bank is larger than the number of the redundant elements installed and cannot be repaired and cannot be accessed. A dynamic RAM including the inaccessible bank is provided by providing a bank enable register for storing the inaccessible bank and shipping a dynamic RAM or the like including the inaccessible bank as a most-good memory.
And the like can be shipped as a product, and the product yield can be increased.

(2) According to the above item (1), a predetermined number of dynamic RAMs and the like including the inaccessible banks are combined in a chip state to constitute a memory module.
Read the contents of the bank enable register, etc.
By providing a memory controller for assigning an address to each dynamic RAM or the like, a dynamic RAM or the like including an inaccessible bank can be combined with an arbitrary address assignment to easily configure a memory module having a desired storage capacity. The effect is obtained.

(3) In the above items (1) and (2), the dynamic RAM or the like is provided with a bank selection circuit for selectively prohibiting access to each bank in accordance with the contents stored in the bank enable register. The effect is obtained that the reliability of the dynamic RAM and the memory module can be improved.

Although the invention made by the inventor has been specifically described based on the embodiment, the invention is not limited to the above embodiment, and various modifications can be made without departing from the gist of the invention. Needless to say, there is. For example, in FIGS. 1 and 4, banks BNK0 to BNKn
As described above, the memory array MARY actually adopts a shared sense system and is divided into a plurality of sub memory arrays including its peripheral circuits. Further, the memory array M
The ARY does not necessarily require that redundant word lines and redundant bit lines be included, and the ARY includes banks BNK0 to BN0.
The reason why Kn is made inaccessible is not limited only to the case where defect repair by the redundant element becomes impossible. Further, when the row address decoder RD or the word line driving circuit has a latch function for keeping the designated word line in a selected state, and acts as a substantial row address holding means, the row address register RA is provided for each bank. No need to provide. The block configuration of the dynamic RAM can take various embodiments, and the names and combinations of the activation control signal, the address signal, the internal control signal, and the like, and their effective levels are not restricted by this embodiment.

2 and 5, the unit bank enable register UBR0 of the bank enable register BR
To UBRn can be replaced with, for example, a PROM (programmable read only memory) or an EEPROM (electrically erasable / programmable read only memory) or the like. The specific configuration of the bank enable register, the polarity of the power supply voltage, the conductivity type of the MOSFET, and the like can take various embodiments.

In FIG. 3, a dynamic RAM (D
Address assignment to the banks BNK0 to BNKn of the RAM0 to DRAMm) is performed by, for example, a central processing unit.
A method of writing to the L address table can be adopted. The block configuration and the bus configuration of the memory module are just examples, and do not limit the gist of the present embodiment.

In the above description, a dynamic RAM and a plurality of dynamic RAMs, which are fields of application in which the invention made by the present inventor is the background, have been described.
The present invention has been described with respect to a case in which the present invention is applied to a memory module in which a memory integrated circuit is combined. For example, various memory integrated circuit devices such as a synchronous DRAM having a dynamic RAM as a basic configuration, and such a memory integrated circuit The present invention can be applied to a logic integrated circuit device including the device, a computer system, and the like. INDUSTRIAL APPLICABILITY The present invention can be widely applied to a semiconductor memory device having at least a plurality of banks and an apparatus or a system including such a semiconductor memory device.

[0054]

The effects obtained by typical ones of the inventions disclosed in the present application will be briefly described as follows. That is, a dynamic RAM having a large number of banks each including a redundant element for repairing a defect.
For example, each bank is provided with a bank enable register for storing that a defective element is detected, for example, in which the number of redundant elements is larger than the number of installed redundant elements, and the cell cannot be repaired and cannot be accessed. Products such as dynamic RAMs are shipped as most-good memory. In addition, such a dynamic type R
A memory module is configured by combining a predetermined number of AMs or the like in a chip state, and a memory controller for reading the storage contents of a bank enable register such as each dynamic RAM and assigning an address to each bank is provided in the memory module. Furthermore, each dynamic type R
The AM or the like is provided with a bank selection circuit for selectively prohibiting access to each bank according to the stored contents of the bank enable register. As a result, it is possible to ship a dynamic RAM or the like including a bank that has become inaccessible, thereby improving the product yield of the dynamic RAM or the like. In addition, such a dynamic RAM or the like can be combined by arbitrary address assignment to easily configure a memory module having a desired storage capacity, and the reliability of the dynamic RAM or the like and the memory module can be improved.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a first embodiment of a dynamic RAM to which the present invention is applied.

FIG. 2 is a circuit diagram showing one embodiment of a bank enable register included in the dynamic RAM of FIG. 1;

FIG. 3 is a block diagram showing one embodiment of a memory module including the dynamic RAM of FIG. 1;

FIG. 4 is a block diagram illustrating a dynamic RAM according to a second embodiment of the present invention;

FIG. 5 is a circuit diagram showing one embodiment of a bank enable register included in the dynamic RAM of FIG. 4;

[Explanation of symbols]

BNK0 to BNKn: Bank, MARY: Memory array, RD: Row address decoder, RA: Row address register, SA: Sense amplifier, WA: Write amplifier, MA: Main amplifier, CD0 * to CDk *
... Complementary data lines, WDB0 to WDBk, write data bus, RDB0 to RDBk, read data bus, CD, column address decoder, CA, column address register, BA, bank address register, BS, bank Selection circuit, BS0 to BSn ... bank selection signal, AB ... address buffer, A0 to Aj ...
... Address signal or its input terminal, BR ... Bank enable register, BR0-BRn ... Bank enable signal, IB ... Data input buffer, OB ... Data output buffer, D0-Dk ... Input or output data or its input Output terminal, TG ... Timing generation circuit, RA
SiB: a row address strobe signal or its input terminal, CASiB: a column address strobe signal or its input terminal, WEB ... a write enable signal or its input terminal. UBR0 to UBRn unit bank enable register, F1 fuse, V1 to V3 inverter, G1 clocked inverter, N1 to N2
... N-channel MOSFET. MCTL memory controller, DRAM0 to DRAMm dynamic RAM, DB0 to DBk data bus, ASB
Address strobe signal, R / WB ... Read / write signal, AB0-ABp ... Address bus, RAS0B-R
ASmB: Row address strobe signal, CAS0B
.About.CASmB... Column address strobe signal. BE
0-BEn... Bank enable signal.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Yutaka Ito 3-16-6 Shinmachi, Ome-shi, Tokyo F-term in the Hitachi, Ltd. Device Development Center Co., Ltd. 5B024 AA15 BA18 BA29 CA07 CA15 CA21 5F083 AD00 LA06 ZA10 5L106 AA01 CC01 CC04 CC21 CC31 GG05 GG07

Claims (6)

[Claims] 1. A plurality of banks each including a substantial row address holding unit and a decoder unit, and capable of independently performing a word line selecting operation, and that each of the banks is inaccessible due to a fault. And a bank enable register for storing the data. 2. The bank according to claim 1, wherein the banks each include a redundancy element for repairing a defect, and each of the banks is selectively disabled when the repair of the defect by the redundancy element is disabled. A semiconductor memory device characterized by the above. 3. The semiconductor memory device according to claim 1, wherein the storage contents of said bank enable register can be output to an external access device as needed. 4. The bank according to claim 1, wherein the bank enable register includes a plurality of unit bank enable registers provided corresponding to each of the banks. A semiconductor memory device, wherein each of the enable registers includes a fuse selectively cut off when the corresponding bank is in an inaccessible state. 5. The bank according to claim 1, wherein the access to each of the banks can be selectively inhibited according to a corresponding storage content of the bank enable register. A semiconductor memory device characterized by the following. 6. The semiconductor memory device according to claim 1, wherein each of the semiconductor memory devices is formed on a single chip surface. A memory module is configured by a predetermined number of the memory modules, and the memory module includes a memory controller that reads stored contents of the bank enable registers of the predetermined number of the semiconductor storage devices and performs address assignment. A semiconductor memory device characterized by the above-mentioned.