JP3404170B2 - Semiconductor memory device bank selection method and its semiconductor memory device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bank selection method for a semiconductor memory device and the semiconductor memory device.

In recent years, semiconductor memory devices have been advanced in speed and integration. As a means for increasing the speed, in a chip layout, a memory cell array is divided into a plurality of memory cell arrays (banks).
There is a semiconductor memory device that operates independently while synchronizing with each other. High integration is also required in such a semiconductor memory device.

[0003]

2. Description of the Related Art Conventionally, a memory cell array formed on a chip is divided into a plurality of memory cells, and the plurality of divided memory cell arrays, that is, each bank is operated as an independent memory while synchronizing with each other, thereby performing high-speed data reading. A DRAM that enables the above has been proposed. Figure 8 shows the DR
It is a block circuit diagram of AM. For convenience of explanation, the number of banks is two. The chip is provided with a first memory cell array (hereinafter referred to as a first bank) 71 and a second memory cell array (hereinafter referred to as a second bank) 81. Further, the chip is provided with a row address buffer 72 for the first bank 71, a row decoder 73, a column decoder 74 and a clock generation circuit 75. Further, the chip has a row address buffer 82 for the second bank 81, a row decoder 83, and a column decoder 84.
And a clock generation circuit 85. Furthermore, the chip is provided with a column address buffer 91 and an input / output buffer 92 for the first bank 71 and the second bank 81.

The row address buffers 72 and 82 of the first and second banks 71 and 81 receive an active command corresponding to the fall of the row address strobe signal (bar RAS signal) of the conventional general-purpose DRAM. Input address data (row address signal). Further, the column address buffer 91 inputs address data (column address signal) when a precharge command corresponding to the rising edge of the bar RAS signal of the conventional general-purpose DRAM is input. For convenience of explanation, each bank 71, 8
1 is a memory of 16 words × 1 bit, and the row address signal and the column address signal each have 3 bits.

Now, when an active command is input, address data, that is, 3-bit row address signals A0, A1, A2 are input, and the row address buffer 7
Reference numerals 2 and 82 receive the row address signals A0 and A1 of the lower 2 bits of the 3 bits. The row address signal A2 of the most significant bit is input to the clock generation circuits 75 and 85 of the first and second banks 71 and 81. When the content of the row address signal A2 of the most significant bit is "H level", the clock generation circuit 75 of the first bank 71 outputs the clock φ0 of H level, and the clock generation circuit 85 of the second bank 81 is of L level. Outputs clock φ1. On the contrary, when the content of the row address signal A2 is "L level", the clock generating circuit 75 of the first bank 71 outputs the clock φ0 of L level and the clock generating circuit 85 of the second bank 81.
Outputs an H level clock φ1.

The row address buffers 72 and 82 of the first and second banks 71 and 81 respectively respond to H-level clocks φ 0 and φ 1, and row decoders 73 and 83 of the next stage.
The row address signals A0 and A1 are output to the. Therefore,
Either the first bank 71 or the second bank 81 is selected based on the content of the row address signal A2 of the most significant bit.

If the first bank 71 is selected, the row decoder 73 selects and activates one word line based on the row address signals A0 and A1. Then, the column address strobe signal (bar C
When a read / write command corresponding to the fall of the (AS signal) is input, the column address buffer 91 inputs the address data, that is, the column address signal.

The column address buffer 91 inputs the lower 2 bits of the column address signals A3 and A4 of the 3-bit column address signals A3, A4 and A5, and outputs both signals A3 and A4 to the column decoders 74 and 84, respectively. Output. Based on the column address signals A3 and A4, the column decoders 74 and 84 operate in the first and second banks 71 and 8, respectively.
Open the corresponding bit line of 1 and select the first or second selected
The data in the memory cells of the banks 71 and 81 are amplified by the sense amplifiers 76 and 86 and output to the input / output buffer 92.

At this time, the input / output buffer 92 receives the column address signal A5 of the most significant bit of the 3-bit column address signals A3, A4, A5. The most significant bit column address signal A5 has the same content as the most significant bit row address signal A2 input based on the previous active command. That is, when the row address signal A2 is at H level, the column address signal A5 is at H level. When the row address signal A2 is at L level, the column address signal A5 is at L level.

When the H-level column address signal A5 is input, the input / output buffer 92 inputs and outputs only the data output from the sense amplifier 76 of the first bank 71. Conversely, when the L-level column address signal A5 is input, the sense amplifier 86 of the second bank 81
Input and output only the data output from. And
In this case, since the input / output buffer 92 inputs the column address signal A5 of H level, it inputs the data output from the sense amplifier 76 of the first bank 71 and outputs it to the external device.

That is, in the case of continuously reading data in this DRAM, when the data of the predetermined memory cell of the first bank 71 is being read, the next predetermined memory cell of the second bank 81 is read. A row address signal for reading data can be transferred to the row address buffer 82 of the second bank 81. On the other hand, in a DRAM that operates without dividing the memory cell array into a plurality of blocks, the next address data cannot be input until one data is read. Therefore, the DRAM having a plurality of banks can be read out at high speed as much as the next address can be input.

[0012]

By the way, in the DRAM having the first and second banks 71 and 81, the row address buffer 72 for the first bank 71 and the row address buffer for the second bank 81 are provided. And an address buffer 82. That is, as many row address buffers as bank are required. Therefore, the number of circuits is increased as compared with a DRAM that operates without dividing the memory cell array into a plurality of pieces, which is a problem in reducing the chip area or increasing the storage capacity.

The present invention has been made to solve the above problems, and an object thereof is to reduce the number of address buffers and the number of circuits in a semiconductor memory device having a plurality of banks. It is an object of the present invention to provide a bank selection method for a semiconductor memory device and a semiconductor memory device capable of suppressing the increase in memory capacity and increasing the storage capacity or reducing the chip area accordingly.

[0014]

FIG. 1 is a diagram for explaining the principle of the present invention. One row address buffer 1 is provided for a plurality of banks and inputs a row address signal. The row decoders 2 and 3 are provided for each bank and are both connected to the row address buffer 1. The control circuit unit 4 includes a clock generation circuit 5 and a control circuit 6.
The clock generation circuit 5 inputs a row address signal designating each bank and outputs a signal designating a corresponding bank to the control circuit 6. The control circuit 6 activates the row decoder of the designated bank of the row decoders 2 and 3 based on the signal designating the bank and outputs the row address signal input by the buffer 1 to the row address buffer 1. It is output to each row decoder 2 and 3 . Claim 1
According to the invention described in 1), a row address signal is input to one row address buffer, and a first row decoder corresponding to the first memory bank is activated based on a first signal designating the first memory bank. And deactivating the first row decoder based on an output signal of the first row decoder, and designating a second memory bank after the first row decoder is deactivated. The gist is to activate the second row decoder corresponding to the second memory bank based on the signal of 2. According to a second aspect of the present invention, in a semiconductor memory device in which a memory cell array is divided into a plurality of banks, one row address buffer provided for the plurality of banks and one row address buffer provided for each bank are provided. Activates a row decoder connected to the row address buffer and a row decoder of a bank designated based on a signal designating each bank, and deactivates the row decoder based on an output signal of the row decoder. The gist of the present invention is to include a control circuit unit for realizing the conversion. According to a third aspect of the present invention, in the semiconductor memory device according to the second aspect , one row address buffer, a first memory bank, and a first row decoder corresponding to the first memory bank, A second memory bank, a second row decoder corresponding to the second memory bank, and the first row decoder based on a signal designating the bank.
Row decoder or a control circuit for activating the second row decoder, and based on an output signal of the first row decoder or the second row decoder, the first row decoder or the second row decoder. The gist is to inactivate the row decoder. According to a fourth aspect of the invention, in a semiconductor memory device in which a memory cell array is divided into a plurality of banks, the plurality of banks are grouped, one row address buffer provided for each group, and each bank. A control circuit for activating a row decoder provided and a row decoder of a designated bank on the basis of a signal designating each bank and deactivating the row decoder on the basis of an output signal of the row decoder. The main point is to have a section. The invention according to claim 5 is
The semiconductor memory device according to any one of claims 2-4, wherein the control circuit includes a clock generating circuit for designating a corresponding bank receives a signal designating the respective bank, the bank from the clock generator circuit A gist of the present invention is to include a control circuit that activates a row decoder of a designated bank based on a designated signal and deactivates the row decoder based on an output signal of the row decoder. According to a sixth aspect of the present invention, in the semiconductor memory device according to any one of the second to fifth aspects, the row decoder includes a latch circuit unit that latches a row address signal output from the row address buffer. That is the summary.

[0015]

According to the present invention, the control circuit section 4 activates the row decoders 2 and 3 of the corresponding bank based on the row address signal designating each bank. Therefore, the row address signal from the row address buffer 1 is input to both the row decoders 2 and 3, but only the row decoder activated by the control circuit 6 can receive the row address signal. As a result, even if there is only one row address buffer 1, the row decoders 2 and 3 provided for each bank can surely respond.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment embodying the present invention will now be described with reference to FIGS.
It will be described with reference to FIG. For convenience of description, the two banks are each a memory cell array of 16 bits × 1 bit, and the same configurations as those in FIG. 8 are denoted by the same reference numerals and the description thereof is partially omitted.

FIG. 2 shows a one-chip D with two banks.
This is a RAM block circuit. One row address buffer 11 receives 3-bit row address signals A0, A1, when an active command corresponding to the fall of the row address strobe signal (bar RAS signal) of the conventional general-purpose DRAM is input from an external device. Lower 2 of A2
Bit row address signals A0 and A1 are input and held. One column address buffer 12 receives a conventional general-purpose D from an external device after an active command is input.
When a read / write command corresponding to the fall of the RAM column address strobe signal (bar CAS signal) is input, a 3-bit column address signal A3,
2-bit column address signal A3 of A4 and A5,
Enter and hold A4.

The first clock generation circuit 13 outputs a 3-bit row address signal A0 based on the active command.
, A1 and A2, the row address signal A2 of the most significant bit is input and held. The clock generating circuit 13 outputs the first clock .phi.0 at the H level when the address signal A2 is at the H level. Then, the first clock generation circuit 13
When the precharge command corresponding to the rising edge of the bar RAS signal of the conventional general-purpose DRAM is input, the first clock φ0 is changed from H level to L level. Further, the clock generating circuit 13 outputs the first clock .phi.0 at the L level when the address signal A2 is at the L level.

The second clock generation circuit 14 inputs and holds the highest address signal A2 based on the active command. The clock generation circuit 14 outputs the second clock .phi.1 at the L level when the address signal A2 is at the H level. Further, the clock generating circuit 14 outputs the second clock .phi.1 of H level when the address signal A2 is of L level. When the precharge command is input, the second clock generation circuit 14 changes the second clock .phi.1 from H level to L level.

The control circuit 15 controls the first and second clocks φ.
Enter 0 and φ1. The control circuit 15 outputs the H-level capture signal φ2 to the row address buffer 11 in response to one of the first and second clocks φ0 and φ1 at the H-level clock. The row address buffer 11 receives the H level capture signal φ.
In response to 2, the row address signals A0 and A1 previously held based on the active command and the inverted row address signals A0 and A1 whose signal levels are inverted are output.

The control circuit 15 controls the first and second clocks φ.
H level first decoder selection signal φ based on 0, φ1
It outputs either 3 or the second decoder selection signal φ4 at the H level. When the first clock φ0 is at the H level (the second clock φ1 is at the L level), the control circuit 15 outputs the first decoder selection signal φ3 at the H level to the first row decoder 16. The second clock φ1 is at H level (first clock φ0
Is at the L level), the control circuit 15 outputs the second decoder selection signal φ4 at the H level to the second row decoder 17.

The first row decoder 16 is connected to the row address buffer 11 and is activated in response to the H level first decoder selection signal φ 3 to activate the row address buffer 1.
The row address signal A0, A0, A1 and A1 from 1 is input. Then, the first row decoder 16 applies an H level word selection signal .phi.50 to one of the four word lines WL10 to WL13 of the first bank 71 on the basis of the row address signals A0, A0, A1 and A1. Output φ53.

The second row decoder 17 is connected to the row address buffer 11 and is activated in response to the H level second decoder selection signal φ4.
The row address signal A0, A0, A1 and A1 from 1 is input. Then, the second row decoder 17 outputs the H level word selection signal .phi.60 to one of the four word lines WL20 to WL23 of the second bank 81 based on the row address signals A0, A0, A1 and A1. Output φ63.

Therefore, when the H-level first decoder selection signal φ 3 is output, the first row decoder 16 is activated to select the first bank 71, and the H-level second decoder 16 is selected.
When the decoder selection signal φ4 is output, the second row decoder 17 is activated and the second bank 81 is selected. That is, when the highest address signal A2 is at H level, the first bank 71 is selected, and when the highest address signal A2 is at L level, the second bank 81 is selected.

The control circuit 15 responds to one of the H-level word selection signals .phi.50 to .phi.53 output from the first row decoder 16 at the H-level and outputs the first decoder selection signal .phi.3 from the H-level to the L-level. Reset to level. Then, it waits for a new first clock φ0 of H level. or,
The control circuit 15 resets the second decoder selection signal φ4 from the H level to the L level in response to one of the H level word selection signals φ60 to φ63 output from the second row decoder 17. To do. Then, it waits for a new second clock φ1 at the H level.

FIG. 3 shows an electric circuit of the control circuit 15.
The control circuit 15 controls the first and second decoder selection signals φ3,
It is composed of a selection signal generation circuit section 15a for generating φ4 and a capture signal generation circuit section 15b for generating a capture signal φ2.

First, the selection signal generation circuit section 15a will be described. An RS flip-flop (hereinafter, simply referred to as FF) 23 including two NAND circuits 21 and 22 has a set input terminal connected to the first clock generation circuit 13 and a reset input terminal connected to the NOR circuit 24. NOR circuit 24 is a NOR circuit having four inputs, and inputs the word selection signal φ50~φ53 of the first row de <br/> coder 16. F
The set output terminal of F23 is connected to the NAND circuit 25. The NAND circuit 25 is a 2-input NAND circuit,
The other input terminal is connected to the first clock generation circuit 13. The output terminal of the NAND circuit 25 is connected to the inverter 26, and the output signal output from the output terminal of the NAND circuit 25 is output to the first row decoder 16 via the inverter 26 as the first decoder selection signal φ3.

The set output terminal of the FF 23 is connected to the inverter 27, and the output signal output from the set output terminal of the FF 23 is output to the fetch signal generation circuit section 15b as the first reset signal φ7 via the inverter 27. It

Therefore, when the set output terminal of the FF 23 is in the set state of H level, the word selection signals φ50 to φ53.
When all the signals are at the L level and the first clock φ0 at the H level is input, the set output terminal of the FF 23 remains at the H level. On the other hand, the output of the NAND circuit 25 changes from H level to L level. As a result, the first decoder selection signal φ3 changes from the L level to the H level. That is, when the first clock φ 13 of H level is output from the first clock generation circuit 13, the first decoder selection signal φ 3 of H level is output to the first row decoder 16. Further, in this state, the first reset signal φ7 remains L level.

Eventually, when the first row decoder 16 is activated and any one of the word selection signals φ50 to φ53 becomes H level, an L level signal is input to the reset input terminal of the FF23. The FF 23 inverts in response to this L level, and the output signal of the set output terminal becomes L level. Therefore, the first decoder selection signal φ3 changes from H level to L level. That is, word selection signals φ50 to φ53
When any one of them becomes the H level, the L level first decoder selection signal φ 3 is output to the first row decoder 16. Further, the first reset signal φ7 changes from the L level to the H level.

The circuit for generating the second decoder selection signal φ4 based on the second clock φ1 has the same circuit configuration as that described above. The detailed description thereof will be omitted.

Therefore, from the second clock generation circuit 14 to H
When the second clock φ1 of the level is output, the second decoder selection signal φ4 of the H level is output to the second row decoder 17. Further, in this state, the second reset signal .phi.8 remains L level. Further, when any one of the word selection signals φ60 to φ63 becomes H level, the L level second decoder selection signal φ4 becomes the second row decoder 17.
Is output to. Further, the second reset signal .phi.8 changes from L level to H level.

Next, the fetch signal generation circuit section 15b will be described. The first clock φ 0 is input to the input terminal of the CMOS inverter 32 via the inverter 31. The CMOS inverter 32 is a P-channel MOS transistor (hereinafter, simply referred to as a PMOS transistor) Q
1 and N-channel MOS transistor (hereinafter, simply NMO
It is called S transistor) Q2. The source of the PMOS transistor Q1 is connected to the high potential power supply VCC through the PMOS transistor Q3, and the NMOS transistor Q1
The source of 2 is connected to the low potential power supply VSS via the NMOS transistor Q4. The output terminal of the CMOS inverter 32 is connected to the row address buffer 11, and the fetch signal φ2 is output from the output terminal thereof.

The output terminal of the CMOS inverter 32 is 2
It is connected to the high-potential power supply VCC through the individual PMOS transistors Q5 and Q6. The second clock φ1 is input to the gate of the PMOS transistor Q5 and the gate of the NMOS transistor Q4 via the inverter 33.

An NMOS transistor Q7 is connected in parallel with the NMOS transistor Q2. The gate of the NMOS transistor Q7 and the PMOS transistor Q
The first reset signal .phi.7 is input to the gate of 3.

An NMOS transistor Q8 is connected in parallel with the NMOS transistor Q4. The gate of the NMOS transistor Q8 and the PMOS transistor Q
The second reset signal .phi.8 is input to the gate of 6.

The first and second reset signals φ7,
First clock φ0 at H level with φ8 at L level
Is output (φ1 is at L level), the MOS transistors Q1 and Q3 are turned on and the MOS transistors Q2 and Q7 are turned on.
Is turned off, the output terminal of the CMOS inverter 32 outputs an H level capture signal φ2.

In addition, the first and second reset signals φ7 and φ8
When the second clock φ1 at the H level is output while φ is at the L level (φ0 is at the L level), the MOS transistor Q
The output terminal of the CMOS inverter 32 is at H level because the Q5 and Q6 are turned on and the MOS transistors Q4 and Q8 are turned off.
Output level capture signal φ2.

Therefore, the first or second clocks φ0, φ1
Either of when it comes to H level, capture signal φ2 of H level will be output to the row address buffer 11. Then, when the H-level first reset signal φ7 is output while the fetch signal φ2 is being output at the H level of the first clock φ0, the PMOS transistor Q3 is turned off and the NMOS transistor Q7 is turned on. Therefore, the fetch signal φ2 becomes L level. or,
While the capture signal φ2 is being output at the H level of the second clock φ1, the second reset signal φ8 of the H level is output.
Is output, the PMOS transistor Q6 turns off,
Since the NMOS transistor Q8 is turned on, the fetch signal φ2 becomes L level.

FIG. 4 shows an electric circuit of the first row decoder 16. The first row decoder 16 is composed of four decoding circuit sections 16a to 16d having the same structure. First
The decode circuit section 16a receives the row address signals A0 and A1 of the row address buffer 11 and receives the address signal A
A word selection signal .phi.50 is output to the word line WL10 of the first bank 71 based on 0 and A1. Second
The decode circuit section 16b receives the row address signals A0 and A1 of the row address buffer 11 and outputs the word selection signal .phi.51 to the word line WL11 of the first bank 71 based on the address signals A0 and A1. ing. The third decoding circuit section 16c inputs the row address signal bars A0 and A1 of the row address buffer 11 and outputs the word selection signal φ52 to the word line WL12 of the first bank 71 based on the address signal bars A0 and A1. It has become. The fourth decoding circuit section 16d is provided with row address signal bars A0 and A1 of the row address buffer 11.
Is input to the word line WL13 of the first bank 71 based on the address signals A0 and A1.
Is output.

The decode circuit sections 16a to 16d are
Since the circuit configuration is the same except that the word line connected to the input address signal is different, the first decode circuit section 16a will be described for convenience of description, and the other decode circuit sections 16b to 16d will be given the same reference numerals. The description is omitted.

The first decoding circuit section 16a comprises an AND circuit section, a latch circuit section and an output circuit section. The AND circuit section includes PMOS transistors Q11 and 3
It is composed of individual NMOS transistors Q12 to Q14. The source of the PMOS transistor Q11 is connected to the high potential power supply VCC, and the drain of the PMOS transistor Q11 is connected to the low potential power supply VSS via the NMOS transistors Q12 to Q14. The first clock .phi.0 is input to the gate of the PMOS transistor Q11. The gate of the NMOS transistor Q12 has
The row address signal A0 is input, and the row address signal A1 is input to the gate of the NMOS transistor Q13. The NMOS transistor Q14 is a control transistor, and the gate thereof receives the first decoder selection signal .phi.3. The first clock φ0 input to the gate of the PMOS transistor Q11 is PM when the H-level first decoder selection signal φ3 is output.
It is designed to be inputted in advance by being controlled by a timing adjusting circuit such as a delay circuit so as to be inputted to the OS transistor Q11.

Therefore, the first decoder selection signal φ3 and the first decoder selection signal φ3
With the clock φ0 at the L level, the control NMOS transistor Q14 turns off and the PMOS transistor Q11
Turns on. As a result, the PMOS transistor Q11
The level of the output terminal extending from the node connecting the drain of the MOS transistor and the drain of the NMOS transistor Q12 is H level.

In this state, when the H-level first decoder selection signal .phi.3 and the first clock .phi.0 are input and the row address signals A0 and A1 are both at the H level, all three NMOS transistors Q12 to Q14 are turned on. . On the other hand, the PMOS transistor Q11 is turned off.
As a result, the level of the output terminal changes from H level to L level. At this time, if at least one of the row address signals A0 and A1 is at L level, one of the MOS transistors Q12 and Q13 is turned off, and the level of the output terminal remains at H level.

The signal from the output terminal of the AND circuit section is output to the latch circuit section. The latch circuit section includes a PMOS transistor Q15 and two NMOS transistors Q1.
6, Q 17 and an inverter 31. The source of the PMOS transistor Q15 is connected to the high potential power supply VCC, and the drain of the PMOS transistor Q15 is NMOS.
It is connected to the low potential power supply VSS through the transistors Q16 and Q17. The first clock .phi.0 is input to the gate of the NMOS transistor Q16. NMOS
The inverter 3 is connected to the node connecting the drain of the transistor Q16 and the drain of the PMOS transistor Q15.
1 input terminal is connected. The output terminal of the inverter 31 is connected to the gates of the PMOS transistor Q15 and the NMOS transistor Q17.

Therefore, when the first clock φ0 is at L level, the H level signal output from the output terminal of the AND circuit section is inverted by the inverter 31, the PMOS transistor Q15 is turned on, and the NMOS transistor Q17 is turned off. (At this time, the NMOS transistor Q16 is also turned off). As a result, the output of the inverter 31 holds the L level. Further, when the first clock φ0 is at H level and the output terminal of the AND circuit section outputs a signal at H level, the NMOS transistor Q16 is turned on, but similarly, the output of the inverter 31 is maintained at L level. To do.

Further, when the first clock φ0 is at H level and the output terminal of the AND circuit section outputs a signal at L level, it is inverted by the inverter 31, the PMOS transistor Q15 is turned off, and the NMOS transistor Q17.
Is on (at this time, NMOS transistor Q16 is also on)
To do. As a result, the output of the inverter 31 holds the H level.

The output of the inverter 31 is output to the output circuit section. The output circuit section is composed of two inverters 32 and 33. The output of the inverter 31 is output to the word line WL10 via the inverters 32 and 33 as the word selection signal φ50. Also, word selection signal φ50
Is output to the NOR circuit 24 of the selection signal generation circuit section 15a. Therefore, when the first clock φ0 is at the L level, or when the first clock φ0 is at the H level and at least one of the row address signals A0 and A1 is at the L level, the first decoding circuit section 16a is at the L level. The word selection signal φ50 is output. When the first clock .phi.0 is at H level and the row address signals A0 and A1 are both at H level, the first decoding circuit section 16a outputs the H level word selection signal .phi.50.

FIG. 5 shows an electric circuit of the second row decoder 17. The second row decoder 17 is composed of four decode circuit sections 17a to 17d having the same configuration. First
The decode circuit section 17a receives the row address signals A0 and A1 of the row address buffer 11 and inputs the address signal A0.
, A1 to output the word selection signal φ60 to the word line WL20 of the second bank 81. Second
The decode circuit section 17b inputs the row address signals A0 and A1 of the row address buffer 11 and outputs the word selection signal .phi.61 to the word line WL21 of the second bank 81 based on the address signals A0 and A1. ing. The third decoding circuit section 17c inputs the row address signal bars A0 and A1 of the row address buffer 11 and outputs the word selection signal φ62 to the word line WL22 of the second bank 81 based on the address signal bars A0 and A1. It has become. The fourth decoding circuit section 17d is provided with row address signal bars A0 and A1 of the row address buffer 11.
Is input to the word line WL23 of the second bank 81 based on the address signals A0 and A1.
Is output.

The decode circuit sections 17a to 17d are
The second clock φ1 and the second decoder selection signal φ4 are input instead of the first clock φ0 and the first decoder selection signal φ3, and each output terminal is connected to the word line WL10 of the second bank 81.
~ WL13, word lines WL20 to W of the second bank 81
The circuit configuration is the same as that of each of the decoding circuit units 16a to 16d of the first row decoder 16 except that it is connected to L23. Therefore, the reference numerals of the corresponding circuits are added to the reference numerals of the corresponding circuits and the detailed description thereof is omitted.

In FIG. 2, the column buffer 12 includes column decoders 74 and 8 of the first and second banks 71 and 81.
4 is connected. The column buffer 12 receives the column address signals A3 and A4 and receives the column address signal A
3, A4 and inverted column address signal bars A3, A4 in which the levels of the address signals A3, A4 thereof are inverted are output to both column decoders 74, 84.

Both column decoders 74 and 84 open predetermined bit lines based on the column address signals A3, A3, A4 and A4, and amplify the data read from the selected bit lines by the sense amplifiers 76 and 86. And outputs it to the input / output buffer 92. The input / output buffer 92 inputs the column address signal A5 of the most significant bit of the 3-bit column address signals A3 to A5. The column address signal A5 has the same content as the content of the row address signal A2 of the most significant bit input by the previous active command. That is, when the row address signal A2 is at H level, the column address signal A5 is at H level. When the row address signal A2 is at L level, the column address signal A5 is at L level.
It is a level.

When inputting / outputting the column address signal A5 of H level, the input / output buffer 92 inputs and outputs only the data output from the sense amplifier 76 of the first bank 71. Conversely, when the L-level column address signal A5 is input, the sense amplifier 86 of the second bank 81
Input and output only the data output from. And
In this case, since the input / output buffer 92 inputs the column address signal A5 of H level, it inputs the data output from the sense amplifier 76 of the first bank 71 and outputs it to the external device. In the write mode, the input / output buffer 92 receives write data from an external device and transfers the write data to the bank selected by the column address signal A5.

Next, the operation of the DRAM configured as described above will be described. For convenience of description, first the first bank 7
A case where 1 is selected and then the second bank 81 is selected to sequentially read data will be described.

When an active command is input, the row address buffer 11 causes the row address signals A0 and A1.
, And the first and second clock generation circuits 13 and 14 receive the row address signal A2. At this time, since the first bank 71 is selected, the row address signal A2 is at H level. Therefore, the first clock generation circuit 13 outputs the first clock φ0 of H level to the control circuit 15. In the control circuit 15, the fetch signal generation circuit section 15b outputs the fetch signal φ2 of H level to the row address buffer 11 in response to the first clock φ0 of H level.
On the other hand, the selection signal generation circuit section 15a responds to the first clock φ0 at the H level in response to the first decoder selection signal φ at the H level.
Outputs 3. At this time, since the second clock .phi.1 is at the L level, the selection signal generation circuit section 15a does not output the H level second decoder selection signal .phi.4.

In response to the H-level fetch signal φ2, the row address buffer 11 complements the held row address signals A0 and A1 with the complementary row address signal A0 and bar A.
0, A1, and bar A1 for the first and second row decoders 1
Output to 6 and 17. At this time, only the first decoder selection signal φ3 at the H level is being output, so only the first row decoder 16 is activated and the second row decoder 17 is not activated.

The activated first row decoder 16 receives the row address signal A in each of the decoding circuit sections 16a to 16d.
0, bar A0, A1, bar A1 are decoded. For example, when the row address signals A0 and A1 are both at the H level, the first decode circuit section 16a outputs the H level word selection signal .phi.50 to select the word line WL10.

On the other hand, when the read / write command is input, the column address buffer 12 inputs the column address signals A3 and A4. Then, the column address buffer 12 co complementary column address signals A3, A4
Ram address signals A3, bar A3, A4, column decoder 7 of the first and second banks 71 and 81 in the bar A4
Output to 4,84. Column decoder 74, 84 Korah
Beam address signals A3, bar A3, A4, to select a predetermined bit line of the first and second banks 71 and 81 respectively on the basis of the bar A4. At this time, since the word line WL10 is selected in the first bank 71, the data of the memory cell determined by the word line WL10 and the bit line selected by the column decoder 74 is amplified by the sense amplifier 76 and is input / output buffered. It is output to 92. Further, in the second bank 81, since all the word lines WL20 to WL23 are not selected,
Data is not read even if the bit line is selected by the column decoder 84.

In addition, the input / output buffer 92 inputs the column address signal A5 in response to the read / write command. At this time, since the first bank 71 is selected, the column address signal A5 is at H level. Therefore, the input / output buffer 92 inputs only the data output from the sense amplifier 76 of the first bank 71 and outputs it to the external device.

The H-level word selection signal φ50 for selecting the word line WL50 output from the first row decoder circuit 16 is selected by the selection signal generation circuit section 1 of the control circuit 15.
It outputs to the NOR circuit 24 of 5a. Therefore, the FF 23 performs the inversion operation, and the selection signal generation circuit unit 15a outputs the H-level first reset signal φ7 to the fetch signal generation circuit unit 15b. In response to the H-level first reset signal .phi.7, the fetch signal generation circuit section 15b changes the fetch signal .phi.2 to the L level. As a result, the row address buffer 11
Prepares for the input of the next new row address signals A0 and A1 (for the second bank 81).
Stop the output of 0, bar A0, A1, bar A1.

Further, the selection signal generation circuit section 15a sets the first decoder selection signal φ3 to the L level. Therefore, the first row decoder 17 becomes inactive. At this time, since the first row decoder 17 holds the data of the word line selected by the latch circuit section, when the first clock .phi.0 becomes L level, the word selection signals .phi.50 to .phi.53 become L level. In this embodiment, when the precharge command is input, the first clock .phi.0 goes to L level and the word selection signals .phi.50 to .phi.53 go to L level. Next, when a new active command is input, the row address buffer 11 causes the row address signals A0, A for the second bank 81 to be input.
Input 1 from an external device. Similarly, the first and second
The clock generation circuits 13 and 14 receive the row address signal A2. At this time, since the second bank 81 is selected,
The row address signal A2 is at L level. Therefore, the second
The clock generation circuit 14 outputs the second clock φ1 at H level to the control circuit 15. In the control circuit 15, the fetch signal generation circuit section 15b outputs the H level fetch signal φ2 to the row address buffer 11 in response to the H level second clock φ1. On the other hand, the selection signal generation circuit section 15a outputs the H level second decoder selection signal .phi.4 in response to the H level second clock .phi.1. At this time,
Since the first clock .phi.0 is at L level, the selection signal generation circuit section 15a does not output the first decoder selection signal .phi.3 at H level.

The second row decoder 17 is activated based on the H-level second decoder selection signal φ4. And
The second row decoder 17 is similar to the first row decoder 16 in that it has row address signals A0, A0, A1 and A0.
Decode 1 to select one of word lines WL20 to WL23
One of the word selection signals φ60 to φ63 is output. Then, based on the input of the read / write command, the second
The column address signals A3 and A4 for the bank 81 are copied.
Muba Ffa 12 inputs from an external device. Then, similar to the above, a predetermined bit line is selected through the column decoders 74 and 84.

Further, the column address signal A5 for the second bank 81 is input based on the input of the read / write command.
To the input / output buffer 92 from an external device. Then, the input / output buffer 92 outputs the data read from the second bank 81 to the external device.

As described above, in this embodiment, since the memory cell array is divided into the first and second banks 71 and 81, when reading data continuously, when reading data from the first bank 71, Row address signals A0 and A1 for reading the data of the memory cells of the two banks 81 can be output to the row address buffer 11. Therefore, the data can be read at a high speed as much as the next row address signal can be input. Since the control circuit 15 operates in the same manner when writing data, the writing speed can be correspondingly increased.

Moreover, in this embodiment, one row address buffer 11 is provided for the first and second banks 71 and 81, and the row address buffer 11 can be shared by the first and second banks 71 and 81. I did it. That is, the control circuit 15 causes the first row decoder 16 of the first bank 71 to operate.
Alternatively, one of the second row decoders 17 of the second bank 81 is activated and the activated row decoder is made to hold the row address signal output from the row address buffer 11. Therefore, the chip area occupied by the row address buffer can be reduced by one row address buffer. In this embodiment, 16-bit × 1-bit banks 71, 81
Although the row address signal is 3 bits, the chip area occupied by the row address buffer can be reduced as the memory capacity of one bank increases and the number of bits of the row address signal increases.

Further, in the present embodiment, the first row decoder 16
Since the second row decoder 17 is provided with the latch circuit section, the row address buffer 11 can reliably take in the next row address signal, and high speed reading and high speed writing of data can be realized.

The present invention is not limited to the above embodiment, but may be carried out in the following modes. (1) As shown in FIG. 7, the number of bits of the row address signal is large, a predecoder 51 is provided at the output stage of the address buffer 11, and the predecoder 51 is connected to the first row decoder (main decoder) 16 of the bank 71. Bank 81
The second row decoder (main decoder) 17 may be embodied in a DRAM in which a row address signal is output. In this case, the control circuit 15 activates either the first row decoder (main decoder) 16 or the second row decoder (main decoder) 17. Therefore, in this case, the predecoder 51 can be shared, and the chip area can be further reduced.

(2) In the above embodiment, two banks 71,
Although it is embodied in the DRAM having 81, it may be divided into a larger number. In this case, the larger the number of divided banks, the smaller the chip area occupied by the row address buffer.

(3) A plurality of, for example, four banks are grouped into two banks each. A row address buffer is provided for each of the two groups. Then, the control circuit 15 may activate four banks. That is, two row address buffers are provided for four banks. In this case as well, the chip area occupied by the row address buffer becomes smaller than in the conventional case. Of course, in this case as well, the control circuit 15 may be provided corresponding to the number of two row address buffers instead of one.

(4) The above embodiment is embodied as a DRAM, but if it is divided into a plurality of banks, an SRAM,
A semiconductor storage device such as a ROM may be used.

[0071]

As described in detail above, according to the present invention, in a semiconductor memory device in which a memory cell array is divided into a plurality of banks, the number of address buffers can be reduced and the chip area occupied by the address buffers can be reduced. It has the effect that can be achieved.

[Brief description of drawings]

FIG. 1 is an explanatory view of the principle of the present invention.

FIG. 2 is a block circuit diagram illustrating a basic configuration of a DRAM according to an embodiment.

FIG. 3 is an electric circuit diagram for explaining details of the control circuit of FIG.

FIG. 4 is an electric circuit diagram of the first row decoder of FIG.

5 is an electric circuit diagram of a second row decoder of FIG.

FIG. 6 is a waveform diagram of each signal

FIG. 7 is a block circuit diagram of a main part of another example of DRAM.

FIG. 8 is a block circuit diagram illustrating a basic configuration of a conventional DRAM.

[Explanation of symbols]

1 Row address buffer 2 row decoder 3 Row decoder 4 Control circuit section 5 clock generation circuit 6 control circuit

─────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-57-100688 (JP, A) JP-A-7-45075 (JP, A) JP-A-60-157798 (JP, A) JP-A-6- 275071 (JP, A) JP 60-115094 (JP, A) JP 56-137585 (JP, A) JP 8-77767 (JP, A) JP 6-302186 (JP, A) International publication 92/09084 (WO, A1) (58) Fields investigated (Int.Cl. ⁷ , DB name) G06F 12/00-12/06 G06F 13/16-13/18 G11C11 / 401,11 / 407, 11/41

Claims (6)

(57) [Claims] 1. A row address signal is a row address.
First input to buffer, specifying first memory bank
Corresponding to the first memory bank based on the signal of
The row decoder of the first row decoder
Deactivates the first row decoder based on the output signal of
And after the first row decoder is deactivated,
Based on a second signal designating a second memory bank,
Activate the second row decoder corresponding to the second memory bank.
Bank selection for semiconductor memory devices characterized by characterization
How to choose. 2. A memory cell array is divided into a plurality of banks.
Integrated semiconductor memory device, one row address buffer provided for a plurality of banks is provided.
And a bank for each bank.
C. The row decoder connected to the address buffer and the bank specified based on the signal specifying each bank
The row decoder is activated and the row decoder is activated.
Deactivates the row decoder based on the output signal of
A semiconductor memory device including a control circuit unit. 3. A row address buffer, a first memory bank, and a first row decoder corresponding to the first memory bank.
If a second row decoder corresponding to the second memory bank, the second memory bank
And the first row decoding based on a signal designating a bank.
Or a control circuit for activating the second row decoder
Of the first row decoder or the second row decoder
Based on the output signal, the first row decoder or the first row decoder
A contract characterized by deactivating the second row decoder
The semiconductor memory device according to claim 2. 4. A memory cell array is divided into a plurality of banks.
Integrated semiconductor memory device, a plurality of banks are grouped and provided for each group.
One and Rouado less buffer that is, a row decoder provided in each bank, on the basis of a signal designating the respective bank, the specified bank
Row decoder is activated and the row decoder
The row decoder is deactivated based on the output signal of
And a semiconductor memory device having a control circuit section. 5. The control circuit section inputs a signal designating each bank and designates a corresponding bank.
Based on the clock generator circuit and the signal specifying the bank from the clock generator circuit.
Then, activate the row decoder of the specified bank.
The row decoder based on the output signal of the row decoder.
A control circuit for deactivating the decoder.
5. The semiconductor memory device according to any one of 2 to 4. 6. The row decoder is configured to output the row address.
Latches the row address signal output from the buffer
The latch circuit section according to claim 2, further comprising a latch circuit section.
Semiconductor memory device.