KR100534206B1 - A redundancy decoder of a semiconductor memory device - Google Patents

Abstract

The present invention discloses a redundancy decoder of a semiconductor memory device. The present invention includes a first control signal generator for generating a first control signal that is enabled when the enable fuse is cut; When a plurality of fuses selectively cut according to an address of the bad memory cell are cut, a first level signal is output in response to a corresponding address of the bad memory cell, and in response to an address other than the corresponding address of the bad memory cell. A plurality of address inputs for outputting a second level signal; A second control signal generator which is enabled only when a first level signal is output from all of the plurality of address inputs to generate a second control signal for accessing the defective memory cell and the redundancy line replaced; An option pad for outputting a third control signal whose level varies according to the increase or decrease of the number of data input / outputs; When the number of data input / outputs is decreased, in response to the third control signal, the second control signal generator blocks the predetermined address input unit and the second control signal generator, and affects the enable of the second control signal. It provides a predetermined level signal that does not reach, and the switching unit for connecting between the address input unit and the second control signal generator when the number of data input and output is increased, thereby improving the operation reliability of the semiconductor memory device that can change the number of data input and output Improve.

Description

A redundancy decoder of a semiconductor memory device

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a redundancy decoder of a semiconductor memory device that generates a control signal (decoding signal) that is involved in accessing a predetermined redundancy line in a semiconductor memory device in which the number of data input / outputs can be changed. will be.

In general, a semiconductor memory device includes a memory cell array in which memory cells, which are basic elements for storing or reading data, are arranged in a matrix form, and a horizontal direction of the memory cell array is " low " "Column". In addition, there is a limitation in configuring a memory cell array in one matrix form due to the increase in memory capacity. Thus, the memory cell array is divided into a plurality of matrix forms, which are referred to as "blocks".

When a bad memory cell is detected in a predetermined block of the semiconductor memory device, a method for repairing the bad memory cell includes replacing a low line including the bad memory cell with a redundancy low line or including a bad memory cell. It is common to replace redundant column lines with redundant column lines.

Among them, in the method of replacing a column line including a bad memory cell with a predetermined redundancy column line (hereinafter referred to as a column repair), a column line including a bad memory cell is replaced with a predetermined redundancy column line existing in the same block. There is an alternative.

However, the column repair in the same block has a disadvantage in that the chip size of the semiconductor memory is increased by increasing the number of redundancy column lines existing in the same block in proportion to the number of column lines including the defective memory cells.

In order to solve the above disadvantages, a method of replacing a column line including a bad memory cell with a redundancy column line existing in another block when a plurality of columnar errors occur in one block is conventionally used. Mainly used.

On the other hand, the semiconductor memory device is preferably designed to operate in a variety of modes to improve the efficiency of the product, the semiconductor memory device designed to allow the user to change the number of data input and output to meet the purpose. For example, in the case of a semiconductor memory device having a 1M capacity, the data input / output method could be interchanged between the x16 mode and the x8 mode. Here, 16 address pins are used when the number of data inputs and outputs is x16, but 17 address pins are used when x8, so in the x16 mode, one of the address pins is floated without an external input. As a result, while the semiconductor memory device operates in the x16 mode, the output signal of the address buffer corresponding to the unused address pin is fixed to the "high" level or the "low" level by the combination of internal logic.

However, as described above, when a predetermined address pin is in a floating state according to the change of the number of data input / output, and the output signal of the predetermined address buffer is fixed at the "high" level or the "low" level, the corresponding redundancy line in response to the output signals of the address buffers A redundancy decoder that generates a control signal (decoding signal) that is involved in accessing a device may malfunction in some cases, resulting in a poor operation reliability of the semiconductor memory device.

The present invention has been made to solve the above problems, and is fixed to a "high" level or a "low" level in response to a predetermined control signal input through an option pad when the number of data input / output is changed. It is an object of the present invention to provide a redundancy decoder of a semiconductor memory device that generates an accurate decoded signal that is not affected by an output signal of an address buffer.

In order to achieve the above object, a redundancy decoder of a semiconductor memory device according to an embodiment of the present invention includes an enable fuse selectively cut according to whether a defective memory cell is replaced, and a first control enabled when the enable fuse is cut. A first control signal generator for generating a signal; When the fuses are cut, including a plurality of fuses selectively cut according to the address of the bad memory cell when the enable fuse is cut, the first level signal is output in response to a corresponding address of the bad memory cell, A plurality of address input parts for outputting a second level signal in response to an address other than the corresponding address of the defective memory cell; A second control signal generator which is enabled only when a first level signal is output from all of the plurality of address inputs to generate a second control signal for accessing the defective memory cell and the redundancy line replaced; An option pad for outputting a third control signal whose level varies according to the increase or decrease of the number of data input / outputs; One of the plurality of address input units is connected between the second control signal generator to cut off the address input unit and the second control signal generator in response to the third control signal when the number of data input / output is reduced. At the same time, the second control signal generator is supplied with a predetermined level signal which does not affect the enable of the second control signal, and when the number of data input / outputs is increased, the address input unit and the second control signal generator are connected. It characterized in that it comprises a switching unit to.

Prior to the description of the present invention, a redundancy decoder of a conventional semiconductor memory device will be described.

1 and 2 are circuit diagrams of a column redundancy decoder according to an example of the prior art, in which a circuit diagram of a first control signal generator is illustrated in FIG. 1, and a circuit diagram of the remaining components is illustrated in FIG. 2.

As shown in FIGS. 1 and 2, the column redundancy decoder according to the prior art includes an enable fuse F11 that is selectively cut according to whether a defective memory cell is replaced. A first control signal generator 10 which generates first control signals A and Ab which are enabled when cut; The fuses F21 to F22 include two fuses F21, F22, F21 ′ and F22 ′ which are selectively cut according to the column address of the bad memory cell when the enable fuse F11 is cut. ') Is truncated, outputs a "high" level signal in response to a corresponding column address of the bad memory cell, and n outputs a "low" level signal in response to a column address other than the corresponding column address of the bad memory cell. Address input sections 20-1 to 20-n; A second that is enabled only when all of the "high" level signals are output from the plurality of address inputs 20-1 to 20-n so that the column line including the bad memory cell and the replaced redundancy column line are accessed; A second control signal generator 30 for generating a control signal (decoding signal RCOL) is provided.

The detailed circuit configuration of each of the components is as follows.

As shown in FIG. 1, the first control signal generator 10 includes an enable fuse F11 connected between a power supply and a node ⓐ, and five NMOS transistors connected in series between the node ⓐ and ground. An inverter (N11 to N15), a capacitor (C11) connected between the node (ⓐ) and ground, and an inverter inverting the potential of the node (ⓐ) corresponding to the first control signal (Ab) to generate a first control signal (A) ( I11) and an NMOS transistor N16 having a drain and a source connected to the node ⓐ and ground, respectively, and to which an output of the inverter I11 is applied as a gate.

In the first control signal generator 10 configured as described above, when the enable fuse F11 is not disconnected in the repair process, the potential of the node ⓐ becomes "high" and the inverter I11 and the NMOS transistor N16 are connected. ), The first control signal Ab is latched at the "high" level and the first control signal A is at the "low" level. On the contrary, when the enable fuse F11 is cut in the repair process, the potential of the node ⓐ is “low” by the five NMOS transistors N11 to N15 and the capacitor C11, and the first control signal Ab is At the " low " level, the first control signal A is enabled at the " high " level, respectively, and then the first control signals Ab, A are respectively turned off by the inverter I11 and the NMOS transistor N16. Latched to the "level" and "high" levels.

Each of the n address input units 20-1 to 20-n has the same detailed circuit configuration. More specifically, one address input unit (for example, 20-1) is a PMOS transistor in which one of the n column addresses RA1b to RAnb is applied to the drain, and the first control signal Ab is applied to the gate. (P21), an NMOS transistor (N21) having a source and a drain connected to a drain and a source of the PMOS transistor (P21), and a first control signal (A) applied to a gate, and a drain of the PMOS transistor (P21). A first fuse F21 connected between the source connection point of the NMOS transistor N21 and the second control signal generator 30 and selectively cut in a repair process according to the level of the column address RA1b; An inverter R21 for inverting the column address RA1b and a connection between the inverter R21 and the second control signal generator 30 are selectively cut in the repair process according to the level of the corresponding column address RA1b. Second fuse (F22) Consists of Here, the n column addresses RA1b to RAnb correspond to output signals of the address buffers (not shown).

The two fuses F21 and F22 included in the one address input unit 20-1 configured as described above are cut off only the first fuse F21 when the column address RA1b is at the "low" level. When the column address RA1b is at the "high" level, only the second fuse F22 is blown. As described above, two fuses F21 to F22 ′ respectively provided to the n address input units 20-1 to 20-n are selectively cut in accordance with the level of the corresponding column address in the repair process, and then the semiconductor memory device If the n column addresses RA1b to RAnb corresponding to the column addresses of the bad memory cells are input to the n address input units 20-1 to 20-n during the read or write operation, the n address input units 20- All of the "high" level signals are output from 1 to 20-n, and are applied to the second control signal generator 30.

The second control signal generator 30 may include an NAND gate NAND31 for inverting and outputting the outputs of the n address input units 20-1 to 20-n, and an output of the NAND gate NAND31. The first inverter I31 for inverting the second inverter, the second inverter I32 for inverting the output of the first inverter I31, and the second control signal RCOL for inverting the output of the second inverter I32. It consists of the 3rd inverter I33 which outputs with the.

The second control signal generator 30 configured as described above has the output of the NAND gate NAND31 only at the "low" level only when the outputs of the n address input units 20-1 to 20-n are all at the "high" level. This generates a second control signal RCOL of "high" level. This "high" level second control signal RCOL enables access to the corresponding redundancy column line.

The operation of the redundancy decoder according to the example of the prior art configured as described above is as follows.

First, when a bad memory cell is detected in a test process of a semiconductor memory device, in the next repair process, fuses included in the column redundancy decoder are appropriately cut so that the column line including the bad memory cell is replaced with a predetermined redundancy column line.

Next, an example in which a column line including a bad memory cell is replaced with a predetermined redundancy column line existing in another block will be described. When the column line including the bad memory cell is replaced with a predetermined redundancy column line, the enable fuse F11 included in the first control signal generator 10 of FIG. 1 is cut in a repair process, and FIG. The fuses F21 to F22 'included in the n address input units 20-1 to 20-n of 2 are also cut appropriately according to the column address of the defective memory cell. In addition, due to the cutting of the enable fuse F11, the first control signal Ab is latched to the "low" level and the first control signal A to the "high" level.

In the above state, when n column addresses RA1b to RAnb corresponding to the column addresses of the bad memory cells are applied to the n address input units 20-1 to 20-n one by one, the n address input units 20-n are applied. All of the "high" level signals are output from 1 to 20-n and are applied to the NAND gate NAND31 of the second control signal generator 30. As a result, the output of the NAND gate NAND31 is at the "low" level, and the second control signal RCOL corresponding to the output of the inverter I33 is at the "high" level, so that the column line including the bad memory cell and Access to the replaced redundancy column lines becomes possible.

On the contrary, if a different column address is applied to the n address input units 20-1 to 20-n instead of the column address of the bad memory cell, at least one of the n address input units 20-1 to 20-n is " Low level signal is output and applied to the NAND gate NAND31 of the second control signal generator 30. As a result, the output of the NAND gate NAND31 becomes the "high" level, and the second control signal RCOL corresponding to the output of the inverter I33 becomes the "low" level, thereby preventing access to the corresponding redundancy column line. .

On the other hand, in order to increase the number of data input / output of the semiconductor memory device from x2 ^m-1 to x2 ^m , one of the address pins provided in the package of the semiconductor memory device is in a floating state in which no external input is applied. The output signal of the address buffer corresponding to the address pin is fixed to the "high" level or the "low" level by the combination of internal logic.

However, the output signal of the address buffer applied to one of the n address inputs of the column redundancy decoder in accordance with the increase in the number of data input / output in the state in which the column line including the bad memory cell is replaced with the predetermined redundancy column line as described above. Is fixed to the "high" level or the "low" level, the second control signal RCOL is not enabled to the "high" level because a "low" level signal may be output instead of a "high" level signal from the corresponding address input. There was a problem that the malfunction occurred.

Hereinafter, a redundancy decoder of a semiconductor memory device according to an exemplary embodiment of the present invention will be described.

3 is a partial circuit diagram of a column redundancy decoder according to an embodiment of the present invention, wherein the column redundancy decoder according to an embodiment of the present invention is a circuit configuration of a column redundancy decoder according to the prior art (first control signal generator + n). Option pads (not shown) and the switching unit 40 are added to the two address input units + the second control signal generator. Therefore, in the following, only the configuration of the option pad and the switching unit 40 will be described in detail. In addition, in FIG. 3, components that perform the same role as those of the prior art are denoted by the same reference numerals as the prior art illustrated in FIGS. 1 and 2.

The option pad outputs to the switching unit 40 a third control signal OP whose level varies according to the increase or decrease of the data input / output number of the semiconductor memory device. An option mask may be used instead of the option pad. However, in the case of the option mask, the option mask may not be quickly responded to the user's needs, such as the cost of manufacturing the mask and the operation of the product. Use a pad. The option pad is not illustrated but may be formed in two ways. In the first method, an option pad is connected between an extra pin provided in a package of a semiconductor memory device and a switching unit 40 to receive a third control signal OP received from the outside through the extra pin. 40). In the second method, an option pad is arranged to be bonded between a power pad and a ground pad of a semiconductor memory device, so that a third control of a logic “high” or “low” level is determined depending on whether the power pad or the ground pad is bonded. It is formed to transfer the signal OP to the switching unit 40.

When the number of data input / output of the semiconductor memory device is changed from × 2 ^m-1 to × 2 ^m , the option pad configured as described above outputs a third control signal OP having a “high” level, and the number of data input / output is × When changing from 2 ^m to x 2 ^{m -1} , the third control signal OP of the "low" level is output.

The switching unit 40 is connected between the first address input unit 20-1 and the second control signal generation unit 30 among the n address input units 20-1 to 20-n to provide data of the semiconductor memory device. When the number of input / output decreases from × 2 ^m to × 2 ^m-1 , the address input unit 20-1 and the second control signal generator 30 are blocked in response to the third control signal OP having the "low" level. At the same time, the second control signal generator 30 supplies a "high" level signal that does not affect the enable of the second control signal RCOL, and the number of data input / outputs is from x2 ^m-1 to x2 ^m. When increased to, the address input unit 20-1 and the second control signal generator 30 are connected in response to the third control signal OP having the “high” level.

More specifically, the switching unit 40 generates an inverter I41 for inverting the third control signal OP, two fuses F21 and F22 of the address input unit 20-1, and a second control signal. A PMOS transistor P41 having a source and a drain connected to the NAND gate NAND31 of the unit 30 and the third control signal OP applied to the gate, and a drain at a source and a drain of the PMOS transistor P41. And a source are connected to each other, and the output of the inverter I41 is applied to the gate of the NMOS transistor (N41), the drain between the PMOS and NMOS transistors (P41, N41) and the NAND gate (NAND31) the source is supplied to the power source. It is composed of a PMOS transistor P42 connected and the output of the inverter I41 is applied to the gate. Here, when the third control signal OP is applied at the "low" level, the PMOS transistor P41 and the NMOS transistor N41 are turned on, and the PMOS transistor P42 is turned off to output the address input unit 20-1. The PMOS transistor P41 and the NMOS transistor N41 are turned off when the signal is transferred to the NAND gate NAND31 of the second control signal generator 30 as it is, and when the third control signal OP is applied at the "high" level. The PMOS transistor P42 is turned on so that the output of the address input unit 20-1 is cut off, and the " high " level signal is instead applied to the NAND gate NAND31 of the second control signal generator 30 by the PMOS transistor P42. Is applied.

The operation of the column redundancy decoder according to the embodiment of the present invention configured as described above will be described in detail. In addition, the following description will take an example in which the option pad formed in the first manner is used.

First, when a bad memory cell is detected in a test process of a semiconductor memory device, in the next repair process, fuses included in the column redundancy decoder are appropriately cut so that the column line including the bad memory cell is replaced with a predetermined redundancy column line.

Next, an example in which a column line including a bad memory cell is replaced with a predetermined redundancy column line existing in another block will be described. When the column line including the bad memory cell is replaced with a predetermined redundancy column line, the enable fuse included in the first control signal generator is cut in the repair process, and the n address input units 20 of FIG. The fuses F21 to F22 'included in -1 to 20-n are also cut off appropriately according to the column address of the defective memory cell. Further, due to the disconnection of the enable fuse, the first control signal Ab is latched to the "low" level and the first control signal A to the "high" level.

A third control signal of the extra pin connected to the option pad in order in a state as described above to set the data input and output number of the semiconductor memory device as × 2 ^m-1 and × 2 ^m × 2 ^m-1 of the "low" level ( OP) is applied, and when n column addresses RA1b to RAnb corresponding to the column addresses of the bad memory cells are applied to the n address input units 20-1 to 20-n, the n address input units 20-n are applied. 1 to 20-n, all of the " high " level signals are output, and are connected between the address input unit 20-1 and the NAND gate NAND31 of the second control signal generator 30 by the switching unit 40. Therefore, the "high" level outputs of the n address input units 20-1 to 20-n are respectively transmitted to the NAND gate NAND31. As a result, the output of the NAND gate NAND31 is at the "low" level, and the second control signal RCOL corresponding to the output of the inverter I33 is at the "high" level, so that the column line including the bad memory cell and Access to the replaced redundancy column lines becomes possible.

However, when another column address is applied to the n address input units 20-1 to 20-n instead of the column address of the bad memory cell, at least among the n address input units 20-1 to 20-n as in the prior art. At least one "low" level signal is output and applied to the NAND gate NAND31 of the second control signal generator 30. As a result, the output of the NAND gate NAND31 becomes the "high" level, and the second control signal RCOL corresponding to the output of the inverter I33 becomes the "low" level, thereby preventing access to the corresponding redundancy column line. .

On the other hand, it is a "high" third control signal (OP) of a level in excess of the pin associated with the option pad for setting a data input and output number of the semiconductor memory device as × 2 ^m-1 and × 2 ^m × 2 ^m of and The address pin corresponding to the column address of the least significant bit among the address pins included in the package of the semiconductor memory device is in a floating state so that the column address RA1b applied to the address input unit 20-1 is "high" level or "low". N-1 corresponding to the column address of the bad memory cell in the remaining address input units except the first address input unit 20-1 among the n address input units 20-1 to 20-n. When the column address is applied, all of the other address input units except for the first address input unit 20-1 output a “high” level signal, and the switching unit 40 outputs the address input unit 20-1 and the second signal. Instead of being blocked between the NAND gates NAND31 of the control signal generator 30, a "high" level signal is always applied to the NAND gate NAND31 regardless of the input level of the column address RA1b. As a result, the output of the NAND gate NAND31 is at the "low" level, and the second control signal RCOL corresponding to the output of the inverter I33 is at the "high" level, so that the column line including the bad memory cell and Access to the replaced redundancy column lines becomes possible.

Incorrect output of the address input unit 20-1 when the column address RA1b input of the address input unit 20-1 is fixed to the "high" level or the "low" level due to the floating state of the predetermined address pin as described above. If a "high" level signal is applied to the NAND gate NAND31 through the PMOS transistor P42 of the switching unit 40 instead of the signal, a malfunction caused by the second incorrect control signal RCOL of the prior art is prevented. .

As described above, the redundancy decoder of the semiconductor memory device according to the present invention has redundancy even when a predetermined address pin is in a floating state according to a change in the number of data input / output and the output signal of the address buffer is fixed at a "high" level or a "low" level. Since the control signal (decoding signal) involved in accessing the column line can be accurately generated, the operation reliability of the semiconductor memory device in which the number of data input / output can be changed can be improved.

1 and 2 are circuit diagrams of a column redundancy decoder according to an example of the prior art;

3 is a partial circuit diagram of a column redundancy decoder according to an embodiment of the present invention.

Claims (3)

A first control signal generator configured to generate a first control signal enabled when the enable fuse is cut, including an enable fuse selectively cut according to whether to replace the defective memory cell; When the fuses are cut, including a plurality of fuses selectively cut according to the address of the bad memory cell when the enable fuse is cut, the first level signal is output in response to a corresponding address of the bad memory cell, A plurality of address input parts for outputting a second level signal in response to an address other than the corresponding address of the defective memory cell; A second control signal generator which is enabled only when a first level signal is output from all of the plurality of address inputs to generate a second control signal for accessing the defective memory cell and the redundancy line replaced; An option pad for outputting a third control signal whose level varies according to the increase or decrease of the number of data input / outputs; One of the plurality of address input units is connected between the second control signal generator to cut off the address input unit and the second control signal generator in response to the third control signal when the number of data input / output is reduced. At the same time, the second control signal generator is supplied with a predetermined level signal which does not affect the enable of the second control signal, and when the number of data input / outputs is increased, the address input unit and the second control signal generator are connected. Redundancy decoder of a semiconductor memory device, characterized in that it comprises a switching unit. The method of claim 1, The option pad is connected between an extra pin provided in the package of the semiconductor memory device and the switching unit to transfer the third control signal received from the outside through the extra pin to the switching unit. Redundancy decoder of semiconductor memory device. The method of claim 1, The option pad may be disposed between the power pad and the ground pad of the semiconductor memory device to bond the third control signal having a logic “high” or “low” level depending on whether the power pad or the ground pad is bonded. The redundancy decoder of the semiconductor memory device, characterized in that the transfer to the switching unit.