JPH10188595A - Circuit and method for replacing defective memory cell with redundant memory cell - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce complexity of a redundant circuit by providing a matrix switch connecting a memory cell with a data line, a matrix switch control circuit opening the matrix switch when a cell fails, a redundant switch connecting a redundant cell and the data line, and a control circuit closing the redundant switch corresponding to the first value of a redundant address signal. SOLUTION: When a plurality of defective rows are discovered in a matrix memory array 2 and the defective row is addressed, a redundant row decode and select circuit 28 decodes a row selection signal from an address decoder 14 and activates a redundant word line related to a mapped redundant row. Similarly, when a plurality of defective columns are discovered and the defective column is addressed, a redundant column decode and select circuit 30 decodes a column selection signal from the address decoder 14 and connects a read/write circuit 24 to a complementary bit line of a mapped redundant column. A fuse is burnt out to separate the defective row and defective column from the read/ write circuit 24.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates generally to integrated electronic circuits, and more particularly, to circuits and methods for removing defective memory cells from a line and replacing the defective memory cells with redundant memory cells. It is about.

[0002]

BACKGROUND OF THE INVENTION Many integrated memory circuits today have redundant memory cells that can replace a failing or defective matrix memory cell. Typically, the entire matrix row or column to which the defective memory cell belongs is identified as defective and replaced with a redundant row or column, respectively. Often, only one defect matrix row or column causes the memory circuit to malfunction. Thus, by providing redundant rows and columns on the integrated memory circuit, engineers can repair otherwise unusable memory circuits and the overall manufacturing yield of operable memory circuits. Can be increased.

[0003] Typically, engineers perform tests to find and identify rows and columns with defective memory cells shortly after the memory circuit is manufactured. For example,
After the test station identifies a defective column, it causes the redundant column to be mapped to the address of the defective column. When an external circuit such as a processor writes data to an address of a memory cell in a defective column via a data bus during a normal operation period of the memory circuit, a redundant circuit in the memory circuit stores the data in the defective column. Separate from the bus and supply the data to the corresponding memory cells in the redundant column. Redundancy circuits within the memory circuit provide this isolation and supply in a manner that is transparent or invisible to external circuits. One problem with many redundant circuits is that the access time of the redundant columns is significantly slower than the access time of the matrix columns. Thus, if a redundant column is mapped to replace a defective matrix column, the rated access time of the memory circuit will often be increased to accommodate the slower access time of the mapped redundant column. . Further, redundant columns and redundant circuits often significantly increase the layout area of the memory circuit.
Such an increase in layout area is often
This will increase cost, manufacturing time, test time, or redundant mapping time associated with the memory circuit.

[0004] Further technical background on memory circuits and column redundancy can be found in Prince, Betty, "Semiconductor Memory, Design, Manufacturing and Application Handbook (Semico).
nductor Memories, A Handb
book of Design, Manufactur
e, and Applications) ", Second
Edition, John Wiley and Sons Publishers, 199
1, Hardee et al. "Defect tolerance 30 ns /
375mW16K × 1NMOS static RAM (A
Fault-Tolerant 30 ns / 375
mW 16K × 1 NMOS Static RA
M) ", Journal of Solid State Circuits, SC-16 (5): 435-43 (IEEE,
1981), Childrens et al. "18ns4
K × 4 CMOS SRAM (An18 ns 4K ×
4 CMOS SRAM) ", Journal of Solid State Circuits, SC-19 (5): 54
5-51 (IEEE, 1984), ISSCC Proceedings, 1975 to the present, all of which are incorporated herein by reference.

[0005]

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and has solved the above-mentioned disadvantages of the prior art, and has an improved circuit for replacing defective memory cells with redundant memory cells. The aim is to provide a method.

[0006]

According to one aspect of the invention, when a matrix memory cell is defective, the matrix memory cell is separated from the data lines and the redundant memory cells are coupled to the data lines. A memory access circuit is provided. The memory access circuit includes a matrix switch coupled between a matrix memory cell and a data line, and a matrix switch control circuit that opens the matrix switch if the matrix memory cell is defective. I have. The memory access circuit further includes a redundant switch coupled between the redundant memory cell and the data line, and receiving the redundant address signal and closing the redundant switch if the redundant address signal has a first value. And a redundant switch control circuit.

An advantage of the present invention is that it reduces the complexity of the redundancy architecture, reduces the layout area of the memory circuit, and increases the access speed of the mapped redundant columns. . One aspect of the present invention achieves such advantages by removing isolation elements, such as fuses, from the bit lines of the matrix and redundant columns, for example.

[0008]

FIG. 1 is a block diagram of a memory device or circuit 10 according to the present invention. In one aspect of the present invention, the memory device 10 comprises a 32K × 32 bit burst static random access memory (burst SRA).
M).

Although memory 10 has its matrix memory cells arranged in an even number of memory blocks B ₀ -B ₃₁ , other embodiments of memory 10 may have more, less, or odd numbers of memory cells. It is possible to have such a memory block. The memory cells in each block B ₀ -B ₃₁ are arranged in rows and columns. One row refers to a group of memory cells coupled to a common word line, and one column is a common bit line or, in the case of an SRAM, a common pair of complementary cells. Means a group of memory cells coupled to a typical bit line.

The block B ₀ -B ₃₁ is divided into four quadrants Q ₀ -Q ₃ each consisting of eight blocks.
That is, the quadrant Q ₀ has a block B ₀ -B _7, quadrants Q ₁ is has a block B ₈ -B _15, quadrant Q ₂ is has a block B ₁₆ -B _23, and quadrant Q ₃ are has a block B ₂₄ -B _31. Each quadrant Q ₀ -Q ₃ supplies eight of the 32 data bits D ₀ -D ₃₁ provided by the memory 10. During a read or write cycle,
One block from each quadrant is accessed and provides 8 bits of data for that quadrant. For example, during a read or write cycle, block B from quadrant Q _0
0, block B ₈ from quadrant Q _1, block B ₁₆ from quadrant Q _2, block B ₂₄ from quadrant Q ₃ is simultaneously activated, supplies a D ₀ -D _31. A master word line decoder 12 is located along one central axis of the memory device 10. Master word lines MWL ₀ -MWL ₃
Are traveling through each quadrant Q ₀ -Q ₃ respectively. The local word line decoders LWD ₀ -LWD ₁₅ are:
It is located between each pair of blocks B ₀ -B ₃₁ .

The memory 10 further has 16 block input / output circuits BLKIO _0-15 , which are:
Each associated with the block B ₀ -B ₃₁ of the corresponding pair. The BLKIO circuit connects memory cells in blocks B ₀ -B ₃₁ to 32 external data input / output pins or terminals DQ.
Corresponding to bind to the ones of ₀ -DQ _31. The memory 10 further has other external terminals for receiving an address signal, a control signal, and a power signal from an external circuit (not shown). A memory device similar to memory 10 is described in U.S. patent application Ser. No. 08 / 587,708, entitled "Device and Method for Driving Conductive Paths with Signals"
ND METHOD FOR DRIVINGA CO
DUCTIVE PATH WITH A SIGNA
L) ", filed January 19, 1996, U.S. Patent Application No. 0
No. 8 / 588,762, "Data input device (DATA-I for generating test signal on bit line and bit complement line)
NPUT DEVICE FOR GENERATEN
G TEST SIGNALSON BIT AND
BIT-COMPLEMENT LINES) ", 19
Filed January 19, 1996, US patent application Ser. No. 08/589,
No. 141, “Write driver with test function (WRI
TE DRIVER HIVING A TEST F
UNCTION), filed Jan. 19, 1996, U.S. patent application Ser. No. 08 / 589,140, entitled "MEMORY-ROW SEL with Test Function".
ECTOR HIVING A TEST FUNCT
ION), filed Jan. 19, 1996, US patent application Ser. No. 08 / 588,740, entitled "Apparatus and method for separating bit lines from data lines (DEVICE AND ME
THOD FOR ISOLATING BIT LI
NES FORM A DATA LINE) ", 19
Filed January 19, 1996, US patent application Ser. No. 08/589,
No. 024, "Low-power reading circuit and method for controlling a sense amplifier (LOW-POWER READ CI
RCUIT AND METHOD FORCONTR
OLLING A SENSE AMPLIFIE
R) ", filed January 19, 1996, which are incorporated herein by reference.

FIG. 2 is a schematic block diagram of the memory 10 of FIG. Address decoder 14 receives an address signal from an external circuit (not shown), decodes the address signal, and supplies a corresponding column select and row select signal to row and column select circuit 16. Matrix row selection circuit 18 receives the row selection signal from the address decoder, and forms matrix memory array 2 forming a part of memory array 21.
Activate the word line in the addressed matrix memory row within 0. Similarly, matrix column select circuit 22 receives a column select signal from address decoder 14 and couples the bit line of the addressed matrix memory column in matrix array 20 to read / write circuit 24.

If a defective matrix row of a plurality of memory cells in the array 20 is found during an initial test of the memory 10, it is replaced by a redundant memory row 26 of a plurality of redundant memory cells. With one of the following. That is, the redundant row is mapped to the address of the defective matrix row. When the defective matrix row is addressed, redundant row decode and select circuit 28 decodes the row select signal from address decoder 14 and activates the redundant word line associated with the mapped redundant row. Similarly, if during the initial test of memory 10 a defective matrix column of memory cells in array 20 is found, it is replaced with one of redundant memory columns 32. That is, the redundant column is mapped to the address of the defective matrix column. When the defective matrix column is addressed, redundant column decode and select circuit 30 decodes the column select signal from address decoder 14 and couples read / write circuit 24 to the complementary bit line of the mapped redundant column. Defective rows and columns of a plurality of memory cells in matrix array 20 are isolated from read / write circuit 24, as described below in connection with FIGS. Therefore, circuits 28 and 30
Maps the redundant rows 26 and redundant columns 32 to the addresses of the defective matrix rows and columns in the matrix array 20 in a manner that is transparent or invisible to external circuitry that supplies address signals to the address decoder 14, respectively. To make things possible.

Still referring to FIG. 2, during a write cycle, read / write circuit 24 receives data from the data bus via input / output (I / O) buffer 34 to address in memory array 21. To the selected memory cell.
During a read cycle, read / write circuit 24 transfers data from the addressed memory cells to I / O buffer 24.
To the data bus via. Read / write circuit 24
Has one or more write drivers for writing data to the addressed memory cells and one for reading data from the addressed memory cells.
It has one or more sense amplifiers. I / O buffer 34 has an input buffer that supplies data from the data bus to read / write circuit 24 during a write cycle, and data from read / write circuit 24 during a read cycle. To the data bus.

The control circuit 36 receives control signals from the control bus, and in response thereto, operates the address decoder 14, the row and column selection circuit 16, the read array 21, the read / write circuit 24, and the I / O buffer 34. Control. Wafer test mode circuit 38 receives a wafer test signal from a wafer test bus and, while the die (not shown) containing memory 10 is part of the wafer (not shown) on which it is formed, i.e., Before scribing from the wafer,
Allow memory 10 to operate in one or more test modes.

[0016] FIG. 3 is a block diagram of a memory block B ₀ of the memory 10 of FIG. Block B ₀ is shown and described, but the remaining blocks B ₁ -B ₃₁
Are configured and operated in a similar manner. In an embodiment of the present invention,
Block _B0 has eight matrix column groups 40a-4
0h, each of which has 16 matrix memory columns. Therefore, the block B ₀ has a total of 12
It has eight matrix memory columns.

Each matrix column group 40a-40h
Is connection therewith, has an input / output of each (I / O) circuit _{I / O 0 -I / O 7} . The associated I / O circuit selects the addressed one of the 16 columns in group 40, and during a read cycle,
Bits of the selected matrix column - true lines and bit - reading the Complement line - true (RBT ₀ -RBT ₇₎ one associated of the line and read - complement (RBC ₀ -RB
C ₇₎ is coupled to an associated one of line. Similarly, during a write cycle, I / O circuits, respectively, of the selected matrix column bit - true lines and bit - complement write the original line - true (WBT ₀ -WTB ₇₎ of the line Related one and write-complement (WBC ₀ -WBC
₇ ) Connect to the relevant one of the lines.

The block B ₀ further includes a redundant column group 4
2 which is a matrix column group 40a-
It includes one or more redundant memory columns that can be used to replace defective columns in any of 40h. The number of redundant columns in redundant column group 42 is between the predicted number of matrix columns in groups 40a-40h having defective memory cells and the amount and cost of additional area required for each redundant column. Based on the equilibrium of In the illustrated example, the redundant column group 42 has two redundant columns. Since each block B ₀ -B ₃₁ has a redundant column group 42 itself, the redundant column decode and select circuitry 30 (FIG. 2) is not necessary to be centrally located, and the block B ₀ - it can be dispersed in each of the B _31. Such a local distribution is often
It reduces the complexity and area required by routing interconnects within circuit 30. Furthermore, the redundant columns of block B ₀ can use the same local word line driver LWD ₀ as the matrix memory columns, thus reducing programming overhead.

Redundant input / output selection circuit RI / O ₀ -R
I / O ₇ includes each of the redundant columns in redundant column group 42 and read bit true lines RBT ₀ -RBT ₇ , read bit complement lines RBC ₀ -RBC ₇ , write bit true lines WBT ₀ -WBT ₇ , Write bit complement line WBC ₀ −
It is coupled between its WBC ₇ counterparts. For example, the block RI / O ₀ includes each of the redundant columns and RBT ₀ ,
It is coupled between RBC ₀ , WBT ₀ , and WBC ₀ . Redundant column decode circuit RD ₀ includes address decoder 1
4 (FIG. 2) receives a matrix column selection signal, and
If the corresponding matrix column in one of groups 40a-40h is defective, a selected one of the redundant columns in group 42 is activated to replace the defective matrix column.

In operation, during a normal read or write cycle, local word line decoder LWD
₀ activates the addressed row comprising a plurality of matrix memory cells in the block B _0. Block I /
Group 40a-40 to which each of O ₀ -I / O ₇ corresponds
h, select the addressed one of the columns (for a total of eight selected columns, one from each group 40a-40h), and change the bit true line and bit complement line of the selected column. , Depending on whether the cycle is a read or a write, the corresponding lines RBT and RBT
Bound to BC or WBT and WBC. Thus, for example, during a read cycle, circuit I / O ₀ is
The bit true line of the selected column in Oa is coupled to RBT ₀ and the bit complement line of the same column is coupled to RBC ₀ . During a write cycle, circuit I / O ₀ couples the bit true and complement lines of the selected column in group 40a to WBT ₀ and WBC ₀ , respectively. As described below in connection with FIG. 5, in one embodiment of the present invention, during both the read and write cycles, circuit I / O ₀ operates on selected columns in group 40a. is bound bit true line to both RBT ₀ and WBT _0, and bit complement lines of RBC ₀ and W
To bind to both of BC _0.

If a matrix column in one of the matrix column groups 40a-40h is found to be defective, one of the redundant columns in the redundant column group 42 is mapped to replace the defective matrix column. Is done. For example, assume that a defective column has been found in group 40a. If the defective column is addressed, the circuit RD ₀ generates a redundant column selection signal. In response to this redundant column select signal, circuit RI / O ₀ couples the bit true line and bit complement line of the mapped redundant column to RBT ₀ and RBC ₀ during a read cycle, respectively, and writes. During the cycle, the mapped true column bit true line and bit complement line are coupled to WBT ₀ and WBC ₀ , respectively. Circuit I / O ₀
Sets the defect matrix columns in the group 40a to RBT ₀ , RBT ₀
Decoupled from BC ₀ , WBT ₀ , WBC ₀ , so that all data transactions are routed to the mapped redundant column instead of the defective memory column.

[0022] Figure 4a is a schematic diagram of one embodiment of a redundant decoder RD ₀ in FIG. In the illustrated example of the memory 10,
Redundant decoder RD ₀ -RD ₁₅ one by one 16 placed against the block B ₀ / B ₃₁ all pairs are present. Decoder RD ₀ is associated with the block B ₀ and B _1, and the remaining decoders RD ₁ -RD ₁₅ is similar in structure and operation and decoder RD _0. Furthermore, since each pair of blocks has a total of four redundant columns, each redundant decoder
There are four redundant address signal generators RSC ₀ -RSC ₃ , one for each redundant column. Therefore, RD ₀
With respect to the address signal generators RSC ₀ and RSC
₁ can be used to generate the redundant address signals for the two redundant columns in the block B _0, and generators RSC ₂ and RSC ₃ is redundant address for the two redundant columns in the block B ₁ Can be used to generate a signal.

FIG. 4b is a schematic diagram of the signal generator RSC ₀ of FIG. 4a. Generator RSC ₀ has an enable circuit 44, which is associated redundant column, i.e. redundant column 0 can enable or operating the generator RSC ₀ when mapped to the address of the defective matrix column state And if redundant column 0 is not so mapped, disables generator RSC ₀ . The control circuit 46 controls the address decoder 1
4 (FIG. 2) from the matrix column selection signal COL <0:15
> And the column selection signal COL <0:15> corresponding to the defective column to which the redundant column 0 is mapped
Has an active logic 1 signal level, generates an active logic 1 at node N2. One generator RSC _{0 is} provided for each matrix column selection signal COL <0:15>.
There are 16 circuits 46 in total. Output circuit 50 receives the signal at node N2 and active low redundant column select signal RCOL0 on output line 52.
_ Is generated. In this specification, an underlined symbol after an English character symbol indicates that the signal is an inverted signal of the English character symbol.

During a read or write cycle, redundant column 0
Is not mapped to replace the defective matrix column, the selective conducting element 54 of the enable circuit 44 is turned on. Element 54 and similar elements described below can be laser fuses, electrical fuses, programmable memory cells, or other elements having selectable conductivity. Conductive element 54
Couples a supply (power) voltage Vcc equivalent to logic 1 to an input of a latch circuit 56 having an inverter 58 and an NMOS transistor 60. Latch 56 generates a logic zero at the output of enable circuit 44. NOR gate 64 of control circuit 46 receives a logic 0 from latch 56 at one input and a signal CRS that is an inactive logic 0 at the other input, and thus generates a logic 1 at its output. A logic 0 from latch 56 and a logic 1 from NOR gate 64 deactivate pass gate 65, each of which is coupled to an NMO coupled in parallel to a PMOS transistor.
It is formed from S transistors. Therefore, pass gate 65 in the inactive state prevents all of signals COL <0:15> from propagating to node N2. Furthermore, NOR
The logic one generated by gate 64 activates NMOS transistor 66, which causes node N2 to go to logic zero.
Drive to The output circuit has one input terminal.
Receiving a signal ISO is active logic 1 for selecting the block B ₀ in and the other input terminal receives a logic zero at node N2. Accordingly, output circuit 50 generates inactive logic 1 for redundant column select signal RCOL0_ on line 52.

During a read or write cycle, redundant column 0
Are mapped to replace a defective matrix column, element 54 is rendered non-conductive. During the power-up period of the memory 10, a power-on reset (P
The OR) signal is a logic one for a predetermined time period, and activates the transistor 62 of the enable circuit 44 during this period. The active transistor 62 is connected to the latch circuit 56
Is coupled to ground, which is equivalent to logic zero. Latch circuit 56 maintains a logic one at its output, even after POR has returned to a logic zero. NOR gate 64
Receives a logic one from latch 56 at one input and deactivates logic zero at another input.
S, thus producing a logical zero at its output. A logic one from latch 56 and a logic zero from NOR gate 64 activate pass gate 65. All the selectively conducting elements 69 are turned off except for the element 69 corresponding to the defective column. Therefore, when one of the signals COL <0:15> corresponding to the defect matrix column shifts to active logic 1, the logic 1 changes to the corresponding pass gate 6
5 and the conduction element 69 to the node N2. N
Since logic 0 from OR gate 64 deactivates transistor 66, the output circuit converts the logic 1 and logic 1 ISO signals at node N2 to active logic 0 for RCOL0_. Active logic 0 for RCOL0_ selects redundant column 0.

During a first test mode, all matrix memory columns are tested simultaneously and all redundant memory columns are tested simultaneously to see if they are mapped to replace defective memory columns. The signal CRS is active logic one. If redundant column 0 is not mapped to replace the defective matrix column,
The element 54 is conductive, the output of the latch 56 is a logic zero, and the output of the NOR gate 64 is a logic zero. Thus, the PMOS transistor of pass gate 65 is active, element 69 is conductive, and signals COL <0:15>, all of which are active logic 1 to select all matrix columns simultaneously, are at nodes N
2 Further, ISO is active logic one, and output circuit 50 generates RCOL0_ equal to logic zero, which selects redundant column zero accordingly. Redundant column 0
Is mapped to replace the defective matrix column, the element 54 is non-conductive and the latch 56
Is a logical one, and the output of NOR gate 64 is a logical zero. Thus, the PMOS transistor of pass gate 65 is active, only the element 69 corresponding to the defective column is conductive, and the signal COL is all active logic 1 to select all matrix columns simultaneously. A corresponding one of <0:15> is coupled to node N2. Further, transistor 66 is inactive, ISO is active logic 1, and output circuit 5
0 generates RCOL0_ equal to logic 0, which selects redundant column 0 accordingly.

During a second test mode during which all non-defective matrix columns are tested simultaneously, but only redundant columns that have been mapped to replace defective matrix columns are tested with the non-defective matrix columns. CRS
Is inactive logic 0. Therefore, the operation of the circuit RSC ₀ is the same as that described above during the normal operation of the memory 10. That is, if redundant column 0 is mapped to replace a defective matrix column, circuit RSC ₀
Selects RS during the second test mode, and if redundant column 0 is not so mapped, RS
C ₀ does not select it.

In both the first and second test modes, the memory cells in the selected matrix and redundant columns are often stressed with an increased DC voltage, for example, 7-9V. This increased voltage is typically applied to one of the bit true and complement lines in one column, while 0V is applied to the other line. The voltages are then reversed. If the memory cell does not fail when this increased voltage is applied, it is possible to have considerable confidence that it will not fail when a normal operating voltage of, for example, 5 V is applied. It is.

The advantage provided by this second test mode is that it can be implemented after replacing the defective matrix columns with redundant columns and that only the mapped redundant columns are tested. Therefore, since it does not affect the operation of the memory 10,
Redundant columns that are not defective and have not been mapped will not identify memory 10 as defective in this second test mode. Thus, this second test mode prevents the possibility of discarding the functional memory 10 because the unmapped redundant columns are defective.

FIG. 5 is a schematic diagram showing a first embodiment of the section 23 of the matrix column selection circuit 22 of FIG. There is one arrangement of sections 23 for each column in the matrix column groups 40a-40h of FIG. Although only one arrangement is shown for matrix column 0 in group 40a, it should be understood that each arrangement is configured and operates in a similar manner. Section 23 includes matrix pass gates or switches 82 and 84, which are respectively coupled between the bit true and complement lines of matrix column 0 and the read lines RBT ₀ and RBC _0. And each of them has an active low column select signal CO
It has a control terminal coupled to L0_. In the illustrated example of the invention, switches 82 and 84 are PMOS
It is a transistor. Section 23 also includes matrix pass gates or switches 86 and 88;
They are the bit true line and bit complement line of matrix column 0 and the write lines WBT ₀ and WBC, respectively.
₀ , and each of them has a control terminal coupled to COL0_ via an inverter 90. In the illustrated example, switches 86 and 8
8 is an NMOS transistor. The selective conducting isolation elements 92 and 94, when in a non-conducting state, respectively,
The bit true lines are separated from switches 82 and 86 and the bit complement lines are separated from switches 84 and 88.

In operation, during a read or write cycle, if matrix column 0 is not selected and is functional, ie, non-defective, and has not been replaced with a redundant column. Is COL0_ is a deactivated logic one, which deactivates the switches 82, 84, 86, 88. The inactive switches 82, 84, 86, 88
The bit true line and the bit complement line of the matrix column 0 are represented by lines RBT ₀ and WBT ₀ and RBC ₀ and WBC
Each is decoupled or separated from ₀ , thus preventing reading data from or writing data to memory cells in matrix column 0. When column 0 is selected, C
OL0_ is active logic 0, which indicates that switches 82, 8
Activate 4,86,88. Active switches 82, 8
4,86,88 The matrix column bit true lines and bit complement lines lines RBT ₀ and WBT ₀ of 0, and each coupled to a RBC ₀ and WBC _0, thus reading data from the memory cells in the matrix column 0 Alternatively, data can be written to it.

If matrix column 0 is found to be defective during the testing of memory 10, the redundant memory column is mapped to the address of defective matrix column 0, and isolation elements 92 and 94 are non-defective. The conductive state isolates the bit true line and bit complement line of defective matrix column 0 from lines RBT ₀ and WBT ₀ and RBC ₀ and WBC ₀ , respectively. Therefore, CO
L0_ is active logic 0 and switches 82, 84, 8
Even if 6,88 were active, defect matrix column 0
Is separated from the read and write lines and the memory 1
It does not adversely affect the operation of 0.

FIG. 6 shows two redundant column selection circuits 96a and 96 of the RI / O ₀ circuit of FIG. 3 according to the first embodiment of the present invention.
FIG. 3b is a schematic diagram of FIG. 3b, and it should be understood that the redundant column selection circuits of RI / O ₁ -RI / O ₇ are configured and operate in a similar manner. When selected, circuit 96a provides redundant column 0 from redundant column group 42 (FIG. 3).
Read and write lines RBT ₀ , WBT ₀ , RBC ₀ ,
Coupled to WBC ₀ , and circuit 96b couples redundant column 1 from redundant column group 42 to the same read and write lines. For convenience, only circuit 96a will be described in detail, but it should be understood that circuit 96b is similarly configured and operates.

Redundant column select circuit 96a has a first pair of redundant pass gates or switches 98 and 100, which are the bit true line and bit complement line of redundant column 0 and RBT ₀ and RBC _{0, respectively.} And each has a control terminal coupled to RCOL0_. A second pair of redundant switches 102 and 104 are respectively coupled between the bit true and complement lines of redundant column 0 and WBT ₀ and WBC ₀ , and each is connected via an inverter 106 to the RCO
It has a control terminal coupled to L0_. In the illustrated example of the invention, switches 98 and 100 are PMOS
Transistors, and switches 102 and 104 are NMOS transistors. Selective conducting elements 116 and 118 are coupled between RBT ₀ and RBC ₀ and switches 98 and 100, respectively, and selective conducting elements 120 and 122 are connected to the bit true line of redundant column 0, respectively. Switches 100 and 104 and a bit complement are coupled between switches 98 and 102.

The balance and precharge circuit 108 is a PMO
It has S transistors 110, 112, 114,
They precharge and balance the bit true line and the bit complement line of redundant column 0 in a conventional manner. During operation during each read and write cycle, the balancing and precharging circuit 108 is active low or active low balanced / active low.
Receiving and responding to the precharge signal, the bit true line and bit complement line of redundant column 0 are coupled to Vcc and to each other, so that these complementary bit lines are at the beginning of each read and write cycle. Carries the same voltage level.

In operation, if redundant column 0 is not mapped to the address of the defective matrix column, as described above in connection with FIG. 4b, RCOL0_ is a deactivated logic 1 and it , 100,1
02 and 104 are made inactive. These inactive switches read redundant column 0 for read and write lines RB.
Detach from T ₀ , RBC ₀ , WBT ₀ , WBC ₀ .
Elements 116, 118, 120, 122 if redundant column 0 is mapped to replace matrix columns that are coupled to read and write lines other than RBT ₀ , RBC ₀ , WBT ₀ , WBC ₀ Are turned off, so that redundant column 0 is separated from RBT ₀ , RBC ₀ , WBT ₀ , and WBC ₀ irrespective of the logical level of RCOL 0 _.

The redundant column 0 is a matrix column group 40a
If it is mapped to replace matrix column 0 of FIG. 3 (elements 116, 118, 120,
Reference numeral 122 denotes a conducting state, and RI / O ₁ -RI / O ₇
Corresponding elements in the other redundant column selection circuits of N are rendered non-conductive, so that redundant column 0 becomes RBT ₁ -RBT ₇ ,
RBC ₁ -RBC ₇ , WBT ₁ -WBT ₇ , WBC _1-
Separated from WBC ₇ . In operation, when defect matrix column 0 is addressed, RCOL0_ is active logic 0, which activates switches 98, 100, 102, 104, as described above in connection with FIG. 4b. These active switches couple the bit true lines of redundant column 0 to RBT ₀ and WBT ₀ and allow data to be read from and written to redundant column 0 instead of defective matrix column 0. RBC bit complement line
₀ and WBC ₀ .

FIG. 7 shows the matrix column selection circuit 22 of FIG.
FIG. 4 is a schematic diagram of a second embodiment of one section of FIG. There is one arrangement of sections 128 for each column in the matrix column groups 40a-40h (FIG. 3). Section 1 for matrix column 0 in group 40a
Although only 28 arrangements are shown, it should be understood that each arrangement of section 128 is configured and operates in a similar manner.

Section 128 includes a conventional precharge and balance circuit 134, which precharges and balances the bit true and complement lines of matrix column 0 between read and write cycles. To Section 128 further includes a matrix switch circuit 130, which includes matrix switches 136 and 138. Switches 136 and 138 control the bit true line and bit complement line of matrix column 0 and read lines RBT ₀ and RB, respectively.
And C ₀ . Switches 136 and 13
Each of the eight has a control terminal coupled to a first output 141 of the matrix switch control circuit 132. The matrix switch circuit 130 further includes matrix switches 140 and 142, which are coupled between the bit true line and bit complement line of matrix column 0 and the write lines WBT ₀ and WBC ₀ , respectively. Have been. Each of the switches 140 and 142 has a control terminal coupled to the second output 143 of the matrix switch control circuit 132. In the illustrated example of the invention, switches 136 and 138 are PMOS transistors, and switches 140 and 142 are NMOS transistors.

The matrix switch control circuit 132
MOS transistor 144 and NMOS transistor 14
6 formed from the first inverter.
The first inverter has an active high COL at its input.
0 and provides a first output 141 of the circuit 132. The second inverter 148 inverts the signal at the first output 141 and provides a second output 143 of the circuit 132. Inverter 148 and PMOS transistor 15
0 are coupled to form a latch circuit 151. The control circuit 132 receives the block enable signal ISO, which is active logic 1 when block B ₀ (FIG. 1) is selected, as described above in connection with FIG. 4b.
ISO is supplied to the gates of the optional enable NMOS transistor 152 and the optional reset PMOS transistor 154. Selectively conducting disable element 156 is coupled between transistor 146 and supply (power) voltage Vss.

In operation, between a read cycle and a write cycle, the precharge and balancing circuit 134 of FIG.
Operates in a similar manner to precharge and equilibrate the bit true lines and bit complement lines of matrix column 0. During a read or write cycle involving matrix column 0 if matrix column 0 is not defective, the ISO
Is active logic one, which activates transistor 152 and deactivates transistor 154. CO
L0 is an active logic one, which activates transistor 146 and deactivates transistor 144.
Active transistor 146 includes transistors 136 and 13
Drive the gate of 8 to logic 0, which activates these transistors. Active transistors 136 and 138 couple RBT ₀ and RBC ₀ to the bit true line and bit complement line of matrix column 0, respectively. Similarly, inverter 148 is connected to transistor 136
And 138 invert the logic 0 to a logic 1, which activates transistors 140 and 142. Active transistors 140 and 142 couple WBT ₀ and WBC ₀ to the bit true line and bit complement line of matrix column 0, respectively.

During a read or write cycle involving matrix columns other than matrix column ₀ of block B ₀ , I
Either or both SO and COL0 are inactive logic zero. If ISO is a logical 0 and indicates that block B ₀ is unselected, transistor 152 is inactive and transistor 154 is active. Active transistor 154 has a Vcc equivalent to logic one.
To the gates of transistors 136 and 138,
Therefore, they are deactivated. The inverter 148
Supply a logic zero to the gates of transistors 140 and 142, thus deactivating them. Similarly, COL0
Is logic 0, indicating that matrix column 0 of any of blocks B ₀ -B ₃₁ is in a non-selected state, transistor 146 is inactive and transistor 144 is active. The active transistor 144
Vcc is coupled to the gates of transistors 136 and 138, thus deactivating them. Inverter 14
8 supplies a logic zero to the gates of transistors 140 and 142, thus deactivating them. Therefore, if any of the blocks B ₀ or matrix column 0 is a non-selected state, sections 128 of the matrix column 0 of the block B ₀ RBT _0, RBC _0, WBT _0, WBC ₀
Separated from

During a read or write cycle involving matrix column 0 when matrix column 0 is defective,
Element 156 is rendered non-conductive, so it does not couple the source of transistor 146 to Vss.
When the memory 10 is powered up during the initialization routine, the ISO transitions to inactive logic 0 and activates the transistor 154 for a predetermined time, which means that the logic 1
To the input of the inverter 148. Inverter 14
A logic 0 at the output of 8 activates transistor 150, which reinforces a logic 1 at the input of inverter 148. Thus, latch circuit 151 latches a logic one at the gates of transistors 136 and 138 and a logic zero at the gates of transistors 140 and 142, thus disabling these transistors. Thus, by causing element 156 to be non-conductive, if matrix column 0 is defective, control circuit 132 disables circuit 130, which in turn causes defective matrix column 0 to be read line and write line. Separated from

An advantage of circuits 132 and 130 is that selective conducting elements, such as fuses, for example, are not required between the true and bit complement lines of matrix column 0 and circuit 130 and circuit 130. is there. Therefore, the total number of such elements is reduced by about half. Further, it is not necessary to cut such elements such as laser fuses adjacent to the bit lines. This reduces the likelihood of errors occurring during the laser cutting of the element, especially if the size of the memory device is generally reduced, and therefore the bit true line and bit complement of each column. This is useful if the pitch between the original line and the original line is reduced. Furthermore, if such a fuse is omitted, the series resistance of the bit line is reduced. This can significantly increase the speed at which memory cells are accessed. Further, the use of such bit line fuses may place limitations on the manufacturing process. This is because the layer in which the fuse is manufactured must have a relatively low sheet resistance. Conversely, circuits 130 and 132 do not impose such restrictions.

FIG. 8 is a schematic diagram of a second embodiment of the redundant selection circuit of the redundant column decoding and selection circuit 30 of FIG. For the sake of simplicity, only the arrangement of redundant column circuits 158 of RI / O ₀ (FIG. 3) corresponding to redundant column 0 of redundant column group 42 will be described, but the remaining RI / O ₀ -RI / O ₇ will be described. It should be understood that redundancy select circuit 158 has a similar configuration and operates in a similar manner. Further, the section 128 (FIG. 7) of the matrix column selection circuit 22 (FIG. 2)
And the combination of the redundancy selection circuit 158 can be referred to as a memory access circuit. Redundancy selection circuit 15
8 has a precharge and balancing circuit 160,
It is similar in construction and operation to the precharge and balancing circuit 134 of FIG. Redundant switch circuit 162 selectively couples RBT ₀ , RBC ₀ , WBT ₀ , and WBC ₀ to the bit true line and bit complement line of redundant column 0 of block B ₀ (FIG. 3). Redundant switch control circuit 1
Reference numeral 64 controls the switch circuit 162.

More specifically, the redundant switch circuit 162 has switches 166 and 168 coupled between the bit true line and the bit complement line of the redundant column 0 and RBT ₀ and RBC ₀ , respectively. The bit true line and the bit complement line and WBT ₀ and WB
It has switches 170 and 172 respectively coupled to C ₀ . In the illustrated example, the switch 1
66 and 168 are PMOS transistors, and switches 170 and 172 are NMOS transistors. Redundant switch control circuit 164, RCOL0_ (from decoder RSC ₀ in Fig. 4b) and the switches 166 and 1
68 and a second selective conducting element 176 coupled between the active low signal CRS_ and the control terminals of switches 166 and 168. have. Inverter 178 includes elements 174 and 176 and switches 170 and 1
72 are connected to the control terminal.

In operation, during a read or write cycle, if redundant column 0 is not mapped to replace a defective matrix column, element 17
4 and 176 are both conductive. In addition, RCO
Both L0_ and CRS_ is inactive logic 1, the switch circuit 162 is disabled, that matter to separate the redundant column 0 from RBT _0, RBC _0, WBT _0, WBC _0. Elements 174 and 176 in the circuit 158 of RI / O ₁ -RI / O ₇ are also rendered conductive, so that the unmapped redundant column 0 also has RBT ₁ -RBT ₇ , RBC ₁
-RBC ₇ , WBT ₁ -WBT ₇ , WBC ₁ -WBC ₇
Separated from

During a read or write cycle, redundant column 0
Matrix column group 40b-40h of but block B ₀
Redundant column 0 is mapped to replace the defective matrix column in one of the
_1- RBT ₇ , RBC ₁ -RBC ₇ , WBT _1- WBT
₇ , WBC ₁ -WBC ₇ should be coupled to the corresponding one, element 174 is rendered non-conductive and element 1
Reference numeral 76 indicates a conductive state. Therefore, when the RCOL0_ transitions to an active logic 0, CRS_ the circuit 162 is disabled stops inactive logic 1, thus redundant column 0 is separated from RBT _0, RBC _0, WBT _0, WBC ₀ .

During a read or write cycle, redundant column 0
Are mapped to replace matrix column 0 of matrix column group 40a, element 17
4 is turned on and element 176 is turned off. Therefore, when defect matrix column 0 is addressed,
The decoder circuit RSC ₀ of FIG. 4b drives RCOL0_ to active logic 0, which means that the switches 166, 168, 1
Activate 70,172. These active switches connect the bit true lines of redundant column 0 to RBT ₀ and WBT ₀
And the bit complement line of redundant column 0 is connected to RBC ₀
And WBC ₀ . In circuit 158 of RI / O ₁ -RI / O ₇ , element 174 is turned off and element 176 is turned on, so that redundant column 0 has RB
T ₁ -RBT ₇ , RBC ₁ -RBC ₇ , WBT ₁ -WB
Is separated from the T _7, WBC ₁ -WBC _7.

As described above in connection with FIG. 4b, a first test mode for simultaneously testing all matrix columns and all redundant columns before any redundant columns are mapped to replace defective matrix columns. During the period, element 17
4 and 176 are conductive in all of the redundant selection circuits 158 of RI / O ₀ -RI / O ₇ . In addition, RCOL
0_ is active logic 0, so redundant column 0 is
_{T 0 -RBT 7, RBC 0 -RBC} 7, WBT 0 -W
BT ₇ , WBC ₀ -Coupled to all of WBC ₇ . CRS_ is also active logic zero to prevent signal contention at the input of inverter 178. Thus, the advantage of control circuit 164 is that it eliminates the switching transistors of conventional control circuits by ensuring that there is no contention between RCOL0_ and CRS_ when both elements 174 and 176 are conductive. That is possible. Further, the circuit 164
Are also the selective conducting elements 116, 118, 12 of FIG.
It is possible to omit 0,122 and thus reduce the number of such elements by about half. Removing such switching transistors and elements reduces the layout area of the memory 10. Furthermore,
If these elements are laser fuses, reducing the number of fuses allows for an increase in the spacing between the fuses, thus reducing the likelihood of an error if the fuse is blown. Further, the elimination of such conductive elements reduces the resistance of the bit line path, and thus reduces the access time of the memory cell.

During the second test mode, which occurs after the selected redundant memory column is mapped to the address of the defective matrix column, CRS_ is inactive logic 1,
Therefore, only the mapped redundant columns are accessed simultaneously with the matrix columns. Therefore, if redundant column 0 is mapped to replace the defective matrix column, RCOL0_ transitions to active logic 0 and redundant column 0 is set as described earlier in the description of the operation of redundant column select circuit 158. Select Similarly, if redundant column 0 is not mapped, RCOL0_ will remain at inactive logic 1, and redundant column 0 will not be selected.

FIG. 9 shows the wafer test mode circuit 38 of FIG.
FIG. 3 is a schematic diagram of a wafer test mode power circuit 180 of FIG. The circuit 180 may store the memory 10 before the die on which the memory 10 is formed is scribed from a wafer (not shown).
To be able to test Signal WTM0 or WT
If any of M1 is logic zero, circuit 180 generates an active logic zero for signal WFRB_. Circuit 18
0 further includes U.S. patent application Ser. No. 08 / 710,357;
"Integrated Circuit Supporting Wafer Level Test and Method Thereof (INTEGRATED CIRCUIT THA)"
T SUPPORTS AND METHOD FOR
WAFER-LEVEL TESTING) ", 19
Filed September 17, 1996 and US patent application Ser. No. 08/71.
No. 0,356, "Integrated Circuit Dies Suitable for Wafer Level Testing and Methods of Manufacturing Same
CUIT DIE SUITABLE FOR WAF
ER-LEVEL TESTING AND METH
OD FOR FORMING THE SAME) "
These applications are described in the September 17, 1996 applications, which are incorporated herein by reference.

FIG. 10 shows the logic circuit 2 of the control circuit 36 shown in FIG.
FIG. Circuit 250 generates signals CRS and CRS_ of FIGS. 4b and 8. The operation will be described. During the first test mode, WFRB_ (FIG. 9)
Is active logic zero and signal FON (FIG. 11) is active logic one, NAND gate 252 produces a logic zero at its output. First inverter 254
Generates an active logic one for CRS and the second inverter 256 generates an active logic zero for CRS_.
During the second test mode, WFRB_ is inactive logic 1
And FON is at inactive logic 0, circuit 250 generates an inactive logic 0 to CRS and
Generate an inactive logic 1 for S_.

FIG. 11 is a schematic diagram of the test mode logic circuit 258 of the control circuit 36 of FIG. The circuit 258 generates a FON (FIG. 1) from the test mode signals TM0 to TM2, the wafer test mode signals WTM0 to WTM1, and WFRB_.
0) and other signals. Circuit 258 is further described in U.S. patent application Ser. No. 08 / 587,708, entitled "Device and Method for Driving Conduction Paths With Signals (DEVICE AND
METHOD FORDRIVING A COND
UCTIVE PATH WITH A SIGNA
L) ", filed January 19, 1996, U.S. Patent Application No. 0
No. 8 / 588,762 "Data input device (DAT for generating test signals on bit lines and bit complement lines)
A-INPUT DEVICE FOR GENERA
TING TEST SIGNALS ON BIT
AND BIT-COMPLEMENT LINE
S), filed January 19, 1996, US Patent Application No. 0
No. 8 / 589,141, “Write Driver Having Test Function (WRITE DRIVERHAVING AT)
EST FUNCTION), filed Jan. 19, 1996, U.S. patent application Ser. No. 08 / 589,140, entitled "MEMORY-ROW Selector with Test Function".
SELECTOR HAVING A TESTFU
No. 08 / 588,740, filed Jan. 19, 1996, entitled "Device and Method for Separating Bit Lines from Data Lines (DEVICE)."
AND METHOD FOR ISOLATING
BITLINES FROM A DATA LIN
E), filed Jan. 19, 1996, and U.S. patent application Ser.
D CIRCUIT AND METHOD FOR
CONTROLLLING A SENSE AMPLI
FIER) ", filed January 19, 1996, which are incorporated herein by reference.

FIG. 12 is a schematic diagram of one embodiment of the redundant row decoder 260 of the redundant row decode and secret circuit 28 of FIG. In one embodiment, memory 10 has four redundant rows and circuit 28 has two circuits 260, one for each pair of the four redundant rows. Redundant row decoder 260 has a decoder 262a associated with redundant row 0 and has a decoder 262b associated with redundant row 1. Remaining redundant row decoder 26
0 is associated with redundant rows 3 and 4. For simplicity,
Although decoder 262a is described in detail, it should be understood that decoder 262b is configured and operates in a similar manner.

The decoder 262a includes an enable circuit 264
a and a select circuit 266a. If redundant row 0 is mapped to the address of the defective matrix row, enable circuit 264a enables select circuit 266a to activate redundant row 0 when the defective matrix row is addressed. Enable circuit 264a has a selective conducting element 268a, which is rendered conductive if redundant row 0 is not mapped to replace a defective matrix row, and redundant row 0 is so mapped. If it is, it is brought into a non-conductive state. Circuit 264a further includes N
MOS transistor 270a, NMOS transistor 2
Latch 272 including 74a and inverter 276a
a, and an inverter 278a.

Select circuit 266a includes eight pass gates or switches 280a that receive row address true signals Rat ₁ -Rat ₈ (only one is shown for simplicity).
And the row address complement signals Rac ₁ -Rac
_{It has eight} switches 282a (only one is shown for simplicity) receiving eight. The eight selective conducting elements 284a (only one is shown for simplicity)
Each coupled in series between a corresponding one of the one and the node NFA ₁ -NFA ₈ a corresponding one of the switch 280a. Eight selective conduction element 286a (only shown one for simplicity) is serially coupled between the corresponding one of the one and the node NFA ₁ -NFA ₈ a corresponding one of the switches 282a ing. Eight switches 287a (only one is shown for simplicity)
Each coupled between a corresponding one and Vss of has a control terminal coupled to the output terminal of the inverter 278a, and node NFA ₁ -NFA _8.
Nodes NFA ₁ -NFA ₃ are coupled to respective inputs of NAND gate 288a and nodes NFA ₄ -NFA ₃
NFA ₆ is coupled to the respective input of NAND gate 290a, and nodes NFA ₇ -NFA ₈ are connected to N
It is coupled to a respective input of AND gate 292a. The outputs of NAND gates 288a, 290a, 292a are coupled to respective inputs of NOR gate 294a, the output of which is coupled to the input of NOR gate 296a. NOR gate 296a generates an active low redundant row 0 select signal RRWDC-0_. NOR
The second input of gate 296a is coupled to receive CRS (FIG. 10).

In operation, during a read or write cycle, if redundant row 0 is not mapped to replace a defective matrix row, element 26
8a is conductive and CRS is inactive logic zero. Inverters 276a and 278a each have logic 0
And a logic 1 to deactivate switch 280a and activate switch 287a. These active switches are connected to NAND gates 288a, 290a, 292a.
Is driven to logic zero. NAND gate 288
a, 290a, 292a generate a logic zero at their outputs, thus causing NOR gate 294a to drive a logic zero.
Output. RRWDC-0_ is an inactive logic one because both the CRS and the output of NOR gate 294a are logic zeros. Therefore, circuit 262a does not select redundant row 0.

In operation, during a read or write cycle, if redundant row 0 is not mapped to replace a defective matrix row, element 26
8a is non-conductive and CRS is inactive logic zero. Inverters 276a and 278a generate a logic one and a logic zero, respectively, to activate switch 280a and deactivate switch 287a. Element 284
appropriate ones of a and 286a are non-conductive, thus if the value of the Rat ₁ -Rat ₈ and Rac ₁ -Rac ₈ corresponds to the defective matrix row, NAND gate 2
88a, 290a, 292a receive a logic one at each of their inputs. For example, if the defect matrix row is R
at ₁ -Rat ₈ are all equal to logic 1 and Rac _1-
If all of Rac ₈ correspond to a logical zero, then all eight elements 284a are conductive and all eight elements 286a are non-conductive. Thus, when a defective row is addressed, NAND gate 288
a, 290a, 292a receive a logic one at all of their inputs and generate a logic zero at their outputs, and RRWDC-0 is an active logic zero to select redundant row zero.

During the first test mode, as described above with reference to FIGS. 4b, 7, and 8, all matrix rows and redundant rows, whether mapped or not, are accessed simultaneously and the CRS Is active logic one, which forces the output of NOR gate 296a to logic zero.
Therefore, RRWDC-0_ is active logic 0, regardless of whether redundant row 0 is mapped.

During the second test mode, when all the matrix rows and the mapped redundant rows except the unmapped redundant rows are selected simultaneously, the CRS is at inactive logic 0; And the signal Rat ₁
-Rat ₈ and Rac ₁ -Rac ₈ are all logical ones. Since both Rat ₁ -Rat ₈ and Rac ₁ -Rac ₈ are logical 1, if redundant row 0 is mapped to any defective matrix row, circuit 262
a operates as described above to select redundant row 0.

FIG. 13 is a schematic diagram of a multiplexer circuit 300, which is similar to the redundant switch control circuit 164 (FIG. 8), and for other applications in the memory 10 or where a multiplexer is required. It can be used in other circuits. Multiplexer 300 includes k input terminals for receiving input signals IN ₀ -IN _k−1, and k selective conductive elements F each coupled between a corresponding input terminal and node 302.
₀ -F _k-1, is coupled between node 302 for example and selective conduction pulldown element F _p which is coupled between a reference voltage, such as Vss, the node 302 and the output terminal 305 inverter 304.

During operation, if none of the plurality of multiplexers 300 are used in parallel, all the elements F ₀ -F _k-1 and F _p of the multiplexers 300 are non-conductive. And IN ₀ -IN _k-1 are each at the same logic level, in this case a logic 0, so that no signal collision occurs at node 302. That is, each of the input signals IN ₀ -IN _k-1 and Vss drives node 302 to the same logic level, rather than to a different logic level. In another embodiment of the present invention, the element F _p is coupled to Vcc, and the signal IN ₀ -I
N _k-1 is a logical one. On the other hand, it is possible to make all of the elements F ₀ -F _k-1 non-conductive and to make the element F _p conductive, or to make the elements F ₀ -F _k-1 conductive and the element F F _p is made non-conductive, and IN ₀ -IN _k-1
At the same logic level.

During operation, at least one of the multiplexers 300 connected in parallel receives the input signal IN.
_When used to couple a selected _one of the _0- IN _k-1 to output 305, all elements F ₀ -F _k-1 of the used multiplexer 300 are selected. Except for elements coupled to the input signal, they are non-conductive. F _p of the multiplexer 300 which is also used in a non-conductive state. For example, the used multiplexer 300
There if one desires to bind IN ₀ to the output 305, all of the elements F ₁ -F _k-1 and F _p is a non-conducting state, and F ₀ is conductive. Therefore, only the selected signal IN ₀ propagates to the output terminal 305. For each of the unused multiplexers 300 in parallel, all elements F ₀ -F _k-1
Is turned off, and the element _Fp is turned on.

An advantage of multiplexer 300 is that it has fewer parts than a similar conventional multiplexer. For example, multiplexer 300 does not require components such as transistors to separate the input signal from node 302.
Reductions in such components are often due to the memory device 1
The operation of multiplexer 300 is increased because it reduces the overall layout area of zeros and there is no transistor or gate delay.

FIG. 14 is a block diagram of a computer system 306 incorporating the memory 10 of FIGS.
Computer system 306 includes computer circuitry 308 for performing computer functions such as, for example, execution software for performing desired calculations and tasks. Circuit 308 typically includes processor 31
0 and the memory 10 coupled to the processor 310. One or more input devices 312, such as a keypad or mouse, for example,
To allow an operator (not shown) to manually enter data. One or more output devices 314 provide data generated by computer circuitry 308 to an operator. Examples of such output devices 314 include video displays such as printers and cathode ray tube (CRT) displays.
One or more data storage devices 316 are coupled to computer circuitry 308 for recording data on and retrieving data from external storage media (not shown). Examples of the data storage device 316 and the corresponding storage medium include a drive for receiving a hard disk and a floppy disk, a tape cassette, and a compact disk read only memory (CD-ROM). Typically, the computer circuits 308 each have a memory 1
It includes an address, data and control bus coupled to a zero address, data and control bus.

Although the specific embodiments of the present invention have been described in detail above, the present invention should not be limited to these specific examples, but may be variously modified without departing from the technical scope of the present invention. Of course is possible.

[Brief description of the drawings]

FIG. 1a is a schematic diagram illustrating a portion of an integrated memory circuit according to the present invention.

FIG. 1b is a schematic diagram showing a part of an integrated memory circuit according to the present invention.

FIG. 2 is a schematic diagram showing one embodiment of the memory circuit of FIG. 1;

FIG. 3 is a schematic diagram showing a memory block of the memory circuit of FIG. 1;

FIG. 4A is a schematic diagram showing one embodiment of a redundant column decoder of the redundant column selection circuit of FIG. 2;

FIG. 4b is a schematic diagram illustrating the redundant address signal generator of FIG. 4a.

FIG. 5 is a schematic diagram showing a first embodiment of a memory column selection circuit of the matrix column selection circuit of FIG. 2;

FIG. 6 is a schematic diagram showing a first embodiment of a redundant column selecting circuit of the redundant column decoding and selecting circuit of FIG. 2;

FIG. 7 is a schematic diagram showing a second embodiment of the memory column selection circuit of the matrix column selection circuit of FIG. 2;

FIG. 8 is a schematic diagram showing a second embodiment of the redundant column selecting circuit of the redundant column decoding and selecting circuit of FIG. 2;

FIG. 9 is a schematic diagram showing one embodiment of a part of the wafer test mode circuit of FIG. 2;

FIG. 10 is a schematic diagram showing one embodiment of a first portion of the control circuit of FIG. 2;

11 is a schematic diagram illustrating one embodiment of a test mode logic circuit forming the second part of the control circuit of FIG. 2;

FIG. 12 is a schematic diagram showing one embodiment of a redundant column decoding and selecting circuit of FIG. 2;

FIG. 13 is a schematic diagram showing a multiplexer circuit according to the present invention.

FIG. 14 is a schematic block diagram showing a computer system incorporating the memory circuits of FIGS. 1 and 2;

[Explanation of symbols]

 Reference Signs List 10 memory device (circuit) 12 master word line decoder 14 address decoder 16 row and column selection circuit 18 matrix row selection circuit 20 matrix memory array 21 memory array 22 matrix column selection circuit 24 read / write circuit 26 redundant memory row 28 redundant row Decoding and selecting circuit 30 Redundant column decoding and selecting circuit 32 Redundant memory column 34 Input / output (I / O) buffer 36 Control circuit 38 Wafer test mode circuit

Claims (24)

[Claims] 1. A memory access circuit for separating a matrix memory cell from a data line and coupling a redundant memory cell to a data line when a matrix memory cell having an address is defective, wherein the matrix memory cell and the data line A matrix switch coupled to the matrix switch; a matrix switch control circuit coupled to the matrix switch and operable to open the matrix switch if the matrix memory cell is defective; A redundant switch coupled between the redundant switch and the data line, coupled to receive a redundant address signal, coupled to the redundant switch, and responsive to a first value of the redundant address signal. A redundant switch control circuit operable to close the switch, Memory access circuit, characterized in that it comprises. 2. The matrix switch control circuit of claim 1, wherein said matrix switch control circuit is further coupled to receive a matrix address signal, said matrix switch control circuit comprising: A memory access circuit operable to close the matrix switch when has a value equal to the address of the matrix memory cell. 3. The apparatus of claim 1, further comprising a redundant signal generator coupled to receive a matrix address signal, wherein said redundant signal generator is provided when said matrix memory cells are defective and Operable to generate the redundant address signal with the first value when the matrix address signal has a value equal to the address of the matrix memory cell, wherein the redundant signal generator is Operable to generate the redundant address signal having a second value when the memory cell is functional, wherein the redundant switch control circuit is responsive to the second value of the redundant address signal to generate the redundant switch signal. A memory access circuit operable to open the memory. 4. The method of claim 1, further comprising: the redundant switch having a control terminal and operable to open when the redundant address signal has a second value.
The redundant switch control circuit is coupled to receive a redundant disable signal having the second value, and the redundant switch control circuit is coupled between the redundant disable signal and the control terminal of the redundant switch. And a second programmable element coupled between the redundant address signal and the control terminal of the redundant switch, wherein the redundant switch control circuit includes the redundant switch control circuit. When the enable signal has the second value and the first element is conductive and the redundant address signal has the second value and the second element is conductive. Operable to open the redundant switch in some cases, a redundant signal generator being coupled to receive the matrix address signal, A redundant signal generator configured to generate the redundant address signal having the first value when the matrix memory cell is defective and the matrix address signal has a value equal to the address of the matrix memory cell; Operable to generate, the redundant signal generator generates the second value when both the first and second selectively conductive elements are conductive and the matrix memory cell is functional. A memory access circuit operable to generate the redundant address signal having the following. 5. The matrix switch control circuit of claim 1, wherein said matrix switch control circuit has an input coupled to receive an initialization signal and a latch having an output coupled to said matrix switch. Wherein the matrix switch control circuit is operable to set the latch to a first value in response to the initialization signal if the matrix memory cell is defective, wherein the first value is the matrix switch. A memory access circuit characterized in that a memory access circuit is opened. 6. A memory selection circuit that accesses the matrix memory cell when the matrix memory cell is operable and accesses a redundant memory cell instead of the matrix memory cell when the matrix memory cell is inoperable. A matrix pass gate comprising first and second supply nodes, a data path, a control terminal, and coupled between the matrix memory cell and the data path; a control terminal; A redundant passgate coupled between a redundant memory cell and the data path, a matrix address input terminal, an output terminal coupled to the control terminal of the matrix passgate, and coupled to the first supply node. Gate controller comprising a first supply terminal and a second supply terminal A first selective conducting element having a first terminal coupled to the second supply terminal of the matrix gate controller and having a second terminal coupled to the second supply node; a redundant address; A second selective conducting element having an input terminal and having an output terminal coupled to the control gate of the redundant passgate. 7. The memory selection circuit according to claim 6, wherein said data path is a read line. 8. The memory selection circuit according to claim 6, wherein said data path is a write line. 9. The memory selection circuit according to claim 6, wherein each of said matrix and said redundant pass gate has a MOS transistor. 10. The apparatus according to claim 6, further comprising an initialization switch coupled between said first power supply node and said control terminal of said matrix pass gate, wherein said initialization switch is initialized. A memory selection circuit comprising a control terminal coupled to receive a signal. 11. The third selection of claim 6, further comprising an input terminal coupled to receive a disable signal, and a control terminal coupled to the control terminal of the redundant passgate. A memory selection circuit having a static conduction element. 12. The memory selection circuit according to claim 6, wherein each of said first and second selective conducting elements has a fuse element. 13. The memory selection circuit according to claim 6, further comprising a latch having a latch terminal coupled to said control terminal of said matrix pass gate. 14. A memory device, comprising: a first and a second power supply terminals; an address decoder operable to generate a plurality of matrix column selection signals; a data read line, a data write line, and a matrix column. An array of a plurality of matrix memory cells, each matrix memory cell in a matrix column being coupled to a corresponding matrix bit line, arranged in the form of a redundant column, each redundant memory cell in a redundant column An array of a plurality of redundant memory cells coupled to a corresponding redundant bit line; a matrix column selection circuit coupled to an array of the address decoder and the matrix memory cells; A control terminal is provided for each matrix column composed of cells, and the matrix bit line and the data A first switch coupled between the matrix bit line and the data write line; a second switch having a control terminal and coupled between the matrix bit line and the data write line; An input terminal coupled to receive one of the select signals; an output terminal coupled to the control terminal of the first and second switches; a first power supply node coupled to the first power supply terminal A matrix controller comprising a second power supply node; a first terminal coupled to the second power supply node of the matrix controller; and a second terminal coupled to the second power supply terminal. A matrix column selection circuit comprising: a first element having a selectable conductivity; and a redundant column circuit, wherein the matrix comprises: A redundant decoder having an input terminal coupled to receive one of the column select signals and having an output terminal; and a redundant decoder having a control terminal and between the redundant bit line and the data read line. A fourth switch having a control terminal and coupled between the redundant bit line and the data write line; and a fourth switch coupled to the output terminal of the redundant decoder. A second element having selective conductivity having an input terminal connected to the control terminal of the third and fourth switches and an output terminal coupled to the control terminal of the third and fourth switches. A memory device characterized by the above-mentioned. 15. The matrix controller of claim 14, wherein the matrix controller comprises: a gate coupled to the input terminal of the matrix controller; a source coupled to the first power supply node;
A first type MOS transistor having a drain coupled to the output terminal of the matrix controller, a gate coupled to the input terminal of the matrix controller, and coupled to the second power supply node Source and
A second type MOS transistor comprising: a drain coupled to the output terminal of the matrix controller;
A memory device comprising: 16. The method of claim 14, wherein the matrix column selection circuit further comprises: a drain coupled to the control terminal of the first and second switches; and one of the first and second power terminals. A MOS transistor having a source and a gate coupled to one another, an inverter having an input terminal coupled to the drain of the transistor, and having an output terminal coupled to the gate of the transistor; A memory device comprising: 17. The device of claim 14, wherein the matrix column selection circuit further comprises: a drain coupled to the control terminal of the first and second switches; and one of the first and second power terminals. A first MO having a source coupled to one and a gate
An S-transistor; an inverter having an input terminal coupled to the drain of the transistor and having an output terminal coupled to the gate of the transistor; an inverter coupled to the control terminal of the first and second switches. And a second MOS transistor having a drain coupled to a source coupled to one of the first and second power terminals, and a gate coupled to receive an initialization signal. Characteristic memory device. 18. The apparatus of claim 14, further comprising a control circuit operable to generate a redundant disable signal on an output terminal, wherein the redundant column circuit has a selectable conductivity. And a third element having a first terminal coupled to the output terminal of the control circuit and having a second terminal coupled to the control terminal of the third and fourth switches. A memory device. 19. A computer system, comprising: a data input device, a data output device, an arithmetic circuit coupled between the data input device and the data output device and having a memory device,
The memory device includes: first and second power terminals; an address decoder operable to generate a plurality of matrix column selection signals; a data read line; a data write line; An array of a plurality of matrix memory cells, each matrix memory cell in a matrix column being coupled to a corresponding matrix bit line, and an array of redundant memory cells arranged in a redundant column form. An operation circuit having an array of a plurality of redundant memory cells in which memory cells are coupled to corresponding redundant bit lines; an operation circuit coupled to the address decoder and coupled to an array of the plurality of matrix memory cells And a control terminal for each matrix column including a plurality of memory cells. A first switch coupled between the matrix bit line and the data read line, and a first switch having a control terminal and coupled between the matrix bit line and the data write line. Two switches; an input terminal coupled to receive one of the matrix column select signals; an output terminal coupled to the control terminal of the first and second switches; coupled to the first power terminal. A first power supply node, a matrix switch controller having a second power supply node, and a first terminal coupled to the second power supply node of the matrix switch controller, and a second power supply terminal. A matrix column selection circuit comprising: a first element having a coupled second terminal and having selectable conductivity; A redundant decoder having an input terminal coupled to receive one of the matrix column select signals and having an output terminal, and a control terminal for each of the redundant columns of recells; A third switch coupled between a redundant bit line and the data read line; a fourth switch having a control terminal and coupled between the redundant bit line and the data write line; A second having an input terminal coupled to the output terminal of the redundant decoder and an output terminal coupled to the control terminal of the third and fourth switches and having a selectable conductivity; And a redundant column circuit comprising: 20. The apparatus of claim 19, further comprising a data storage device coupled to the arithmetic circuit, wherein the arithmetic circuit has a processor coupled to the memory device. And a computer system. 21. A method of mapping a redundant memory cell to an address of a defective memory cell, comprising: opening a first switch coupled between the defective memory cell and a first data path; A second switch coupled between the redundant memory cell and the data path is closed when is addressed. 22. The method according to claim 21, wherein said opening step programs a memory cell selection circuit to generate a signal level at a control terminal of said first switch. 23. The method of claim 21, wherein the opening step blows a fuse to program a memory cell select circuit to generate a signal level at a control terminal of the first switch. . 24. The redundant memory cell according to claim 21, further comprising: generating a redundant cell selection signal for closing the second switch when the defective memory cell is addressed. Blowing the fuse to disengage the select signal from a third switch coupled between the fuses.