JP3618495B2 - Semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device and a system, for example, a synchronous DRAM (random access memory), a computer including the same, and a technique particularly effective when used for speeding up and stabilizing the operation thereof.
[0002]
[Prior art]
There is a so-called synchronous DRAM that includes a plurality of banks and operates synchronously according to a predetermined clock signal. The synchronous DRAM includes a clock buffer that receives the clock signal and forms a predetermined internal clock signal.
[0003]
[Problems to be solved by the invention]
Prior to the present invention, the inventors of the present application developed a synchronous DRAM having a clock buffer CB as shown in FIG. 9, and faced the following problems. That is, in this synchronous DRAM, the clock signal CLK input via the external terminal CLK passes through the input circuit IC3 of the clock buffer CB, and is then logically connected to the substantial clock enable signal CKE at the NAND gate NAND4. The product is taken. An output signal of the NAND gate NA4 is a CMOS (complementary) composed of a P-channel MOSFET (metal oxide semiconductor field effect transistor. In this specification, the MOSFET is a generic name for an insulated gate field effect transistor) P2 and an N-channel MOSFET N3. Type MOS) is supplied to a one-shot pulse generation circuit PG via an inverter VC. The output signal of the pulse generation circuit PG passes through a CMOS inverter V4 composed of a P-channel MOSFET P3 and an N-channel MOSFET N4, and then passes through similar inverters VE and VF and VG to VI, and inverted internal clock signals CK1B to CK3B (here, A so-called inversion signal or the like that is selectively set to the low level when it is effective is indicated by adding B to the end of the name (the same applies hereinafter).
[0004]
In other words, in this clock buffer CB, the output signals of the NAND gate NA4 and the pulse generation circuit PG are transmitted via the CMOS type inverters VC and VD and distributed to each part of the synchronous DRAM. The gate capacitances of two MOSFETs P2 and N3 or P3 and N4 formed with a relatively large size so as to have a predetermined driving capability are always coupled to the output node of the pulse generation circuit PG. As a result, the delay time of the inverted internal clock signals CK1B to CK3B with respect to the clock signal CLK is increased, and the clock access time of the synchronous DRAM is delayed. In order to cope with this, if the size of the MOSFETs constituting the inverters VC to VI is reduced to reduce the gate capacity thereof, the drive capacity of the inverter decreases and the number of required logic stages of the clock buffer CB increases. However, the access time is not increased.
[0005]
An object of the present invention is to realize a one-shot pulse generation circuit that reduces the delay time while reducing the number of required logic stages. Another object of the present invention is to speed up and stabilize the operation of a synchronous DRAM including a one-shot pulse generation circuit and a computer system including the same.
[0006]
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
[0007]
[Means for Solving the Problems]
The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows. That is, in a synchronous DRAM or the like that operates synchronously according to a clock signal, a clock buffer one-shot pulse generation circuit includes an N-channel first MOSFET that receives an input clock signal, a power supply voltage of the circuit, and a drain of the first MOSFET. A second P-channel type MOSFET that receives a substantial delay signal of the internal pulse signal at the drain of the first MOSFET at its gate, a source of the first MOSFET, and a ground potential of the circuit An N-channel third MOSFET that is provided in between and receives a substantial delay signal of the internal pulse signal at its gate is basically configured. When the pulse width of the input clock signal is on the maximum value side, a set that receives a substantial input clock signal at its inverted set input terminal and a substantial inverted delay signal of the internal pulse signal at its inverted reset input terminal A reset flip-flop is provided to supply a substantially non-inverted output signal to the gates of the second and third MOSFETs.
[0008]
According to the above means, the configuration of the one-shot pulse generation circuit which is the center of the clock buffer can be simplified, the input capacitance is only the gate capacitance of the first MOSFET, and the driving capability is increased correspondingly, thereby making the one-shot pulse. The number of required logic stages in the clock transmission path of the pulse generation circuit can be reduced. Further, even when the pulse width of the input clock signal is on the maximum value side, a stable internal clock signal is generated without generating an erroneous pulse, and the operation and speed of the operation of the synchronous DRAM and the computer system including the same are increased. Can be achieved.
[0009]
DETAILED DESCRIPTION OF THE INVENTION
FIG. 1 is a block diagram showing an embodiment of a synchronous DRAM to which the present invention is applied. First, the outline of the configuration and operation of the synchronous DRAM of this embodiment will be described with reference to FIG. The circuit elements constituting each block in FIG. 1 are not particularly limited, but are formed on a single semiconductor substrate such as single crystal silicon by a known MOSFET integrated circuit manufacturing technique.
[0010]
In FIG. 1, the synchronous DRAM of this embodiment includes a pair of banks BNK0 and BNK1, each of which is a memory array MARY arranged to occupy most of the layout area and a direct peripheral circuit. A row address decoder RD, a sense amplifier SA, a column address decoder CD, a write amplifier WA, and a main amplifier MA are provided.
[0011]
The memory arrays MARY constituting the banks BNK0 and BNK1 each include a predetermined number of word lines arranged in parallel in the vertical direction in the drawing and a predetermined set of complementary bit lines arranged in parallel in the horizontal direction. At the intersections of these word lines and complementary bit lines, a large number of dynamic memory cells comprising information storage capacitors and address selection MOSFETs are respectively arranged in a lattice pattern.
[0012]
The word lines constituting the memory arrays MARY of the banks BNK0 and BNK1 are coupled to the corresponding row address decoder RD, and are selectively set in the selected state. To these row address decoders RD, 11-bit internal address signals X0 to X10 excluding the most significant bit are commonly supplied from the row address register RA, and an internal control signal RG (not shown) is commonly supplied from the timing generation circuit TG. The Further, the X address signals AX0 to AX11 are supplied to the row address register RA via the address buffer AB, and the internal control signal RL is supplied from the timing generation circuit TG. Further, the X address signals AX0 to AX11 and the Y address signals AY0 to AY8 are supplied to the address buffer AB from an external access device via the address input terminals A0 to A11 in a time division manner.
[0013]
The address buffer AB takes in the X address signals AX0 to AX11 and the Y address signals AY0 to AY8 that are supplied in a time-sharing manner via the address input terminals A0 to A11, and receives the row address register RA, the column address counter CC, and the mode register MR. To communicate. The row address register RA takes in and holds the X address signals AX0 to AX11 transmitted from the address buffer AB according to the internal control signal RL, and forms the internal address signals X0 to X11 based on these X address signals. To do. Among them, the internal address signal X11 of the most significant bit is supplied to the bank selection circuit BS for bank selection, and the other internal address signals X0 to X10 are the row address decoders of the banks BNK0 and BNK1, as described above. Commonly supplied to RD.
[0014]
The bank selection circuit BS selectively sets the bank selection signal BS0 or BS1 to the high level in accordance with the internal address signal X11 of the most significant bit supplied from the row address register RA. These bank selection signals BS0 and BS1 are supplied to the banks BNK0 and BNK1, respectively, and selectively operate the row address decoder RD, the column address decoder CD, the sense amplifier SA, the write amplifier WA, the main amplifier MA, and the like which are peripheral circuits thereof. Served to make you.
[0015]
The row address decoders RD of the banks BNK0 and BNK1 are selectively activated by setting the internal control signal RG to the high level and the corresponding bank selection signal BS0 or BS1 to the high level, respectively. The internal address signals X0 to X10 supplied from are decoded, and the designated word line of the corresponding memory array MARY is alternatively selected.
[0016]
Next, the complementary bit lines constituting the memory array MARY of the banks BNK0 and BNK1 are coupled to the corresponding sense amplifier SA. The sense amplifier SA of each bank is supplied with a bit line selection signal of a predetermined bit (not shown) from the corresponding column address decoder CD, and is commonly supplied with an internal control signal PA (not shown) from the timing generation circuit TG. The column address decoder CD of each bank is commonly supplied with 9-bit internal address signals Y0 to Y8 from the column address counter CC, and is commonly supplied with an internal control signal CG (not shown) from the timing generation circuit TG. Further, Y address signals AY0 to AY8 are supplied to the column address counter CC via the address buffer AB, and an internal control signal CL is supplied from the timing generation circuit TG.
[0017]
The column address counter CC includes a binary counter that performs a stepping operation according to an internal control signal (not shown). This counter takes in and holds Y address signals AY0 to AY8 supplied via the address buffer AB in accordance with the internal control signal CL. Further, stepping operation is performed using these Y address signals AY0 to AY8 as initial values, and internal address signals Y0 to Y8 are sequentially formed and supplied to the column address decoders CD of the banks BNK0 and BNK1. At this time, the column address decoder CD of each bank is selectively activated by setting the internal control signal CG to the high level and the corresponding bank selection signal BS0 or BS1 to the high level, and the internal address signal Y0. ... Y8 is decoded, and the corresponding bit of the bit line selection signal is alternatively set to the high level.
[0018]
When the mode register set command is executed, the mode register MR fetches and holds various mode data input via predetermined bits of the address input terminals A0 to A11 according to the internal control signal MS. Further, the mode data is decoded to determine the operation mode of the synchronous DRAM, and a mode control signal is selectively formed and supplied to each part of the synchronous DRAM.
[0019]
The sense amplifiers SA of the banks BNK0 and BNK1 include a predetermined number of unit circuits provided corresponding to the respective complementary bit lines of the memory array MARY, and each of these unit circuits is formed by cross-coupling a pair of CMOS inverters. A unit amplifier circuit and a pair of N-channel type switch MOSFETs are included. Among these, each unit amplifier circuit is selectively activated simultaneously when the internal control signal PA is set to the high level and the corresponding bank selection signal BS0 or BS1 is set to the high level. A minute read signal output via a corresponding complementary bit line from a predetermined number of memory cells coupled to the selected word line is amplified to be a high level or low level binary read signal.
[0020]
On the other hand, the switch MOSFET pairs of each unit circuit are selectively turned on by eight groups in response to the high level of the corresponding bit line selection signal, and the corresponding eight complementary bit lines and complementary common data lines of the memory array MARY. CD0 * to CD7 * (Here, for example, the non-inverted common data line CD0T and the inverted common data line CD0B are collectively indicated by * as a complementary common data line CD0 *. This is also effective. A so-called non-inverted signal or the like that is selectively set to a high level is indicated by adding a T to the end of the name, and so on.
[0021]
The complementary common data lines CD0 * to CD7 * are respectively coupled to the output terminals of the respective unit circuits of the corresponding write amplifier WA, and are coupled to the input terminals of the respective unit circuits of the corresponding main amplifier MA.
[0022]
The write amplifier WA and the main amplifier MA each include eight unit circuits provided corresponding to the complementary common data lines CD0 * to CD7 *. Among these, the input terminal of each unit circuit of the write amplifier WA is coupled to the output terminal of the corresponding unit circuit of the data input buffer IB via the write data buses WDB0 to WDB7, and the output of each unit circuit of the main amplifier MA. The terminals are respectively coupled to the input terminals of the corresponding unit circuits of the data output buffer OB via read data buses RDB0 to RDB7. The input terminal of each unit circuit of the data input buffer IB and the output terminal of each unit circuit of the data output buffer OB are commonly coupled to the corresponding data input / output terminals D0 to D7. An internal control signal WP is commonly supplied from the timing generation circuit TG to each unit circuit of the write amplifier WA, and an internal control signal OC is commonly supplied to each unit circuit of the data output buffer OB.
[0023]
Each unit circuit of the data input buffer IB takes in 8-bit write data inputted from the previous access device via the data input / output terminals D0 to D7 when the synchronous DRAM is selected in the write mode. The data is held and transmitted to the corresponding unit circuit of the write amplifier WA via the write data buses WDB0 to WDB7. At this time, each unit circuit of the write amplifier WA is selectively activated by setting the internal control signal WP to the high level and the corresponding bank selection signal BS0 or BS1 to the high level, and the data input buffer IB After the write data transmitted from each unit circuit via the write data buses WDB0 to WDB7 is converted into a predetermined complementary write signal, the bank BNK0 or BNK1 designated via the complementary common data lines CD0 * to CD7 * is converted. Write to eight selected memory cells of the memory array MARY.
[0024]
On the other hand, the unit circuits of the main amplifiers MA of the banks BNK0 and BNK1 are selectively activated when the internal control signal RP (not shown) is set to high level and the corresponding bank selection signal BS0 or BS1 is set to high level. The read signals output from the selected eight memory cells of the corresponding memory array MARY via the complementary common data lines CD0 * to CD7 * are amplified, and data is output via the read data buses RDB0 to RDB7. This is transmitted to the corresponding unit circuit of the buffer OB. At this time, each unit circuit of the data output buffer OB is selectively activated in response to the high level of the internal control signal OC, and the read data buses RDB0 to RDB0 are read from the corresponding unit circuit of the main amplifier MA of the bank BNK0 or BNK1. Read data transmitted via the RDB 7 is output from the corresponding data input / output terminals D0 to D7 to an external access device.
[0025]
The clock buffer CB forms predetermined inverted internal clock signals CK1B to CK3B based on the clock signal CLK and the clock enable signal CKE supplied from the previous stage access device, and supplies them to each part of the synchronous DRAM. The specific configuration of the clock buffer CB will be described later in detail.
[0026]
The timing generation circuit TG is based on the chip selection signal CSB, the row address strobe signal RASB, the column address strobe signal CASB, the write enable signal WEB, and the input / output mask signal DQM supplied as activation control signals from the previous stage access device. Various internal control signals and the like are selectively formed and supplied to each part of the synchronous DRAM. The inverted internal clock signal CK1B is supplied from the clock buffer CB to the timing generation circuit TG.
[0027]
FIG. 2 shows a circuit diagram of a first embodiment of the clock buffer CB included in the synchronous DRAM of FIG. 3 shows a signal waveform diagram of an embodiment when the clock pulse width of the clock buffer CB of FIG. 2 is minimum, and FIG. 4 shows a signal waveform diagram of the embodiment when the clock pulse width is maximum. It is shown. Based on these drawings, the specific configuration and operation of the clock buffer CB of this embodiment and its features will be described. In the following circuit diagrams, MOSFETs with an arrow attached to the channel (back gate) portion are P-channel type, and are distinguished from N-channel MOSFETs without an arrow.
[0028]
In FIG. 2, the clock buffer CB of this embodiment includes two input circuits IC1 to IC2, one one-shot pulse generation circuit PG, and three inverters V6 to V8, although not particularly limited. Among these, the input circuits IC1 to IC2 include a predetermined input protection circuit. The pulse generation circuit PG includes a substantial inverter V1 centered on an N-channel (first conductivity type) MOSFET N1 (first MOSFET) and a two-input NAND gate NA1. The drain of the MOSFET N1 constituting the inverter V1 is coupled to the power supply voltage (first power supply voltage) of the circuit via a P-channel type (second conductivity type) MOSFET P1 (second MOSFET). It is coupled to the ground potential (second power supply voltage) of the circuit via the channel MOSFET N2 (third MOSFET).
[0029]
A clock signal CLK, that is, ICLK, is supplied from the external terminal CLK to the gate of the MOSFET N1 that constitutes the inverter V1 via the input circuit IC1, and an internal pulse signal, that is, an inverted clock signal CKB at its drain is latched by inverters V2 and V3. After passing through the circuit and inverters V6 to V8, the internal clock signals CK1B to CK3B are obtained. These internal clock signals are classified for use, for example, for command control, address control and data input / output control, and are distributed to corresponding parts of the synchronous DRAM.
[0030]
One input terminal of the NAND gate NA1 of the pulse generation circuit PG is supplied with the output signal of the latch circuit composed of the inverters V2 and V3, that is, the inverted delay signal of the internal pulse signal CK by the delay circuit DL and the inverter V4, and the other input. The terminal is supplied with a clock enable signal CKE, that is, ICKE, from the external terminal CKE via the input circuit IC2. Further, the output signal of the NAND gate NA1 is inverted by the inverter V5 to become an internal pulse signal ECK, which is supplied to the gates of the MOSFETs P1 and N2 constituting the inverter V1.
[0031]
Here, the clock signal CLK has a pulse width t. _CKH Is the minimum value, that is, t _{CKH = MIN} As shown in FIG. 3, for example, the period t _CK Is 20 ns (nanoseconds) and its pulse width t _CKH Is a pulse signal with a relatively small duty of 3 ns. In the pulse generation circuit PG, both the MOSFETs N1 and N2 are turned on in response to the high level of the internal pulse signal ECK and the rising of the input clock signal CLK to the high level, and the inverted internal pulse signal CKB changes to the low level. In response to the low level of the inverted internal pulse signal CKB, the internal pulse signal CK becomes high level, and when the delay time td of the delay circuit DL elapses after the internal pulse signal CK is set to high level, the output signal of the inverter V4 That is, the inverted internal pulse signal DCKB changes from the high level to the low level.
[0032]
As a result, the output signal of the NAND gate NA1 becomes high level, and in response to the high level of the output signal of the NAND gate NA1, the output signal of the inverter V5, that is, the internal pulse signal ECK becomes low level. Further, in response to the low level of the internal pulse signal ECK, the MOSFET N2 of the inverter V1 is turned off, the MOSFET P1 is turned on, and the inverted internal pulse signal CKB becomes high level. Further, when the delay time td of the delay circuit DL elapses, the inverted internal pulse signal DCKB is returned to the high level, and then the internal pulse signal ECK is returned to the high level. Holds until high level. As a result, the internal clock signals CK1B to CK3B output from the clock buffer CB have their periods set to the period t of the clock signal CLK. _CK And a predetermined pulse signal whose pulse width is approximately the delay time td of the delay circuit DL.
[0033]
In this embodiment, the clock signal CLK input via the input circuit IC1 is input only to the gate of one MOSFET N1 of the inverter V1 constituting the pulse generation circuit PG, and the load is only the gate capacitance of the MOSFET N1. . Therefore, the size of the MOSFET N1 can be increased at least twice as compared with a conventional synchronous DRAM using a CMOS inverter, so that the drive capability of the inverter V1 is increased and the number of required logic stages in the clock transmission path is reduced. be able to. As a result, the transmission delay time of the clock signal can be shortened and the operation of the synchronous DRAM can be speeded up.
[0034]
By the way, in this embodiment, the pulse width t of the clock signal CLK. _CKH Is the maximum value, that is, t _{CKH = MAX} When the internal pulse signal ECK is returned to the high level, the clock signal CLK is still in the high level state as illustrated in FIG. For this reason, the inverted internal pulse signal CKB becomes high level again, and an erroneous pulse such as a hatched line may occur, which may cause a malfunction.
[0035]
FIG. 5 shows a circuit diagram of a second embodiment of the clock buffer CB included in the synchronous DRAM of FIG. 6 shows a signal waveform diagram of an embodiment when the clock pulse width of the clock buffer CB of FIG. 5 is minimum, and FIG. 7 shows a signal waveform diagram of the embodiment when the clock pulse width is maximum. It is shown. Since this embodiment is an improvement of the embodiment shown in FIGS. 2 to 4 in order to eliminate the erroneous pulse, only the portions different from this will be described.
[0036]
In FIG. 5, the clock buffer CB of this embodiment includes a set-reset type flip-flop SRFF centered on a pair of NAND gates NA2 and NA3 which are cross-coupled. The first input terminal of the NAND gate NA2 becomes the inverted reset input terminal RB of the flip-flop SRFF, and the output signal of the latch circuit composed of the inverters V2 and V3, that is, the inverted delay signal of the internal pulse signal CK, that is, the inverted internal pulse signal DCKB is supplied. The The second input terminal of the NAND gate NA2 becomes the control terminal C of the flip-flop SRFF, and a clock enable signal CKE, that is, ICKE is supplied through the input circuit IC2. Further, the second input terminal of the NAND gate NA3 is coupled to the inverting set input terminal SB of the flip-flop SRFF via the two inverters V9 and VA. The inverting set input terminal SB is connected to the inverting set input terminal SB via the input circuit IC1. An input clock signal CLK is supplied. The output signal of the NAND gate NA2 passes through the inverter VB, becomes the non-inverted output signal Q of the flip-flop SRFF, and is supplied to the gates of the MOSFETs P1 and N2 constituting the inverter V1 as the internal pulse signal FCK.
[0037]
In this embodiment, the P-channel and N-channel MOSFETs that constitute the inverter V9 and whose gates are coupled to the inverting set input terminal SB of the set-reset type flip-flop SRFF are sufficiently smaller than the MOSFET N1 that constitutes the inverter V1. Formed in size. Therefore, the gate capacities of these MOSFETs are sufficiently smaller than that of MOSFET N1, and the increase in load due to the common coupling of inverting set input terminal SB of flip-flop SRFF to the transmission path of clock signal CLK is relatively small. It becomes.
[0038]
Pulse width t of clock signal CLK _CKH Is its minimum value t _{CKH = MAX} 6, the pulse generation circuit PG of the clock buffer CB, as shown in FIG. 6, inverts the internal pulse when the delay time td of the delay circuit DL elapses after the clock signal CLK is set to the high level. The signal DCKB is changed to a low level. At this time, the clock signal CLK is already returned to the low level, and the inverting set input terminal SB and the inverting reset input terminal RB are simultaneously at the effective level. However, since it is already in the set state, the flip-flop SRFF changes to the reset state in response to the low level of the inverted internal pulse signal DCKB. As a result, the non-inverted output signal Q of the flip-flop SRFF changes to the low level, the inverted internal pulse signal CKB becomes the high level, and the internal pulse signal CK, that is, the internal clock signals CK1B to CK3B are pulses having a predetermined pulse width td. Signal.
[0039]
When a predetermined time td elapses after the internal pulse signal CK is returned to the low level and the inverted internal pulse signal DCKB is returned to the high level, the flip-flop SRFF is set by receiving the low level of the clock signal CLK, that is, the inverted set input terminal SB. The output signal, that is, the internal pulse signal FCK becomes high level. As a result, the MOSFET P1 constituting the inverter V1 is turned off, the MOSFET N2 is turned on, and the pulse generation circuit PG can be prepared for the next rising edge of the clock signal CLK.
[0040]
Next, the pulse width t of the clock signal CLK _CKH Is its maximum value t _{CKH = MAX} 7, in the clock buffer CB, as shown in FIG. 7, the clock signal CLK is still at the high level when the inverted internal pulse signal DCKB is returned to the high level, and the set condition of the flip-flop SRFF is satisfied. do not do. Therefore, the flip-flop SRFF is kept in the reset state, the non-inverted output signal Q, that is, the internal pulse signal FCK is kept at the low level, and the inverted internal pulse signal CKB is never set to the low level again. As a result, the pulse width t of the clock signal CLK _CKH Is the maximum value t _{CKH = MAX} Even if it is on the side, the erroneous pulse as described above does not occur, and the malfunction of the synchronous DRAM can be prevented.
[0041]
Note that the flip-flop SRFF transitions to the set state when the clock signal CLK is set to the low level, and the non-inverted output signal Q, that is, the internal pulse signal FCK is changed to the high level. It can be prepared for the next rising edge of the signal CLK.
[0042]
FIG. 8 shows a system configuration diagram of an embodiment of a computer including a synchronous DRAM to which the present invention is applied. Based on this figure, the outline and features of the application system of the synchronous DRAM of this embodiment will be described.
[0043]
In FIG. 8, the computer of this embodiment has a so-called stored program type central processing unit CPU as its basic component. The central processing unit CPU is connected to a random access memory RAM such as a normal static RAM, a read only memory ROM such as a mask ROM, a display controller DPYC and a peripheral device controller PERC via a system bus SBUS. Is done. A frame memory FLM to which the synchronous DRAM of FIG. 1 is applied is coupled to the display control device DPYC, and a predetermined display device DPY is coupled to the display control device DPYC. In addition, a keyboard KBD and an external storage device EXM are coupled to the peripheral device controller PERC.
[0044]
The central processing unit CPU performs a step operation according to a program stored in advance in the read-only memory ROM, and controls and controls each part of the computer. The random access memory RAM is used as a cache memory or the like, and is used for temporarily storing and relaying a program, operation data, and the like transmitted from the read-only memory ROM to the central processing unit CPU, for example. Further, the display control device DPYC performs display control of the display device DPY based on the image data stored in the frame memory FLM, and the peripheral device controller PERC controls peripheral devices such as the keyboard KBD and the external storage device EXM. . The computer further includes a power supply device POWS that forms a predetermined stable DC power supply voltage based on an AC input power supply and supplies the power to each unit as an operation power supply.
[0045]
In this embodiment, the synchronous DRAM serving as the frame memory FLM includes the one-shot pulse generation circuit PG as described above, and this pulse generation circuit includes one N-channel MOSFET N1 that receives the substantial clock signal CLK. And a set-reset type flip-flop SRFF that receives a substantial clock signal CLK at its inverted set input terminal SB. Therefore, the number of required logic stages in the clock transmission path is reduced, the clock access time as a memory is increased, and the pulse width t of the clock signal CLK is increased. _CKH Is its maximum value t _{CKH = MAX} Even when it is on the side, the generation of erroneous pulses is suppressed, and the operation is stabilized. This speeds up and stabilizes the operation of the computer including the synchronous DRAM, that is, the frame memory FLM.
[0046]
The effects obtained from the above embodiments are as follows. That is,
(1) In a synchronous DRAM or the like that operates synchronously in accordance with a predetermined clock signal, a one-shot pulse generation circuit of a clock buffer includes an N-channel first MOSFET that receives an input clock signal, a power supply voltage of the circuit, and a first A P-channel type second MOSFET provided between the drain of the MOSFET and receiving at its gate a substantial delay signal of the internal pulse signal at the drain of the first MOSFET; and a source of the first MOSFET and a circuit ground A one-shot pulse generation circuit serving as the center of a clock buffer by basically configuring an N-channel third MOSFET that is provided between the potential and receives a substantial delay signal of the internal pulse signal at its gate. And the input capacitance of the first MOSFET is reduced. Only the preparative capacity, by increasing the correspondingly driving capability, there is an advantage that it reduces the required number of logic stages of the pulse generating circuit.
[0047]
(2) In the above item (1), when the pulse width of the input clock signal is on the maximum value side, a substantial input clock signal is received at its inverted set input terminal and the actual internal pulse signal is transmitted at its inverted reset input terminal. A set-reset type flip-flop that receives a typical inverted delay signal is provided, and the substantial non-inverted output signal is supplied to the gates of the second and third MOSFETs, so that the pulse width of the input clock signal is maximized. Even in this case, an effect that a stable internal clock signal can be generated without generating an erroneous pulse can be obtained.
(3) According to the above items (1) and (2), it is possible to obtain an effect that the operation of the synchronous DRAM and the computer system including the synchronous DRAM can be speeded up and stabilized.
[0048]
As mentioned above, the invention made by the present inventor has been specifically described based on the embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in FIG. 1, the synchronous DRAM can take an arbitrary bit configuration such as × 4 bits, × 16 bits, or × 32 bits, and can include an arbitrary number of banks. In addition, the memory arrays MARY of the banks BNK0 and BNK1 can include an arbitrary number of redundant elements, and can be divided into a plurality of mats including its direct peripheral circuit. Furthermore, the block configuration of the synchronous DRAM can take various embodiments, and the names and combinations of the start control signal and the internal control signal, their effective levels, and the like are not restricted by this embodiment.
[0049]
2 and 4, the specific configurations of the pulse generation circuit PG and the clock buffer CB adopt various embodiments as long as the same logic condition is obtained, and the polarity and absolute value of the power supply voltage and the conductivity type of the MOSFET. The same applies to. 3 and 4 and FIGS. 6 and 7, the effective levels of the clock signal CLK and each internal pulse signal, the specific time relationship thereof, and the like are not limited by these embodiments. In FIG. 8, the computer can include various other functional blocks, and the block configuration and bus configuration are arbitrary.
[0050]
In the above description, the case where the invention made mainly by the present inventor is applied to a synchronous DRAM as a field of use as a background and a computer including the same has been described, but the present invention is not limited thereto. The present invention can also be applied to various synchronous memories and logic integrated circuit devices including a similar clock buffer CB and various digital systems including these. The present invention can be widely applied to a semiconductor device including a one-shot pulse generation circuit in at least a clock transmission path and a device or system including such a semiconductor device.
[0051]
【The invention's effect】
The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows. That is, in a synchronous DRAM or the like that operates synchronously according to a clock signal, a clock buffer one-shot pulse generation circuit includes an N-channel first MOSFET that receives an input clock signal, a power supply voltage of the circuit, and a drain of the first MOSFET. A second P-channel type MOSFET that receives a substantial delay signal of the internal pulse signal at the drain of the first MOSFET at its gate, a source of the first MOSFET, and a ground potential of the circuit An N-channel third MOSFET that is provided in between and receives a substantial delay signal of the internal pulse signal at its gate is basically configured.
[0052]
When the pulse width of the input clock signal is on the maximum value side, a set that receives a substantial input clock signal at its inverted set input terminal and a substantial inverted delay signal of the internal pulse signal at its inverted reset input terminal A reset flip-flop is provided to supply a substantially non-inverted output signal to the gates of the second and third MOSFETs. As described above, the configuration of the one-shot pulse generation circuit serving as the center of the clock buffer can be simplified, the input capacitance is only the gate capacitance of the first MOSFET, and the driving capability is increased by that amount, so that the clock of the pulse generation circuit can be increased. It is possible to reduce the number of required logical stages in the transmission path. Further, even when the pulse width of the input clock signal is on the maximum value side, a stable internal clock signal is generated without generating an erroneous pulse, and the operation and speed of the operation of the synchronous DRAM and the computer system including the same are increased. Can be achieved.
[Brief description of the drawings]
FIG. 1 is a block diagram showing an embodiment of a synchronous DRAM to which the present invention is applied.
FIG. 2 is a circuit diagram showing a first embodiment of a clock buffer included in the synchronous DRAM of FIG. 1;
3 is a signal waveform diagram showing an embodiment when the clock pulse width of the clock buffer of FIG. 2 is minimum. FIG.
4 is a signal waveform diagram showing an embodiment when the clock pulse width of the clock buffer of FIG. 2 is maximum. FIG.
FIG. 5 is a circuit diagram showing a second embodiment of the clock buffer included in the synchronous DRAM of FIG. 1;
6 is a signal waveform diagram showing one embodiment when the clock pulse width of the clock buffer of FIG. 5 is minimum. FIG.
7 is a signal waveform diagram showing an embodiment when the clock pulse width of the clock buffer of FIG. 5 is maximum. FIG.
8 is a system configuration diagram showing an embodiment of a computer including the synchronous DRAM of FIG. 1. FIG.
FIG. 9 is a circuit diagram showing an example of a clock buffer included in a synchronous DRAM developed by the present inventors prior to the present invention.
[Explanation of symbols]
BNK0 to BNK1 ... Bank, MARY ... Memory array, RD ... Row address decoder, SA ... Sense amplifier, CD ... Column address decoder, WA ... Write amplifier, MA ... Main amplifier, AB ... Address buffer , RA: Row address register, BS: Bank selection circuit, CC: Column address counter, MR: Mode register, IB: Data input buffer, OB: Data output buffer, CB: Clock buffer, TG ... ... Timing generation circuit, D0 to D7 ... Data input / output terminal, CSB ... Chip selection signal input terminal, RASB ... Row address strobe signal input terminal, CASB ... Column address strobe signal input terminal, WEB ... Write enable signal Input terminal, DQM ... Data mask signal input terminal , CLK ...... clock signal input terminal, CKE ...... clock enable signal input terminal, A0~A11 ...... address input terminal.
IC1 to IC4 ... input circuit, PG ... pulse generation circuit, P1 to P3 ... P channel MOSFET, N1 to N4 ... N channel MOSFET, V1 to VI ... inverter, NA1 to NA4 ... NAND gate, DL ... Delay circuit.
SRFF …… Set-reset flip-flop.
CPU ... Central processing unit, SBUS ... System bus, RAM ... Random access memory, ROM ... Read only memory, DPYC ... Display control unit, FLM ... Frame memory, DPY ... Display device, PERC ... Peripheral Device controller, KBD ... Keyboard, EXM ... External storage device, POWS ... Power supply device.

Claims (4)

A first inverter having a first input node for receiving a first pulse signal; a second input node for receiving a second pulse signal; and a first output node for outputting a third pulse signal; and the third pulse. A delay circuit to which a signal is input; a third input node to which the first pulse signal is input; a fourth input node connected to the delay circuit; and a second output node for outputting the second pulse signal; A flip-flop circuit having a clock buffer,
The first inverter has a gate connected to the first input node, a source / drain path connected between the first potential and the first MOSFET, and the second input node. A second MOSFET having a gate; and a third MOSFET having a second potential lower than the first potential and a source / drain path connected between the first MOSFET and a gate connected to the second input node. ,
Said second pulse signal, Ri signal der transmitted through the delay circuit,
The semiconductor device, wherein the flip-flop circuit is set by the first pulse signal and is reset by a signal input from the delay circuit . In claim 1 ,
The flip-flop circuit further includes a second inverter connected to the third input node,
A semiconductor device characterized in that the size of the MOSFET constituting the second inverter is smaller than the size of the first MOSFET. In any one of Claim 1 to 2 ,
The semiconductor device, wherein the clock buffer outputs the third pulse signal based on the first pulse signal and the second pulse signal. In any one of Claim 1 to 3 ,
The semiconductor device is a synchronous DRAM,
The semiconductor device, wherein the clock buffer receives the first pulse signal and supplies the third pulse signal to each part of the synchronous DRAM.

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