JPS6325886A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To contrive the increase of the speed and stability of an action by providing respectively a common loading means at an access signal changing detecting circuit and providing two input NAND gate circuits to receive the electric potential of respective output nodes. CONSTITUTION:Since the output terminal of unit circuits UATD0-UATDj-1 is connected in common to an output node no1, at least one address signal out of these is inverted, and then, the potential of the output node no1 is pulled out to the ground potential and only the delaying time part of an inverting delaying circuit is temporarily goes into the low level. On the other hand, the potential of an output node no2 in which the unit circuit UATDj is linked is pulled out temporarily to the ground potential of the circuit as well as the case of the output node no1 and goes into a low level. The electric potentials of these output nodes no1 and no2 are respectively supplied to two input terminals of a NAND gate circuit NAG1 respectively as address changing detecting signals phiatd1 and phiatd2. Thus, it can be prevented that the pulling-out level of an output node is raised by a wiring distribution resistance.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and can be used, for example, in a semiconductor integrated circuit device such as a dynamic RAM having an address signal change detection (ATD) circuit. It is about effective techniques.

[Conventional technology]

A semiconductor memory device having a built-in address signal change detection circuit for detecting a change in an address signal etc. supplied from the outside is described in, for example, Japanese Patent Laid-Open No. 59-45685.

[Problem that the invention seeks to solve]

One of the operating modes in dynamic RAM is a so-called static column mode in which the memory information of multiple memory cells connected to the word line is serially output by switching the column address while the word line remains selected. There is. Dynamic RAM with such static column mode function
Now, we aim to reduce power consumption by using the address signal change detection circuit described above to detect changes in the column address signal and generate timing signals for switching data lines and starting the main amplifier circuit. ing.

FIG. 3 shows a circuit diagram of an address signal change output circuit ATD for a dynamic RAM, which was developed by the inventors of the present invention prior to the present invention. In order to simplify the circuit, the 0 address signal change detection circuit ATD in FIG. Internal address signals ayQ to ayj or their inverted signals 71 to r7 and their inverted delay circuits DN1 to D are provided between the gates and correspond to the respective gates.
Two N-channel MOSFETs QA3 in series form receiving an inverted delay signal by NA. QA4~QA9. Q.A.I.
It is composed of a plurality of unit circuits UATDO to UATD j consisting of O.

In each unit circuit, when the corresponding internal address signal or its inverted signal changes from low level to high level, the two N-channel inter-O3FETs in the - group are both turned on, and the potential of the output node nO is set to the ground potential of the circuit. It is pulled out to a low level like .

However, as the storage capacity of dynamic RAM continues to increase, the number of address signals increases, and pads for inputting these address signals are placed separately on both sides of the semiconductor substrate. When the unit circuits of the signal change detection circuit are placed apart from each other, the distributed resistance Rs and distributed capacitance of the wiring for coupling the unit circuits and the output node no become large. Therefore, when a change in the internal address signal is detected by these unit circuits, a voltage drop occurs due to the above-mentioned distributed resistance Rs, and the potential of the output node no does not fall sufficiently to a low level. The amount of distributed capacitance λ causes a signal delay depending on its time constant. Therefore, speeding up of the operation of the address signal change detection circuit ATD is hindered, and the pulse width of the address signal change detection signal changes depending on the transitioning address signal, making the operation of the dynamic RAM as a whole unstable. I end up making it.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit device equipped with a signal change detection circuit that achieves high-speed and stable operation.

The objects and novel features of this invention and its ponds are as follows:
It will become clear from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows.

That is, in one or more unit address signal change detection circuits separately arranged on both sides of the semiconductor substrate,
A common load means is provided for each, and a two-man NAND gate circuit is provided that receives the potential of each output node.

[For production]

According to the above-mentioned means, change detection signals are formed on both sides of the semiconductor substrate and then transmitted to the NAND gate circuit, so that the operation as an address signal change detection circuit is speeded up and the operation is stabilized. It is possible to aim for

〔Example〕

Figure 2 shows a dynamic RA to which this invention is applied.
A block diagram of one embodiment of M is shown. Each circuit element in the figure is formed on a single semiconductor substrate such as, but not limited to, single crystal P-type silicon using a known CMO3 (complementary MOS) integrated circuit manufacturing technology. In the figure, a MOS FET with an arrow added to the channel (back gate) portion is a P-channel type, and is distinguished from an N-channel MOS FET without an arrow added.

N-channel MOSFETs are made of polysilicon formed on the surface of such a semiconductor substrate, including a source region, a drain region, and a thin gate insulating film formed on the surface of the semiconductor substrate between the source and drain regions. It consists of a gate electrode that looks like this. P channel MOS
The FET is formed in an N-type well region formed on the surface of the semiconductor substrate. This allows the semiconductor substrate to
It forms a common substrate gate for a plurality of N-channel MOSFETs formed thereon. The N-type well region constitutes the substrate gate of the P-channel MOSFET formed thereon. The substrate gate of the P-channel MOSFET, ie, the N-type well region, is coupled to power supply voltage Vcc. The substrate gate of the N-channel MOSFET, ie, the semiconductor substrate, is coupled to a negative substrate bias potential generated within the chip or to a circuit ground potential.

In the dynamic RAM of this embodiment, although not particularly limited, the X address signal and the Y address signal are supplied via the same external terminal by a multiplex method. It also has an automatic refresh function and a so-called column static operation function that performs continuous read or write operations in the same row by changing the column address signal within - memory access periods.

Therefore, in the automatic refresh operation mode, a refresh address counter REFC for specifying a word line to be refreshed, a row address signal formed by this refresh address counter REFC, and a row address signal supplied from the outside are switched and selected. A multiplexer MPX for detecting the address signal and an ATD circuit for detecting a level change of an address signal supplied from the outside are provided.

The memory array M-ARY has a two-intersection system, and has fi+1 sets of complementary data lines DO- arranged in the horizontal direction in FIG.
It is composed of (m+1) x (n+1) memory cells coupled to the intersections of these complementary data lines and the word lines.

Each data line has an address selection MOS F E as represented by the complementary data line DO.
m consisting of T Q m and an information storage capacitor Cs
+1 memory cells are coupled with a predetermined regularity.

Each complementary data line DO-DO-Dn-Dn is connected at one end to a sense amplifier S via a precharge circuit PC.
It is coupled to the corresponding unit circuit of A. The precharge circuit PC is provided between both signal lines of each complementary data line.
+1 N-channel type switch MOSFETQ7~
Consists of Q8. These switches MOS F
The gates of ET are commonly connected, and a timing signal φpc is supplied from a timing control circuit TC, which will be described later. These timing signals φ are set to high level when the dynamic RAM is inactive, and
It is set to low level in the operating state of M. Switch M
The O5FETs Q7 to Q8 are turned on in the non-operating state of the dynamic RAM when the timing signal φpc is at a high level, and short-circuit both signal lines of the complementary data line so that the voltage becomes approximately 1/2 of the power supply voltage VCC. Set to precharge level. As a result, the level of the complementary data line during a read operation changes toward a high level or a low level around this half precharge level, so that the read operation becomes faster.

Each unit circuit of the sense amplifier SA is a P-channel MOSFET Q 3 , Q shown as a representative.
4 and N-channel MOSFETQ5. Q6, and its pair of input/output nodes are coupled to corresponding complementary data lines Do-DO.

The launch circuit may include, but is not limited to, a parallel P-channel power switch MOSFETQ.
Power supply voltage VCC is supplied through I and Q2, and a parallel N-channel type power switch MOSFETQI
3. The circuit's ground voltage is supplied through Ql4. These power switch MOSFETs QI, Q2 and MO
SFETQI 3. Ql 4 is commonly used for latch circuits provided in other similar rows within the same memory mantle. In other words, P-channel MOs constituting multiple latch circuits arranged in the same memory mat
The sources of the 5FET and the N-channel MOSFET are commonly connected to a common source line SP or SN, respectively.

Complementary timing signals φpal and φpal for activating the sense amplifier circuit SA are applied to the gates of the MOSFETQI and Q13, and the MOSFETQ
2. The gate of QL4 receives the timing signal φpal.
, φpa2, which are formed slightly later than φpal, are applied. Thereby, the amplification operation of the read signal by the sense amplifier circuit SA is performed in two stages. That is, in the first stage where the timing signals φpal and φpal are formed, the MOS FET with a relatively small conductance
Due to the current limiting effect of Q1 and QL3, the minute read voltage applied between the pair of data lines from the memory cell is amplified without undergoing undesired level fluctuations. After the potential difference of the complementary data lines is increased by the amplification operation of the sense amplifier circuit SA, the second stage in which the timing signal φpa2+φpa2 is formed, MOSFETs Q2 and Q with relatively large conductance
L4 is turned on. The amplification operation of the sense amplifier circuit SA is performed by MO3F'ETQ2. It is made faster by turning on QL4. By performing the amplification operation of the sense amplifier circuit SA in two stages in this way, it is possible to read data at high speed while preventing undesired level changes in the complementary data line.

Each of the complementary data lines is coupled on the other hand to a corresponding switch MOSFET of column switch C3W. Column switch C3W is the MO shown as a representative.
SFETQ9. n+ like QIO and Qll, QL2
It is composed of a set of switch MOSFETs and selectively connects a designated complementary data line and a common complementary data line CD-C. These switch MOSFETQ9. Q
Column decoder C is connected to the gates of 10 to Qll and QL2.
Data line selection signals YO to Yn formed by DCR
is supplied.

On the other hand, the gates of address selection MOS FETQm of memory cells arranged in the same column of memory array M-ARY are coupled to corresponding word lines WO to Wn. These word lines are selected by a row address decoder.

The row address buffer RADB receives X address signals AXO to AX+ supplied to the address signal input terminals AO-Ai in synchronization with the fall of the row address strobe signal RAS supplied as a control signal from the outside, and reads these external addresses. Internal address signal aO in phase with the signal
Complementary internal address signals consisting of internal address signals aO to ai in opposite phase to at (hereinafter, these are collectively referred to as aQ-at
). These internal complementary address signals are supplied as one input signal of multiplexer MPX.

As another input signal, the multiplexer MPX is supplied with a refresh address signal from the refresh address counter REFC for specifying the word line to be refreshed in the automatic refresh operation mode. , the multiplexer MPX is supplied with a timing signal φref, which is set to the H/F level in the automatic refresh operation mode, as a switching signal from the timing P control circuit TC. In normal read or write operation mode, internal complementary address signal aQxai supplied from row address buffer RADB is selected and transmitted to the row address decoder as internal address signals axQ to axi. In the automatic refresh operation mode in which the refresh address counter REFC is in the automatic refresh operation mode, the refresh address signal supplied from the refresh address counter REFC is selected and similarly transmitted to the row address decoder.

Although not particularly limited, the row address decoder has a two-stage structure and includes a primary row address decoder RDCRI and a secondary decoder RDCR2. The primary row address decoder RDCR1 decodes the lower two bits of complementary internal address signals axO and axl to form four word line selection timing signals φx00 to φx11 (not shown) synchronized with the word line selection timing signal φX. do. These word line selection timing signals are internal X address signals lx2 to lx2 excluding the lower two bits.
Secondary row address decoder DCR that decodes axi
2, the word line selection signal (
WO-Wm) is formed. In this way, by making the row address decoder have a two-stage structure, the layout pitch (interval) of the secondary row address decoder RDCR2 and the word line pinch can be matched, and the space on the semiconductor substrate can be effectively utilized. It is something that can be done.

Column address buffer YADB receives Y address signal AYO-AYj supplied in synchronization with the falling edge of column address strobe signal CAS via address signal input terminals AO to At, and receives complementary internal address signal YADB.
Form O-a y j.

These complementary internal address signals ayo-ayj are supplied to a column address decoder CDCR and also to an address signal change detection circuit ATD.

The column address decoder CDCR decodes the complementary internal address signals yo- and yi supplied from the column address buffer CADH, and outputs the timing control circuit T.
In synchronization with the data line selection timing signal φy supplied from C, a data line selection signal YO=Yn for selecting a designated set of complementary data lines is formed and supplied to the column switch csW.

Between the common complementary data lines CD and CD, there is a precharge MOSFET Q similar to the precharge circuit PC described above.
15 are provided. In addition, this common complementary data line CD
-CD is coupled to the input/output node of the main amplifier MA and also coupled to the output terminal of the data manual buffer DIB.

The precharge MOSFET Q15 short-circuits both the complementary common data lines CD and ζ5 in the non-selected state of the dynamic RAM where the timing signal φpcd supplied from the timing control circuit TC is at a high level.
The level is set to a half precharge level, such as about 1/2 of the power supply voltage Vcc. Moreover, the main amplifier MA further amplifies the read signal supplied from the selected complementary data line via the complementary common data line CD-τ5. The output terminal of this main amplifier MA is coupled to the input terminal of the data output sofa DOB.

The data output sofa DOB is a dynamic RAM
The main amplifier MA is brought into operation by the high level of the timing signal φr generated in the read operation mode, and the output signal of the main amplifier MA is sent out from the data output terminal ])o. In the non-operating state or write operation mode of dynamic RAM, the data output bumper DO
The output of B is placed in a high impedance state.

The data manual buffer DIB is activated by the high level of the timing signal φW generated in the write operation mode of the dynamic RAM, uses the write data supplied from the outside via the data input terminal Di as a complementary write signal, and uses the write data supplied from the outside via the data input terminal Di as a complementary write signal. Common complementary data line CD-3
100 to the selected memory cell. When the dynamic RAM is in a non-operating state or in a read operation mode, the output of the data manual buffer DIB is in a high impedance state.

Address signal change detection circuit ATD receives complementary internal address signal ayo-main yj and detects a change in the signal.

When at least one address signal among these Y address signals is inverted from low level to high level or from high level to low level, the address signal change detection signal φatd is set to high level and output to the timing control circuit TC. .

The refresh address counter REFC operates in the automatic refresh operation mode of the dynamic RAM, counts the timing signal φC supplied from the timing control circuit TC, and forms a refresh address signal for specifying a word line to be refreshed. Supplies multiplexer MPX.

The timing control circuit TC receives a row address strobe signal πAS, a column address strobe signal CAS, and a write enable signal WE supplied as control signals from the outside, and an address signal change detection signal φatd formed by an address signal change detection circuit ATD. receive,
The various timing signals mentioned above are formed and supplied to each circuit.

FIG. 1 shows a circuit diagram of an embodiment of the address signal change detection circuit ATD of the dynamic RAM. In the dynamic RAM address signal change detection circuit ATD of this embodiment, in order to reduce the number of circuit elements, a unit circuit is constructed using two MOSFETs and one inverting delay circuit provided corresponding to each address signal and its inverted signal. It consists of In addition, dynamic RAM
has a large storage capacity and external terminal A for inputting address signals.
Since O-Ai has a large number of terminals, any one or more external terminals, for example, the topmost external terminal Ai, can be connected to the other external terminals AO to A1-1 on the opposite side across the memory array, etc. Placed on a semiconductor substrate (chip). Therefore, among the unit circuits of the address signal change detection circuit ATDOj +1 (1il), the unit circuit UATDj corresponding to the highest Y address signal AYj is arranged close to the external terminal Ai.

For this reason, a common load MOSFETQAI is provided corresponding to the unit circuits UATDO-UATDj-1 that detect changes in the Y address signal A Y O-A Yi-1.
In addition, load MOSFET corresponding to unit circuit UATD j
QA2 is provided. Furthermore, the load MO5FETQAI
The drains of QA2 and QA2 are output nodes nol and no2, respectively, and the two-man NAND gate circuit N A G 1
are respectively coupled to the two input terminals of .

Unit circuit UATDO of address signal change detection circuit ATD
-UATD j is an output node n, as represented by a unit circuit UATDO provided for complementary internal address signals ayQ and ayQ.

Two sets of N-channel MOS FETQA3. Q
A4 and QA5. It is composed of QA6 and inverting delay circuits DNI and DN2. The drains of MOSFETs QA3 and QA5 are commonly coupled to output node noi. A non-inverted internal address signal ayQ is connected to the gate of MOSFET QA3 and the input terminal of the inverted delay circuit DNI.
is supplied to the gate of MOSFET QA4, and the output f3 daQ of the inverting delay circuit DNI is supplied to the gate of MOSFET QA4.Similarly, the gate of MOSFET QA5 and the input terminal of the inverting delay circuit DN2 are The inverted internal address signal ayO is supplied to the gate of the MOSFET QA6, and the output signal da of the inverted delay circuit DN2 is supplied to the gate of the MOSFET QA6.

is supplied. The sources of MOSFETs QA4 and QA6 are coupled to the circuit's ground potential.

In the figure, unit circuits UADTI to UATDj-1 have the same circuit configuration as the unit circuit UATDO, and their output terminals are similarly connected in common to the output node nol. Between the output node nol and the power supply voltage Vcc, there is a P-channel type load MOSFET whose gate is connected to the ground potential of the circuit so that it is always on.
A QAI is provided. Furthermore, the unit circuit UATD j arranged on the opposite side of the semiconductor substrate is also the same as the unit circuit UAT
It has the same circuit configuration as Do, but its output terminal is coupled to output node n02. A P-channel type second load MOSFE whose gate is coupled to the circuit ground potential is connected between the output node no2 and the circuit power supply voltage Vcc.
TQA2 is provided.

The potential of the output node nol is the unit circuit UATDO~U
As the common output signal φatdl of A T Dj-1,
It is supplied to one input terminal of the NAND gate circuit NAGI. Furthermore, the potential of output node no2 is the unit circuit UAT.
The output signal φatd2 of Dj is supplied to the other input terminal of the NAND gate circuit NAG1.

An outline of the address signal change detection operation of these address signal change detection circuits ATD will be explained using the unit circuit UATDO as an example.

In FIG. 1, since the non-inverted internal address signal ayO is inverted and delayed by the inverted delay circuit DN1,
When the address signal does not change, the two MOSFEs
The potentials of the gates of TQA3 and QA4 are complementary. Therefore, MO5FETs QA3 and QA4 are not turned on at the same time, and the potential of the output node nol is
If other unit circuits are not in the signal change detection state, the voltage becomes high level like the power supply voltage Vcc. Furthermore, when the non-inverted internal address signal ayQ is inverted from a high level (i.e., address signal AYO is logic "L") to a low level (i.e., address signal AYO is logic "O"), the inversion delay circuit outputs an output delayed from this inversion. Although the signal dao goes high, the gate of MOSFET QA3 goes low before that, so the potential of the output node nol is not pulled down to the ground potential as well.

On the other hand, when the non-inverted internal address signal ayQ is inverted from a low level (i.e., address signal AYO is logic "0") to a high level (i.e., address signal AYO is logic "in"), MOSFET QA3 is turned on. . In addition, the output signal da of the inverting delay circuit DNI
Since Q changes from high level to low level with a delay of the delay time, MOS FET Q A 3
and QA4 are simultaneously turned on for the delay time of the inversion delay circuit. As a result, the potential of the output node nol is pulled down to the ground potential for a delay time, changes from high level to low level, and then returns to high level.

Similarly, MOSFET QA5 receives the inverted internal address signal ayQ and MOSFET receives the output signal of the inverted delay circuit DN2.
QA6 turns on at the same time, and output node no.
The potential of l is set to low level.

As mentioned above, the output terminals of the unit circuits UATDO-UATDj-1 are commonly connected to the output node nol, so if one of the address signals (one of them) is inverted, the potential of the output node nol becomes the ground potential. pulled out,
The signal is temporarily set to a low level for the delay time of the inversion delay circuit.

On the other hand, the output node n to which the unit circuit UATD j is coupled
As in the case of the output node nol described above, the potential of o2 changes from the low level of the non-inverted internal address signal ayj (that is, the logic '0' of the Y address signal AYj) to the high level (that is, the logic '1' of the Y address signal AYj). ) or the inverted internal address signal ayj changes from a low level (that is, the logic "1" of the Y address signal AYj) to a high level (that is, the logic "O" of the Y address signal AYj), - pulled to ground potential,
It is considered to be low level.

The potentials of these output nodes nol and no2 are respectively supplied to two input terminals of the NAND gate circuit NAG 1 as address change detection signals [π correction and r effect η. Since the address change detection signals ψaLdl and φa td2 are both at high level when no change in the column address signal is detected, the output signal of this NAND game 1/circuit 'IAGI is at low level. When one of the signals AYO to AYj is inverted, the address signal change detection signal φa
Since either tdl or φatd2 becomes low level, the output signal of the NAND gate circuit NAG1 is temporarily set to high level for the delay time of the inverse 5:delay circuit. The outputs of the NAND gate circuits 1i18N7 to G1 are supplied to the above-mentioned timing control circuit TC as a common address signal change detection signal φatd of these address signal change detection circuits ATD.

As described above, in the dynamic RAM of this embodiment,
Since the number of external terminals AO to Ai to which address signals are supplied is large and they cannot be arranged all together on one side of the semiconductor substrate, one of them is arranged on the opposite side with the memory array etc. in between.

Further, in accordance with this, the corresponding unit circuit of the address signal change detection circuit ATD is placed apart from other unit circuits. However, corresponding to one or more unit circuits arranged on both sides of the semiconductor substrate, a common load MOS
FET are provided respectively, and the load MOS
Two address signal change detection signals φatdl and φatd2 are formed corresponding to FET. In addition, the address signal change detection signal of the unit circuit arranged separately from other unit circuits is input to the NAND gate circuit NAGIO high impedance as the address signal change detection signal φa td2 after the determination of the extraction level is completed. Supplied to the terminal. Therefore, in the address signal change detection circuit of the unit circuit arranged separately from the circuit unit circuit, the extraction level will not be increased by the wiring distributed resistance R5 (
, is performed stably. In addition, although the address signal change detection signal φa Ld2 is routed over a relatively long distance to the input terminal of the NAND gate circuit NAG10, there is almost no change in current due to changes in the address signal change detection signal φa td2, so the level decreases. The signal delay is negligibly small.

As shown by Honjitsuo above, the present invention can be applied to a dynamic type RA having an address signal change detection circuit ATD.
For semiconductor bond circuit devices such as M') I! By doing this in January, you will get the following effects. That is, (11) one or more unit address signal change detection circuits arranged separately on both sides of the semiconductor substrate are each provided with a common load means, and a two-man power system that receives the potential of each output node is provided. By providing a NAND gate circuit, input signal change detection signals are formed on both sides of the semiconductor substrate and then transmitted to the NAND gate circuit, so the lead-out rail of each output node is reduced to one wiring.
5 resistance, it is possible to prevent the increase in resistance.

(2) Item (1) above provides the effect that the operating margin of the address signal change detection circuit ATD can be improved.

(3) According to the above item (1), it is possible to obtain the effect that the operation speed in the dynamic RAM 0 column static mode can be sped up.

Although the invention made by the present inventor has been specifically explained based on Examples above, this invention is not limited to the above Examples, and it should be noted that various changes can be made without departing from the gist of the invention. Not even. For example, an amplifier circuit may be provided to increase the current supply capability of the address signal change detection signal by a unit circuit placed separately from other unit circuits and speed up signal transmission. NAND gate circuit NAG into which the detection signal is input
Either way, the logic threshold level of the input terminal of I is made relatively high. In addition, the load MOSFETs QAI and QA2 are N-channel MOSFETs fj! It may also be something that consists of Specific circuit configuration of each unit circuit of address signal change detection circuit ATD and dynamic RAM
Various embodiments can be adopted, such as block configurations and combinations of control signals.

In the above explanation, the invention made by the inventors of the present application was mainly applied to an ATD circuit of a dynamic RAM, which is the background of the invention, but this is not intended to be conclusive; for example, It can also be applied to various semiconductor memory devices that incorporate address signal change extraction circuits.

The present invention is applicable to at least a semiconductor integrated circuit device having a signal change detection circuit for detecting a change in an input signal.

[Effects of the Invention] The effects obtained by the representative inventions disclosed in this application are briefly explained below. In other words, one or more unit address signal change detection circuits separately arranged on both sides of the semiconductor substrate are each provided with a common load means, and a two-manufactured NAND gate circuit receives the potential of each output node. By providing a change detection signal of the input signal on both sides of the semiconductor substrate, the signal is transmitted to the NAND gate circuit after being formed on both sides of the semiconductor substrate, thereby preventing the pull-out level of each output node from increasing due to wiring distribution resistance. Therefore, it is possible to realize a semiconductor integrated circuit device such as a dynamic RAM having an address signal change detection circuit with improved operating margin and faster operation.

[Brief explanation of drawings]

Figure 1 shows a dynamic RAM to which this invention is applied.
2 is a block diagram showing an embodiment of a dynamic RAM including the address signal change detection circuit of FIG. 1; FIG. 3 is a circuit diagram showing an embodiment of the address signal change detection circuit of the present invention; FIG. 1 is a circuit diagram of an address signal change detection circuit developed by the inventors of the present invention prior to the above. ATD...Address signal change detection circuit, UATDO~
UATDj...unit circuit, QAI~QA2. Ql～Q
4...P channel MOS FET, QA3~Q
A10. Q5~Q15 ・ ・ ・ ・ N-channel MOSFETSNl...Inverter circuit, DNI~
DNA...inversion delay circuit, NAGl...NAND gate circuit, R3...wiring resistance. M A RY...Memory array, PC...Precharge circuit, SA...7th amplifier, USA...Sense amplifier unit circuit, C3W...Column switch, R
DCRI, RDCR2...Row address decoder, C
DCR...Column address decoder, RADB...
Row address buffer, CADB...column address buffer, MPX...multiplexer, MA...
Main amplifier, DOB... data output cover sofa, DI
B...Data buffer, REFC...Refresh counter, TC...Timing control circuit.

Claims (1)

[Claims] 1. A plurality of output terminals provided in common for each of a plurality of input signals input via adjacent pads on a semiconductor substrate, and a connection between the plurality of output terminals and a first power supply voltage. a plurality of load means each provided between the plurality of load means, and a first one provided in series between the plurality of output terminals and the second power supply voltage and receiving an input signal corresponding to each gate and an inverted delay signal thereof. and a plurality of signal change detection circuits each including a second MOSFET. 2. The first power supply voltage is the operating power supply voltage of the circuit,
The second power supply voltage is a circuit ground potential, the plurality of load means are a plurality of P-channel MOSFETs whose gates are coupled to the circuit ground potential, and the first and second MOSFETs are N-channel MOSFETs. MOSFET, and the plurality of output terminals are coupled to respective input terminals of a NAND gate circuit whose output signal is used as a common signal change detection signal for the plurality of input signals. The semiconductor integrated circuit device according to item 1. 3. The semiconductor integrated circuit device is a semiconductor memory device,
3. A semiconductor integrated circuit device according to claim 1, wherein said signal change detection circuit is for detecting a change in an address signal supplied to a semiconductor memory device.