KR100241062B1 - Sense amplifier of semiconductor memory device - Google Patents

Abstract

The present invention discloses a sense amplifier of a semiconductor memory device. The circuit includes pull-up means for pulling up the first node in response to the first control signal, first pull-down means for pulling down the second node to a voltage higher than the ground voltage in response to the second control signal, and Second pull-down means for pulling down the second node to ground voltage in response to a control signal, and an amplification for detecting and amplifying signals of bit lines and inverted bit lines connected between the first node and the second node; It consists of means. Accordingly, the sensing noise may be reduced to reduce current consumption, thereby improving dynamic refresh characteristics, thereby improving performance of the memory device.

Description

Semiconductor memory device

The present invention relates to a semiconductor memory device, and more particularly to a sense amplifier of a semiconductor memory device.

Recent semiconductor memory devices are making efforts to realize high integration, high performance, and low power. The semiconductor memory device inputs predetermined signals and addresses from the outside to select a word line corresponding to a given address by a circuit operation inside the semiconductor memory device, and the selected cell transistor is turned on and stored in the memory cell. As the charge and the charge of the bit line are combined, a certain amount of voltage difference is generated, and an internal signal ψ S is generated by a signal synchronized with the inverted row address strobe signal RASB by the voltage difference, and the signals ψ S / ψ SB The sense amplifiers connected between pairs of bit lines are operated.

1 is a circuit diagram of a sense amplifier of a conventional semiconductor memory device, comprising memory cells CA and CB each composed of a series-connected NMOS transistor CA and a capacitor C connected between a bit line pair and a word line, respectively. NMOS transistor MP3 having a source electrode connected to the power supply voltage and a gate electrode to which signal ψSB is applied, a source electrode connected to the drain electrode of the NMOS transistor MP3, a drain electrode connected to the bit line BL, and an inverting bit line PMOS transistor MP0 having a gate electrode connected to BLB, a source electrode connected to the drain electrode of the NMOS transistor MP3, a gate electrode connected to the bit line BL, and a drain electrode connected to the inverting bit line BLB. PMOS transistor MP1, NMOS transistor MN0 having a drain electrode connected to bit line BL and a gate electrode connected to inverted bit line BLB, and inverted bit line BLB. Connected to the drain electrode, the gate electrode connected to the bit line BL, the source electrode connected to the source electrode of the NMOS transistor MN0, the drain electrode connected to the source electrode of the NMOS transistor MN1 and the NMOS transistor MN1, and the ground voltage. The NMOS transistor MN3 has a connected source electrode and a gate electrode to which a signal? S is applied.

The operation of the sense amplifier of the conventional semiconductor memory device will be described with reference to FIG. 3 as follows.

When the inverted low address strobe signal RASB becomes active at the ″ low ″ level, an internal clock signal ψS / ψSB is generated, the signal ψS is at the ″ high ″ level and the signal ψSB is ″ low ″. Level. The high level signal ψS turns on the NMOS transistor MN3 and the low level signal ψSB turns on the PMOS transistor MP3 due to the slope at which the signals ψS / ψSB turn on. Therefore, the drain electrode of the NMOS transistor MN3 gradually becomes the ground voltage, and the drain electrode of the PMOS transistor MP3 gradually becomes the power supply voltage. The NMOS transistors MN1 and MN2 and the PMOS transistors MP1 and MP2 are operated in accordance with the transition of the drain electrodes of the NMOS transistors MN3 and PMOS transistor MP3 so that data from the bit line pair is supplied to the power voltage or ground. It will be amplified by voltage.

The sense amplifier of the above-described conventional semiconductor memory device is continuously operated while the sense amplifier operated by the signal ψS generated by the inverted low address strobe signal RASB while the signal ψS maintains the ″ high ″ level. Driving at ground voltage level causes excessive sensing noise, which is a direct cause of excessive current consumption, and also affects word lines that are not activated by the ground voltage noise generated. Caused it.

An object of the present invention is to provide a sense amplifier of a semiconductor memory device capable of reducing sensing noise to reduce current consumption and improving dynamic refresh characteristics.

The sense amplifier of the semiconductor memory device of the present invention for achieving the above object is a pull-up means for pulling up the first node in response to the first control signal, a voltage higher than the ground voltage to the second node in response to the second control signal First pull-down means for pulling down the second node, second pull-down means for pulling down the second node to ground voltage in response to a third control signal, and connected between the first node and the second node and being bit And amplifying means for sensing and amplifying signals of lines and inverted bit lines.

1 is a circuit diagram of a sense amplifier of a conventional semiconductor memory device.

2 is a circuit diagram of a sense amplifier of the semiconductor memory device of the present invention.

3 is an operation timing diagram of the circuit shown in FIGS. 1 and 2;

4A and 4B are circuit diagrams of a circuit for generating the control signals shown in FIG.

Hereinafter, a sense amplifier of a semiconductor memory device of the present invention will be described with reference to the accompanying drawings.

FIG. 2 is a circuit diagram of a sense amplifier of a semiconductor memory device of the present invention, in which the NMOS transistor MN4 having a drain electrode connected to the source electrode of the NMOS transistor MN3 and a source electrode connected to the gate electrode and the ground voltage in the circuit shown in FIG. And an NMOS transistor MN5 having a drain electrode connected to the drain electrode of the NMOS transistor MN3, a gate electrode to which the signal? S 'is applied, and a source electrode connected to the ground voltage.

The circuit shown in Fig. 2 is composed of two paths having the bit line level as the ground voltage in order to reduce the ground voltage noise. In other words, one path using the drain electrode of the NMOS transistor MN3 as the ground voltage is formed by connecting the NMOS transistor MN3 and the NMOS transistor MN4 in series, and the NMOS transistor MN4 is a clamping diode NMOS. When the transistor MN3 is turned on, the drain electrode of the NMOS transistor MN3 does not completely drop to the ground voltage but instead falls to the threshold voltage of the NMOS transistor MN4. The other passage turns on the NMOS transistor MN5 in response to the signal? S 'delayed by a predetermined time of the signal? S so that the drain electrode of the NMOS transistor MN3 falls to the ground voltage completely.

The operation of the sense amplifier of the semiconductor memory device of the present invention shown in FIG. 2 will be described with reference to FIG.

When the inverted low address strobe signal RASB is activated at a ″ low ″ level, a ″ high ″ level signal ψS and a ″ low ″ level signal ψSB are generated inside the memory device using this signal. These signals turn on the NMOS transistor MN3 and the PMOS transistor MP3 of the sense amplifier to enable the operation of the sense amplifier. Thus, the sense amplifier senses and amplifies the signal from the pair of bit lines BL and BLB. However, at this time, the potential of the bit line (inverting bit line) does not completely drop to the ground voltage but falls to the threshold voltage of the NMOS transistor MN4, and the potential of the inverting bit line (bit line) rises to the power supply voltage. Thereafter, the signal ψS becomes active, which is a pulse signal that rises to the ″ high ″ level when the inverted low address strobe signal rises to the ″ high ″ level and then descends to the ″ low ″ level after a predetermined time delay. When the signal is applied to the NMOS transistor MN5, the NMOS transistor MN5 is turned on so that the drain electrode of the NMOS transistor MN3 falls to the ground voltage completely and the potential of the bit line (inverted bit line) falls to the ground voltage completely. do.

FIG. 4A is a circuit diagram of a circuit for generating the signals ψS and ψSB shown in FIG. 2, in which the signal ψS is inputted, buffered and inverted by five inverted row address strobe signals RASB. 10, 12, 14, 16, and 18, and the signal ψ SB is composed of two series-connected inverters 20 and 22 which input and buffer the output signal of the inverter 16.

FIG. 4B is a circuit diagram of a circuit for generating the signal ψS 'shown in FIG. 2, showing four series-connected inverters 30, 32, 34, 36 for inputting and buffering an inverted row address strobe signal RASB; And a NOR gate 38 which non-logically combines the row address strobe signal RASB and the output signal of the inverter 36 to generate a signal? S '.

That is, as shown in Fig. 3, the signal ψ S is a signal obtained by inverting the inverted row address strobe signal RASB by a predetermined time delay and the signal ψ SB is obtained by delaying the inverted row address strobe signal RASB by a predetermined time. It is a signal. The signal? S 'is a pulse signal that detects and rises at the rising edge of the inverted row address strobe signal and falls after a delay time equal to the delay time of the logic gates shown in FIG. 4B.

The sense amplifier of the semiconductor memory device of the present invention described above divides two paths that cause the bit line (inverting bit line) potential to fall to the ground voltage, and first converts the potential of the bit line (inverting bit line) through the one path to the NMOS transistor. By lowering the potential of the bit line (inverting bit line) to the ground voltage through another passage, the sensing noise and current consumption are reduced to improve dynamic refresh characteristics.

Therefore, the sense amplifier of the semiconductor memory device of the present invention can reduce the sensing noise to reduce the current consumption, thereby improving the dynamic refresh characteristics, thereby improving the performance of the memory device.

Claims (7)

Pull-up means for pulling up the first node in response to the first control signal; First pull-down means for pulling down the second node to a voltage higher than the ground voltage in response to the second control signal; Second pull-down means for pulling down the second node to a ground voltage in response to a third control signal; And amplifying means connected between the first node and the second node and configured to sense and amplify signals of bit lines and inverted bit lines. 2. The sense amplifier of claim 1, wherein the first control signal is inverted after a predetermined time delay of the inverted row address strobe signal. The sense amplifier of claim 1, wherein the second control signal delays the inverted row address strobe signal for a predetermined time. The sense amplifier of claim 1, wherein the third control signal is a pulse rising at the rising edge of the inverted row address strobe signal and falling at a predetermined time delay. The sense amplifier of claim 1, wherein the pull-up means is a PMOS transistor having a source electrode connected to a power supply voltage, a gate electrode to which the first control signal is applied, and a drain electrode connected to the first node. . The semiconductor device of claim 1, wherein the first pull-down means comprises: a first NMOS transistor having a drain electrode connected to the second node and a gate electrode to which the second control signal is applied; And a second NMOS transistor having a drain and a gate electrode connected to a source electrode of the first NMOS transistor, and a source electrode connected to a ground voltage. The method of claim 1, wherein the second pull-down means comprises a third NMOS transistor having a drain electrode connected to the second node, a gate electrode to which a third control signal is applied, and a source electrode to which a ground voltage is applied. Sense amplifiers in semiconductor memory devices.