JPS59140688A - Static mosram - Google Patents

Abstract

PURPOSE:To increase the timing margin and also to ensure a high-speed operation for a static MOSRAM by providing an edge trigger circuit which receives an address signal supplied from outside and detects the change timing of the address signal and a gate circuit which receives the output signal of said edge trigger circuit and inhibits the generation of the write control signal for a fixed period. CONSTITUTION:When an external address signal AXi is changed to a low level from a high level, a corresponding internal address signal axi' is also changed to a low level to a high level with a delay. The signal axi' and the output of an exclusive OR circuit EX which receives the delayed signal are discordant with each other just for the delay time and set at a high level respectively. This edge detecting signal is outputted as a timing signal phi through a gate circuit G2. An MOSFETQ13 is turned on when the timing output phi is set at a high level. Then the input capacity of an inverter IV1 is charged up to a high level. Thus a gate control signal phiew produced by the inverter IV1 is set at a low level, and a gate circuit G1 is closed.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a static RAM configured with MOSFETs (insulated gate field effect transistors).

Detects the change timing of the external address signal,
An internally synchronous (asynchronous) static RAM (Random Access Memory) used for timing control of its internal operations is being considered.

In such a static RAM, as shown in the timing diagram of FIG. 1, an inverter circuit is used to secure the time difference (setup time tas) between the address signal A+ and the write enable signal WE during the write operation. A constructed delay circuit was used. That is, when writing to the memory cell selected by the address signal A+, if the internal write control signal is generated before the memory cell according to the address signal Ai is selected, the memory cell selected in the previous operation cycle is This is because an erroneous write occurs in which a memory cell is written.

Therefore, it is necessary to form an internal write signal by taking into consideration the signal propagation delay time in the address decoder, the operation delay time in the address decoder, etc. after address No. 16 As is input, and its timing control is extremely difficult. .

This is because the delay time from the input of the address signal Ai to the selection of one memory cell varies due to variations in device characteristics and variations in power supply voltage.

Therefore, in the conventional static MO3RAM, the timing margin is small and the write enable signal WE supplied from the outside must have a large set amplifier time tas with respect to the address signal Ai, resulting in a long write operation cycle. There is a problem with this.

An object of the present invention is to provide a static MO3RAM that can increase the timing margin.

Another object of the present invention is to provide a static MO3RAM that operates at high speed.

Further objects of the invention will become apparent from the following description and drawings.

Hereinafter, this invention will be explained in detail together with examples.

FIG. 3 shows a circuit diagram of an embodiment of the present invention. Although not particularly limited, the RAM in the figure is a well-known 0M RAM.
O3 (complementary-metal-insulator-semiconductor) integration port V & (I
C) formed on a semiconductor substrate, such as a single silicon crystal, by technology.

The terminals Ax, Ay, Din, Dout, WE and CS are its external terminals. Note that the power supply terminal is omitted in the figure.

One specific circuit of the memory cell MC is shown as a representative, which is a memory MO3FETQ1. Q2 and the above MO3FETQ
1. High resistances R1 and R2 formed of a polysilicon layer for information retention are provided between the drain of Q2 and the power supply voltage VDD. MO3FETQI above
, Q2 and the complementary data lines Do, DO are connected with transmission gates MO3FE, TQ3. Q4 is provided.

Other memory cells MC also have similar circuit configurations. These memory cells are arranged in a matrix. Transmission gate type MO3FETQ3 of memory cells arranged in the same row. The gates of Q4 and the like are connected to the corresponding words 1ll, W1 and W2, respectively, and the input/output terminals of the memory cells arranged in the same column are connected to a pair of corresponding complementary data (or pinpoints) DO,
Connected to DO and Dl, bl.

In the memory cell MC, in order to make it consume low power, the resistor R1 is set to such a value that the gate voltage of MO3FETQ2 can be maintained above the threshold voltage when MO5FETQ1 is turned off. High resistance value ω. Similarly, the resistor R2 is also made to have a high resistance value. In other words, the resistor R1 has a current supply capacity sufficient to prevent the information charges accumulated in the gate capacitance (not shown) of the MO3FET Q2 from being discharged due to the drain leakage current of the MO3FET QI. .

According to this example, the static type RAM is 0MO3
-IL by IC technology! As mentioned above, the memory cell MC is an n-channel MO3F.
It is composed of an ET and a polysilicon resistance element. P-channel inter-channel O8FET instead of the above polysilicon resistance element
The size of the memory cell and memory array can be reduced compared to the case where the memory cell and the memory array are used. That is, when a polysilicon resistor is used, it can be formed integrally with the gate electrode of the driving MO3FET QI or Q2, and the size of the resistor itself can be reduced. Further, unlike when p-channel MO3FETs are used, there is no need to separate them from the drive Mo5rETQ1°Q2 by a relatively large distance, so no wasted blank space is generated.

In the figure, the word line W1 is connected to the X address decoder
- Drive circuit DVI that receives the selection signal formed by DCR
selected by The same applies to the other word line W2.

The X address decoder X-DCR is mutually l
J14m NOR gate circuit G1. Consists of G2 etc. The inputs of these NOR gate circuits Gl, G2, etc.
Internal complementary address signals 0-ai processed by an X-address buffer X-ADB receiving an external address signal AX supplied from an appropriate circuit device (not shown) are applied in a predetermined combination.

A pair of data lines DO in the memory array.

'i50 and DI, DI are transmission gates MO3FETQ9. for data line selection, respectively. QIO and Qll,
It is connected to common data lines CD and CD via a column switch circuit composed of G12. The common data lines CD and CD have an input terminal of the readout circuit DOB,
The output terminal of write circuit DIB is connected. The output terminal of the read circuit DOB sends a read signal to the data output terminal Dout, and the input terminal of the write circuit DTB is applied with a write data signal supplied from the data input terminal Din.

MO3FETQ9 that constitutes the above column switch circuit.
A selection signal is supplied to the gates of QIO, Qll, and G12 from the Y address decoder Y-DCR, respectively.

This Y-address decoder Y-DCR is composed of mutually similar NOR gate circuits G3, G4, etc. These NOR gate circuits G3. The input of G4 receives an external address signal AY supplied from an appropriate circuit device (not shown).
Internal complementary address signals lO-aj processed by the receiving Y-address buffer Y-ADB are applied in a predetermined combination.

The ii+ control circuit CON receives control signals from the external terminals WE and C3 and forms an internal fall timing signal. Also, in order to increase the write timing margin, a gate circuit as described later is built in. There is.

Between each data line and the power supply voltage VDD, p-channel MO3FETs Q5 to G8 are provided as data line loads. Although not particularly limited, an internal chip selection signal B is applied to the gates of the MO3FETs Q5 to G8 in order to reduce the erase current flowing through the memory cell in the chip non-selected state.

In this embodiment, in order to increase the timing margin of write operation, an edge trigger circuit EGT is used to detect change (transition) timing of external address signals AX and AY.
is provided.

That is, the address buffer X-ADB.

Address signals ax' and ay° formed by Y-ADB are input to the edge 1 trigger circuit EGT. The timing signal φ generated by the edge trigger circuit EGT is transmitted to a gate circuit (not shown) provided in the control circuit CON. Further, in this embodiment, although not particularly limited, the timing signal φ is transmitted to the X address decoder
- The DCR is also manually controlled, and prohibits the word line 24 selection state from occurring at the time of address signal transition.

FIG. 2 shows a circuit diagram of a specific embodiment of the edge trigger circuit EGT and the gate circuit.

Address Huff 7 y X-A D B (Y-A
D B ) T: Formed internal address signal axO''
is supplied to one input of the exclusive LkW summation circuit EX, which is shown as a representative. Further, the delayed signal passed through the delay circuit DL is supplied to the other input of the exclusive OR circuit EX. Other internal address signals ayn°
It is input to a circuit similar to the second one. Each of the above exclusive OR circuits U! ,

On the other hand, the control circuit CON includes the following gate circuit.

The write enable signal WE supplied from the external terminal is
It is input to the input cover sofa circuit B to form an inverted internal write enable signal we'.

This write enable signal W e ' is AND (
A write control signal we for controlling the data person cover sofa DrB is sent through the gate circuit G1.

This gate circuit Gl has data 1 formed in the next circuit.
~Control signal φew is applied.

Although not particularly limited, the edge detection timing output φ
is applied to the gate of MO3FET QI 3 on the power supply voltage side. In addition, a cascade type inverter [V2. IVl,
: Therefore, the jl extension signal φ° is formed. This timing signal φ'' is applied to the gate of the ground potential 1ull Mo5FETQI/I which is connected in series to the MO5FETQ13. This MO3FETQI 3. Ql
The signal at the connection point 4 is input to the inverter TVI,
The gate control signal φe1m is obtained from the output thereof.

The operation of the above embodiment circuit is explained by the timing output shown in FIG. 4. For example, when the external address signal AXi changes from high level to low level, the corresponding internal address signal axl' similarly changes from high level to low level with a delay. This address signal axi° and the output of the exclusive OR circuit EX which receives the delayed signal become high level by the above-mentioned delay time and do not match. This edge detection signal is
Data 1 is outputted as the timing signal φ through the circuit G2.

Due to the high level of this timing output φ, MO3FE
TQ13 turns on and charges up the input capacitance of inverter IVI to a high level. This results in
The gate control signal φe formed by the inverter rV1
The gate circuit G1 is controlled to be closed by setting w to a low level. Therefore, even if the write enable signal (M number WE) supplied from the external terminal becomes low level, the internal write control signal we is not sent out.

Next, the inverter IV2. When the timing signal φ'' delayed through TV3 becomes high level, MO3
FETQ14 is turned on, and the inverter IV
The input capacitance of I is discharged. As a result, the gate control signal ψet formed by impark IVI
The gate circuit G1 is controlled to be opened by setting n to the f level. Therefore, from this point on, the internal write control signal we is sent out in accordance with the write enable signal WE supplied from the external terminal.

In this embodiment, after the internal address signals for that operating cycle are formed as described above, the inverter [/2. T
The internal write control signal we can be generated after a certain time delay set by V3. This makes it possible to secure a sufficient timing margin for the write-enable signal WE for the address (fr) manually input from the external terminal.

In this case, even if there are variations in the readout characteristics or fluctuations in the power supply voltage, the timing of the generation of the internal write control signal we is controlled based on the edge detection signal of the internal AT/S signal. can be significantly reduced, and the control signal we can be generated at the optimal timing immediately after a specific memory cell is selected. Therefore, the write cycle can be shortened and the yield can be increased. 2.According to the inventor's calculations, the operating cycle time of the conventional static RAM, which is approximately 45 ns, is significantly reduced to 35 ns in the static RAM to which this invention is applied (high speed). This makes it possible to

Furthermore, a new operational function can be added in which continuous writing is performed by changing the address signal while keeping the write enable signal WE supplied from the external terminal fixed at a low level.

The invention is not limited to the above embodiments.

In addition to being used to prevent double selection, the edge detection output can also be used to control various memory operations, such as performing equalization by short-circuiting data lines immediately before reading.

Further, the specific circuit configurations of the edge detection circuit of address No. 18, the delay circuit that controls the sending timing of the internal write control signal, and the gate circuit used for the internal write signal we can be modified in various ways. be. For example, the address signal may be an address signal supplied from an external source.

This invention can be widely used in static MO3RAM.

[Brief explanation of the drawing]

FIG. 1 is a timing diagram for explaining a conventional write operation. FIG. 2 is a circuit diagram showing an embodiment of the main part of the present invention. FIG. 3 is a block diagram showing an embodiment of the present invention. - FIG. 4 is a timing diagram for explaining the operation. X-fi, D B・・X address buffer, Y-A
DB...Y address buffer, X-DCR...X address decoder, Y-DCR...Y address decoder, MC
・・Memory cell, DIB・・Write circuit, DOB・・Read circuit, CON・・Control circuit, EGT・・Edge trigger circuit Fig. 1 Fig. 2 Fig.

Claims (1)

[Claims] 1. An address buffer that receives an address signal supplied from the outside and processes it into an internal complementary address signal, and an address buffer that receives an output signal of this address buffer or an address signal supplied from the outside and changes the address signal. A static MO3R characterized in that it includes an edge trigger circuit that detects timing, and a gate circuit that receives the output signal of this edge trigger circuit and prohibits the generation of a write control signal for a certain period of time.
A.M. 2. The static type MO3RAM according to claim 1, wherein the static type MOS RAM is constituted by an 0M08 circuit. 3. The static MO3RAM is of an internal synchronous type that also controls its internal operation timing using an output timing signal generated by the edge trigger circuit. State type MO3RAM.