JPH0428096A - Non-volatile semiconductor memory device - Google Patents

Abstract

PURPOSE:To increase the operation speed in any access method by equalizing a bit line and a reference line at the time of the stand-by state and setting them to a voltage approximately equal to the middle between the '0' discrimination level and the '1' discrimination level of a sense amplifier. CONSTITUTION:Q13 to Q15... are N-channel transistors in the circuit diagram of a differential sense amplifying circuit and its attached circuit, and a threshold VTH is used to reduce the supply voltage to an about middle between the '0' discrimination level and the '1' discrimination level of the sense amplifier. N-channel TRs Q11 and Q12 have gates connected to a chip enable signal Ce and have drains connected to point G and have sources connected to points A and F respectively. N-channel TRs Q11 and Q12 are made conductive to charge the bit line and the reference line to prescribed potentials at the time of the stand-by state (Ce='H'). Thus, the operation speed is increased in any access method.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a nonvolatile semiconductor memory device comprising a floating gate transistor.

[Conventional technology]

FIG. 4 is a circuit diagram showing connections among a differential sense amplifier circuit, a bit line decoder, a memory cell, and a comparison memory cell of a conventional nonvolatile semiconductor memory device.
is a floating gate transistor whose control gate is connected to word lines W, L; M2 is a comparison floating gate transistor whose control gate is also connected to word lines W, L; 3 is a floating gate transistor. A bit line decoder that selects one bit line from among a plurality of bit lines in which a plurality of Ml are connected in parallel; 1 is a bit line decoder 3;
and an inverter whose input is connected to point B, Q3 has the output of inverter 1 connected to its gate, and its drain and source are the power supply, respectively. An N-channel transistor is connected to point B, and Q2 has its gate, drain, and source connected to each other. N-channel transistors connected to the output of inverter 1, points D and B, Ql is the gate.

A P-channel transistor whose drain and source are connected to point D, point D, and power supply, respectively, Q9. QIO is an N-channel transistor whose gate is connected to the power supply, 2 is an inverter whose input is connected to the 0 point, and Ql is an inverter whose output is connected to the gate, and whose drain and source are connected to the power supply and 0 point, respectively. N-channel transistor,
The gate, drain, and source of Q7 are the outputs of inverter 2, respectively, and point E.

Qg is an N-channel transistor connected to point 0, and Qg is a P-channel transistor whose gate, drain, and source are connected to point E, point E, and the power supply, respectively.

Next, the operation will be explained. First, in the memory transistor M1, which is a floating gate transistor, charge is accumulated in the floating gate due to the stored information, and the word line W,
A state with a high threshold voltage that does not become conductive even if L is selected, and a state with a low threshold voltage that causes the charge accumulated in the floating gate to be dissipated by ultraviolet rays and becomes conductive when word lines W and L are selected. It has two types of states. A bit line connected to a plurality of memory transistors Mx and Mz is connected to an N-channel transistor Q4 e by selection signals al and a2 in the bit line decoder 3.
When the memory transistor Ml is selected by the word line WL, which is selected when QR2>f becomes conductive, the potential of the bit line is changed by a feedback bias circuit composed of an inverter 1 and an N-channel transistor RO 3. , has a predetermined amplitude depending on whether the memory transistor M1 is in a conductive state or not. This voltage amplitude is determined by the bit line selection decoder 3.
appears at point B via
If the point potential is higher than a predetermined voltage, it is in a non-conducting state, and if it is lower, it is in a conducting state.

If QR is in a non-conductive state, a level of (power supply level) - (threshold voltage of Ql) appears at point D due to the P-channel transistor RO1. Also, if QR is conductive,
Conduction resistance of P-channel transistor Ro1 and QR, Q4
, QIS , a potential appears divided by the ratio of conduction resistances across M1. On the other hand, floating gate transistor M for comparison
z, N-channel transistor Q7. Qg, Qg.

Qlo, P-channel transistor Q6, and inverter 2 have similar configurations, M2 is a floating gate transistor in a conductive state, and Qg 1 Q71 Qe at point E.
* A potential divided by the ratio of conduction resistance of QIO and M2 appears.

This potential is manually applied as a reference voltage for the differential sense amplifier. In other words, the levels at point E and point D are compared, and the slight potential difference between point E and point D is greatly amplified and output. NI structure FfC
However, as the memory cell size decreases due to higher integration, the memory cell current decreases, and the charging capacity of the N-channel transistor 3 that charges the bit line must also be lowered. There is a problem in that it takes a long time to charge the line from the GND level to a predetermined potential, which hinders speeding up.

The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to obtain a high-speed nonvolatile semiconductor memory device even if the memory cells are reduced.

[Division! Means to solve a]

A non-volatile semiconductor memory device according to the present invention includes a differential sense amplifier circuit having a via line of a memory array consisting of floating gate transistors and a reference line having a floating gate transistor line for comparison. The voltage is equalized at the time of 7f switch I' and is set to a voltage approximately intermediate between the 1φ' judgment level 111 judgment level of the sense amplifier.

[Effect]

The differential sense amplifier in this invention equalizes the focus line and reference line during standby,
In addition, by setting the voltage to be approximately between the 1φ' judgment level and the '1' judgment level of the sense amplifier, the charging time of the bit line and reference line can be almost ignored.
Any access method can be speeded up.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. 1st
The figure shows a circuit diagram of a differential sense amplifier circuit and its auxiliary circuits which are an embodiment of the present invention, and the same reference numerals as those in the conventional circuit designate the same or corresponding parts. In the figure %Q
ts # Ql' * QIllg... is an N-channel transistor, using a threshold voltage VTR.

This step lowers the voltage of the power supply electronics to an intermediate level between the "φ" constant level of the sense amplifier and the "1" determination level. Ql
1 and Ql2 are N-channel transistors whose gates are connected to a chip enable (o8) signal, whose drains are connected to point 0, and whose sources are connected to points A and F, respectively. thus,
During standby (Oe=='E'), N-channel transistors Qll and Qu conduct, charging the bit line and reference line to a predetermined potential. This state is the second
This is shown in the timing chart in the figure.

FIG. 3 is a circuit diagram showing another embodiment of the present invention. In the figure, 4 is a reference voltage generating circuit. This reference voltage generating circuit 4 is activated during standby and is connected to the gates of N-channel transistors Qll and Ql2. It's visible. During standby, the reference voltage (a voltage approximately halfway between the sense amplifier's "φ" judgment level and "1" judgment level) + (N-channel transistors Qll, Ql2)
A predetermined potential is applied to the bit line by applying a threshold voltage of Qll and Ql2 to the gates of Qll and Ql2.

〔Effect of the invention〕

As described above, according to the present invention, the bit line and the reference line are equalized during standby, and are set to an intermediate level between the "φ" judgment level and the ``11 judgment level of the sense amplifier, so that any access method can be used. It becomes faster.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a differential sense amplifier circuit and its auxiliary circuits which are one embodiment of the present invention, and FIG. 2 is a flow chart showing the operation of the circuit of FIG. 1. A circuit diagram of a differential sense amplifier circuit and its auxiliary circuits showing an embodiment. FIG. 4 shows the connections of the differential sense amplifier circuit, bit line decoder, memory cell, and comparison memory cell of a conventional nonvolatile semiconductor device. FIG. In the figure, 11) and (2) are inverters, Ql,
Qa is a P-channel transistor, Q2 to Q17 are N-channel transistors, and Ml is a floating gate transistor (
(memory transistor), square indicates a floating gate transistor for comparison, and 4 indicates a reference circuit. In addition, the same symbols in the figures indicate the same or equivalent parts. Figure 1 Enclosure 1.2 Inverter Qr, Qa: P10-F) Retransistor Q2-On:
N-type transistor Mt': 8M gate transistor (memory transistor) /'IzJ floating gate for comparison)

Claims (1)

[Claims] In a differential sense amplifier circuit having a bit line of a memory array consisting of floating gate transistors and a reference line having a floating gate transistor for comparison, the bit line and the reference line are equalized during standby, and the sense amplifier 1. A nonvolatile semiconductor memory device characterized in that the voltage is set to an intermediate voltage between a "φ" determination level and a "1" determination level.