JP2668150B2 - Nonvolatile semiconductor memory device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device including a floating gate transistor.

[Conventional technology]

FIG. 4 is a circuit diagram showing the connection of an operation type sense amplifier circuit and a bit line decoder, a memory cell, and a comparison memory cell of a conventional nonvolatile semiconductor memory device.
Is a floating gate transistor whose control gate is connected to the word line WL, and M2 is a word line
Floating gate transistor for comparison connected to WL, 3 is a bit line decoder for selecting one bit line among a plurality of bit lines in which a plurality of floating gate transistors M1 are connected in parallel, and 1 is a bit line Decoder 3 and input B
Inverter connected at a point, Q3 is the output of inverter 1 connected to the gate, drain and source are power supply,
An N-channel transistor connected to point B, Q2 has a gate, a drain, and a source, each of which is the output of the inverter 1,
N channel transistor connected to D point and B point, Q1 is P channel transistor whose gate, drain and source are respectively connected to D point, D point and power supply, Q9 and Q10 are N channel whose gate is connected to power supply Channel transistor, 2 is an inverter whose input is connected at the point C, Q8 is the output of the inverter 2 is connected to the gate, drain and source are the power source, N channel transistor connected to the point C, Q7 is the gate and drain, The source is an N-channel transistor connected to the output of the inverter 2, the points E and C, respectively.
Is a P-channel transistor whose gate, drain, and source are connected to point E, point E, and a power supply, respectively.

Next, the operation will be described. First, in the memory transistor M1 composed of a floating gate transistor, charge is accumulated in the floating gate by the stored information, and the word line W.
There is a state where the threshold voltage is high that does not become conductive even when L is selected, and a state where the threshold voltage becomes low when the word line WL is selected because the charge accumulated in the floating gate is erased by ultraviolet rays. It has two states. In the bit line decoder 3 to which the plurality of memory transistors M1 and M2 are connected, the selection is made by the N-channel transistors Q4 and Q5 being turned on by the selection signals a1 and a2. In addition, memory transistors are connected by word lines WL.
When M1 is selected, the potential of the bit line becomes equal to that of inverter 1 and N
The feedback type bias circuit constituted by the channel transistor Q3 has a predetermined amplitude depending on whether or not the memory transistor M1 is conductive. This voltage amplitude appears at the point B via the bit line selection decoder 3, and the N channel transistor Q2
Is in a non-conductive state when the potential at the point B is higher than a predetermined voltage, and is in a conductive state when the potential is lower than the predetermined voltage. If Q2 is in a non-conducting state, the P channel transistor Q1 causes point D to be (power supply level)-
(Q1 threshold voltage) level appears. If Q2 is conducting, the conduction resistance of P-channel transistor Q1 and Q
2, a potential divided by the ratio of the conduction resistance of the entire Q4, Q5, and M1 appears. On the other hand, a floating gate transistor M2 for comparison, N-channel transistors Q7, Q8, Q9, Q10, P-channel transistors
Q6 and the inverter 2 have the same configuration, M2 is a conductive floating gate transistor, and point E is Q6, Q7, Q9, Q
The potential divided by the ratio of the conduction resistance of 10, M2 appears. This potential is input as a reference voltage of the differential sense amplifier. That is, the levels of points E and D are compared, and points E and D are compared.
A small potential difference at a point is greatly amplified and output.

[Problems to be solved by the invention]

Since the conventional non-volatile semiconductor memory device is configured as described above, the memory cell current decreases due to the reduction in memory cell size accompanying the high integration. Therefore, charging of the N-channel transistor Q3 for charging the bit line is performed. The capability must be reduced, and the time required to charge the bit line from the GND level to a predetermined potential becomes longer, which hinders high speed operation.

The present invention has been made to solve the above problems, and has as its object to obtain a high-speed nonvolatile semiconductor memory device even when a memory cell is reduced.

[Means for solving the problem]

According to a nonvolatile semiconductor memory device of the present invention, in a differential sense amplifier circuit having a bit line of a memory array composed of floating gate transistors and a reference line having a floating gate transistor for comparison, a bit line and a reference line are provided. The equalization is performed during standby, and the voltage is set to an intermediate voltage between the “φ” determination level “1” determination level of the sense amplifier.

[Action]

In the differential sense amplifier according to the present invention, the bit line and the reference line are equalized during standby, and the voltage of the bit line and the reference line is set at an intermediate level between the “φ” judgment level and the “1” judgment level of the sense amplifier. The charging time of the reference line is almost negligible and can be accelerated for any access method.

(Example of the invention)

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a circuit diagram of a differential type sense amplifier circuit according to an embodiment of the present invention and its auxiliary circuit. In the figure, Q1
3, Q14, Q15, ... are N channel transistors, threshold voltage V
Utilizing _TH , the power supply voltage is reduced to an intermediate level between the “φ” judgment level and the “1” judgment level of the sense amplifier. Q11 and Q12 are N-channel transistors, a chip enable (e) signal at the gate, a G point at the drain,
The sources are connected to points A and F, respectively. Thus, at the time of standby (e = "H"), the N-channel transistors Q11 and Q12 are turned on, and the bit line and the reference line are charged to a predetermined potential. This state is shown in the timing chart of FIG.

FIG. 3 is a circuit diagram showing another embodiment of the present invention. In FIG. 3, reference numeral 4 denotes a reference voltage generating circuit.
It is connected to the gates of the channel transistors Q11 and Q12. In the standby mode, apply the reference voltage (a voltage between the “φ” judgment level and the “1” judgment level of the sense amplifier) + (threshold voltage of N-channel transistors Q11 and Q12) to the gates of Q11 and Q12. Thus, a predetermined potential is applied to the bit line.

〔The invention's effect〕

As described above, according to the present invention, during standby, the bit line and the reference line are equalized,
In addition, by setting the sense amplifier at an intermediate level between the “φ” determination level and the “1” determination level, the speed is increased in any access method.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a differential sense amplifier circuit and an auxiliary circuit thereof according to an embodiment of the present invention, FIG. 2 is a flowchart showing the operation of the circuit of FIG. 1, and FIG. FIG. 4 is a circuit diagram of a differential sense amplifier circuit and an auxiliary circuit thereof according to another embodiment. FIG. 4 shows a differential sense amplifier circuit and a bit line decoder, a memory cell, and a comparison memory cell of a conventional nonvolatile semiconductor device. FIG. 4 is a circuit diagram showing connection. In the figure, (1) and (2) are inverters, and Q1 and Q6 are P
A channel transistor, Q2 to Q17 are N channel transistors, M1 is a floating gate transistor (memory transistor), M2 is a floating gate transistor for comparison, and 4 is a reference circuit. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

(57) [Claims] A floating gate transistor connected to the bit line and forming a memory cell; a reference line; and a floating gate transistor connected to the reference line and forming a memory cell for comparison. A differential sense amplifier circuit connected to the bit line and the reference line, equalizing the bit line and the reference line during standby, and determining the “φ” determination level of the differential sense amplifier circuit to “1”. "Equalizing means for setting the voltage to about the middle of the judgment level, the equalizing means having a source / drain connected to the bit line, a first transistor turned on during the standby, and the reference Has source / drain connected to line , A second transistor turned on during the standby, and a third transistor diode-connected between a power supply and another source / drain of each of the first and second transistors. Semiconductor storage device.