JPS63183687A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To execute a readout operation at a high speed by transferring the potential of a complementary data line to a complementary common data line through an amplifying MOSFET provided in accordance with the respective complementary data lines. CONSTITUTION:At the time point when a selecting operation for word lines W0-Wm has been ended, timing signals phipa1, phipa2 are activated and a sense amplifier SA is activated, and readout signals outputted to complementary data lines D0, the inverse of D0 from a memory array M-ARY are amplified by the amplifier SA and become quickly binary readout signals. There readout signals are transferred to complementary common data lines CD, the inverse of CD through amplifying MOSFETs Q7, Q15, Q8, Q16-Q9, Q17, Q10 and Q18 of a column switch CSW, and amplified by a main amplifier MA. Therefore, the amplifying action of the readout signal by the amplifier SA is not affected by the floating capacity of the data lines CD, the inverse of CD. Accordingly, a readout operation as a dynamic type RAM is executed at a high speed.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a semiconductor memory device, for example,
The present invention relates to a technique effective for use in a dynamic RAM (random access memory) in which a sense amplifier is provided corresponding to each data line forming a memory array.

[Conventional technology]

The memory array of the dynamic RAM is composed of a so-called one-element type dynamic memory cell consisting of a capacitor for information storage and a MOS FET for address selection, and storage data of logic 11" or logic "0" is stored as information storage. The information stored in the memory cell is read out according to the amount of charge in the information storage capacitor Cs.The information stored in the memory cell is read by turning on the address selection MOSFET and changing the potential of the complementary data line depending on the amount of charge in the information storage capacitor C3. It is done by changing or sensing.

In order to amplify such minute read signals, a latch-type sense amplifier is provided corresponding to each data line. The read signals amplified by these sense amplifiers are selected by column switches and output to the outside, and are used to refresh the data stored in the memory cells.

A dynamic RAM including such a sense amplifier is described in, for example, Japanese Patent Laid-Open No. 57-82282.

(Problems to be Solved by the Invention) In the dynamic RAM as described above, as shown in FIG. 3, the word line selection operation is performed by the row address decoder RDCH in accordance with the word line selection timing signal φX, A data line selection operation is performed by column address decoder CDCR and column switch C8W according to timing signal φy. Also, sense amplifier SA provided corresponding to each data line is activated according to timing signal φpa. These timings The signals have a time relationship as shown in FIG. 4, and the minute read signal output from the memory cell is amplified.

That is, first, the word line selection timing signal φX is set to a high level, so that a predetermined word line is set to a high level selected state, and the minute read signal of the memory cell coupled to that word line is transferred to the corresponding complementary data line ( For example, the 0th order timing signal φpa (or inverted timing signal φpa) output to the complementary data lines DO (DO) is set to a high level (or a hollow level), and the sense amplifier SA is put into an operating state. As a result, the level of the complementary data line is rapidly changed to high level or low level. When the amplification operation by the sense amplifier SA is completed, the data line selection timing signal φy is set to high level, and the data line selection signal generated by the column address decoder CDCR is synchronized with the high level of this timing signal φy. (for example, YO) becomes high level. This results in
Only the complementary data line designated by the column address signal is connected to the complementary common data line CD-CD, and its read signal is output from the output terminal Dout via the main amplifier MA and data output buffer DOB.

In this way, in the dynamic RAM, since a relatively large floating capacitance 1c exists in the complementary common data line CD-σ, the minute read signal output from the memory cell is sufficiently amplified by the sense amplifier SA. After the levels are established, it is necessary to connect to the complementary common data line CD-CD. Therefore, as shown in FIG. 4, from the time when the word line selection timing signal φX is set to high level and the word line selection operation is started until the time when the data line selection timing signal φy is set to high level and the data line selection operation is performed. During the predetermined time 'l' x y
As the capacity of dynamic RAM increases and the stray capacitance of the complementary common data line CD/σ increases, this time T This is a factor that hinders

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device capable of speeding up read operations.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

(Means for Solving the Problems) A brief overview of typical inventions disclosed in this application is as follows.

That is, the potential of the complementary data line is transmitted to the complementary common data line via the amplification MOSFET provided corresponding to each complementary data line.

[For production]

According to the above means, since the potential of the complementary data line is transmitted to the complementary common data line via the amplification MOSFET with high input impedance, the minute read signal output to the complementary data line is present on the complementary common data line. Since the signal is amplified without being affected by stray capacitance, the word line selection operation and the data line selection operation can be performed simultaneously, and the read operation of the dynamic RAM can be made faster.

〔Example〕

FIG. 1 shows a dynamic RA to which this invention is applied.
A circuit block diagram of one embodiment of M is shown. Each circuit element in the figure is formed on a single semiconductor substrate such as, but not limited to, single crystal silicon using a known CMO5 (complementary MO5) integrated circuit manufacturing technology. In the figure, a MOSFET with an arrow added to the channel (bank gate) portion is a P-channel type, and is distinguished from an N-channel MOSFET without an arrow added.

In FIG. 1, although not particularly limited, memory array M
-ARY is a two-intersection (folded bit line) system, and n+1 sets of complementary data lines D are arranged in the horizontal direction in FIG.
m+1 word lines WO to Wm arranged perpendicularly to O-DO to Dn-1 and (m+1)X (n+
1) Consisting of memory cells. Each complementary data line has a complementary data line DO・■1 and Dn・1
As shown in the example, the address selection MOSFE
m+1 one-element type dynamic memory cells each consisting of TQm and an information storage capacitor Cs are coupled with a predetermined regularity.

A precharge circuit PC consisting of switch MOSFETs represented by MOSFETs QI9 and Q20 is provided between the non-inverted signal line and the inverted signal line of each complementary data line. The gates of these switch MOSFETs are commonly connected, and a timing signal φpc is supplied from a timing control circuit TC, which will be described later. timing signal φp
In the non-operating state of the dynamic RAM where c is at high level, the switch MOSFETs QI9 to Q20
is turned on, and both signal lines of the complementary data line are short-circuited. As a result, both signal lines of the complementary data line are set to a half precharge level of approximately 1/2 of the power supply voltage Vcc. Therefore, the levels of both signal lines of each complementary data line are changed from this half precharge level toward a high level or a low level in accordance with the read signal, thereby speeding up the read operation.

Each complementary data line constituting the memory array M-ARY is
It is coupled to an input/output node of a corresponding unit circuit of sense amplifier SA.

In the dynamic RAM of this embodiment, in order to further speed up the read operation, activation of the sense amplifier SA and data line selection operation are performed simultaneously. That is,
A data line selection timing signal φy for causing the column address decoder CDCH to perform a data line selection operation is generated simultaneously with a timing signal φpal for driving the sense amplifier. In addition, in order to prevent the amplification operation of the minute read signal of the memory cell by the sense amplifier SA from being affected by the stray capacitance of the complementary common data line CD-5, each complementary data line and the corresponding switch MOSFET of the column switch C8W are connected. A signal transmission means (connection means) having high input impedance is provided between the pair. In this embodiment, an amplification MOS FET as a signal transmission means having an amplification function is provided in accordance with the above characteristics. These amplification MOSFETs are formed adjacent to the MOSFETs forming the two CMOS inverter circuits of each unit circuit of the sense amplifier SA, although they are not particularly limited.

In FIG. 1, sense amplifier SA is composed of n+1 unit circuits. Each unit circuit of the sense amplifier SA is a P-channel MOSFET, as exemplarily shown in the unit circuit corresponding to the complementary data line DO.
Q3. Q4 and N-channel MOSFET QI 1. Q
It is constituted by a CMOS latch circuit formed by cross-connecting two sets of CMOS inverter circuits consisting of l2.

The input/output nodes of this CMOS latch circuit are respectively coupled to five non-inverted signal lines DO and five inverted signal lines of the corresponding complementary data lines.

Two sets of CMOs that constitute each unit circuit of sense amplifier SA
Each S inverter circuit has an amplification MOSFETQ7.
- Ql 5 and Q8-Ql6 are provided in parallel form.

Amplification MOSFETQ? -Ql5 and Q8/Ql6 are each connected in series, and their respective gates and sources are commonly connected to the gates and sources of the corresponding MOSFETs Q3/Qll or Q4/Ql2 of the sense amplifier SA.

Also, MOS FETQ? The commonly connected drains of Q15 and Q15 are coupled to the non-inverting signal line CD of the complementary common data line via the corresponding switch MOSFET Q21 of the column switch C8W. This allows the amplification MOS
FETQ?・Ql5 is the inverted signal line 5τ of the complementary data line
By inverting the potential of the non-inverting signal line CD of the complementary common data line
It acts as a CMOS inverter circuit to transmit data to. Similarly, the commonly connected drains of MOSFETs Q8 and Ql6 are connected to the corresponding switch M of column switch C8W.
It is coupled to the inverted signal line (1) of the complementary common data line via OSFETQ22. Thereby, Q8 and Ql6 act as a CMOS inverter circuit that inverts the potential of the non-inverted signal line DO of the complementary data line and transmits it to the inverted signal line of the complementary common data line.

The two sets of inverter circuits and the two sets of amplification MOSFETs that constitute the unit circuit of the sense amplifier SA include, but are not particularly limited to, parallel type P-channel MOSFETs QI,
Power supply voltage Vcc is supplied through Q2, and N
Channel MOSFETQ29. The ground voltage of the circuit is supplied through Q10. These driving MO5)'ETQ
1. Q2 and MOSFET Q29. Q30 is a unit circuit and amplification MOSFET provided in the same memory mantle.
Commonly used for. That is, the unit circuit of the sense amplifier SA and the amplification MO included in the same memory mat
The sources of the P-channel MOSFET and the N-channel MOSFET constituting the SFET are commonly connected to a common source line ps or n3, respectively.

Drive MOSFETQ1. A complementary timing signal φp for activating the sense amplifier SA is connected to the gate of Q29.
a 1 , φpal is supplied, MOSFETQ2
．． The gate of Q30 receives the complementary timing signal φpa.
1. #I) Complementary timing signals φpaL and φpa2 formed slightly later than a are supplied. As a result, the operation of the sense amplifier SA is performed in two stages. That is, complementary timing signal φpa 1 + # pa
In the first stage when 1 is supplied, MOSFET QI and Q29, which are made to have a relatively small conductance, are turned on, and their current limiting action causes
The minute read voltage applied from the memory cell to the corresponding complementary data line is amplified without undergoing any undesired level fluctuation. A timing signal φpa2e 111 is supplied.

This results in a MOS with relatively large conductance.
FETQ2. Q30 is turned on. sense amplifier S
The amplification operation of sense amplifier A is accelerated by turning on MOSFET Q2゜Q30, and the level of the complementary data line rapidly changes to high level or low level. In this way, the amplification operation of sense amplifier SA is performed in two stages. By performing the reading separately, data can be read out at high speed while preventing undesired level changes in the complementary data lines.

On the other hand, the potential of the complementary data line amplified by the sense amplifier SA is the potential of the amplification MOSFETQ?・Q15～QIO・
It is transmitted by Ql8 to the corresponding switch MOSFET pair of column switch C8W. That is, for example, the potential of the non-inverted signal DO of the complementary data lines DO/DO is
It is inverted by OSFETQ4 and Ql2, and transmitted to the inverted signal line CD of the complementary common data line via the switch MOSFETQ22 of the column switch Csw.

Similarly, the potential of the inverted signal line 1 is the amplification MOSFETQ
3.Qll, and is transmitted to the non-inverted signal line CD of the complementary common data line via the switch MOSFET Q21 of the column switch CSW.

The input/output nodes of each unit circuit of the sense amplifier SA, that is, each complementary data line, are further connected to the switch MOS FET pairs Q25/Q26 to Q27/Q2 of the column switch CSW.
Combined with 8.

As described above, in the dynamic RAM of this embodiment, in the read operation mode, the read signal is transmitted through the amplification MOS FET provided corresponding to each complementary data line.
The data is transmitted to complementary common data lines CD and CD via the data lines CD and CD. Therefore, in the write operation mode, the same signal path cannot be used. Therefore, in the write operation mode of the dynamic RAM, the complementary common data line CD-CD and the selected complementary data line are amplified by the MOSFET.
Switch MOS for connection without going through ET
FET pairs Q25, Q26 to Q27, Q2B are provided in column switch C8W.

These switch MOSFET pairs Q25, Q26~Q2
7.Q28 and the switch MOSFET pair Q21.Q22 to which the output terminal of the aforementioned amplification MOS FET is coupled.
The gates of Q23 and Q24 are connected in common and supplied with data line selection signals YWO~'fwn or YrO~Yrn formed by a column address decoder CDCH. Among these data line selection signals, data line selection signals YwO to Ywn are used as Y address signals AYO to A in the write operation mode of the dynamic RAM.
Only one line corresponding to the data line designated by Yi is set to high level. Also, data F+tiM selection signal Y
Only one of rO to Yrn corresponding to the data line specified by the Y address signals AYO to AYi is set to high level in the read operation mode of the dynamic 7-type RAM.

Column address decoder CDCR receives complementary internal address signal a supplied from column address buffer CADB.
yO~ayi (Here, for example, external address signal AY
The internal address signal ayO, which is in phase with O, and the internal address signal ayQ, which is in opposite phase, are collectively expressed as a complementary internal address signal ayQ (hereinafter the same) is decoded, and the timing control circuit T
Data line selection signals YWO to Y according to data line selection timing signal φy and internal control signal we supplied from C
Wn and YrO to Yrn are formed, and column switch C8
Supply to W. That is, column address decoder CD
CR is connected to data line selection signals YWO to Yw in the write operation mode in which the internal control signal we is at a high level.
In a read operation mode in which any one of the data line selection signals YrO to '/wr is set to a high level and the internal control signal we is set to a low level, one of the data line selection signals YrO to '/wr is set to a high level. These data line selection signals are
It is set to high level in synchronization with the data line selection timing signal φy.

In the dynamic RAM of this embodiment, as described above, the timing signal φpal for activating the sense amplifier SA and the data line selection timing signal φy are simultaneously set to high level. Further, in the read operation mode, the potential of the complementary data line is transmitted to the complementary common data line CD-n via the amplification MOSFET. For this reason,
Complementary common data line CD-τ with relatively large stray capacitance
Even though the lower end is connected to the complementary data line specified at the same time as the activation of sense amplifier SA, the minute read signal output to the complementary data line is connected to the complementary common data line CD-
It is amplified without being affected by the stray capacitance of σ■, and the read operation of the dynamic RAM is accelerated.

The column address buffer CADB has input terminals AO to A.
Y address signals AYO to A supplied via i in synchronization with the falling edge of the column address strobe signal CAS.
It receives Yi and forms complementary internal address signals ayQ to ayi. Complementary internal address signals ayQ to upper yi are supplied to column address decoder CDCH. Y address signal AYO~ in column address banff 7CADB
The capture operation of AYi is performed in accordance with a timing signal φac (not shown) generated by detecting one falling edge of the column address strobe signal in the timing control circuit TC.

--On the other hand, the gates of the address selection MOSFETs QnL of memory cells arranged in the same row of the memory array M-ARY are coupled to the word line WQ --Wm of the corresponding address. Word lines WO to Wm are coupled to a row address decoder, and one of them is selected and designated.

Although not particularly limited, the row address decoder has a two-stage structure, consisting of a secondary row address decoder RDCRi and a secondary row address decoder RDCR2.
The next row address decoder RDCR1 decodes the complementary internal address signals aXO and axl of the lower two bits, and generates four word line selection timing signals φ synchronized with the timing signal φX supplied from the timing control circuit TC.
xoO to φxll are formed. These word line selection timing signals are combined with a common selection signal formed by the secondary row address decoder RDCR2 that decodes the complementary internal address signals ax2 to axi except for the lower two bits, so that the X address signal AXO=
A word line selection signal (WO to W m ) for selecting one word line designated by AXi is formed.

By configuring the row address system selection circuit in two stages as described above, it is possible to match the layout pitch (spacing) of the unit circuits of the secondary row address decoder RDCR2 with the layout pinch of the word line. The above layout can be made more efficient.

The row address buffer RADB receives a row address signal supplied from the address multiplexer AMX,
While holding it, the complementary internal address signal aXO
〜Upper xi is formed to form a primary row address decoder RDC.
R1 and the secondary row address decoder RDCR2.

By the way, the dynamic RAM of this embodiment is provided with an automatic refresh mode for reading and rewriting data stored in memory cells within a predetermined cycle.
A refresh address counter REFC is provided for specifying a word line to be refreshed in this automatic refresh mode. The address 4 multiplexer AMX is supplied with an X address signal AXO=AXt supplied via external terminals AO to Ai or a rerange air address counter REFC according to internal control signals re and f supplied from the timing control circuit TC. The ref-ref shared address signals CXO to Cxt are selected and transmitted to the row address buffer RADB as a row address signal. That is, in a normal memory access mode in which the internal 1aJ control signal ref is at a low level, X address signals AXO to AXi supplied from an external device via external terminals AO to Al are selected, and the internal control signal ref is selected.
In the automatic refresher mode in which the refresher address counter REFC is set to a high level, the refresher address signals CXO to cxi output from the refresher address counter REFC are selected.

Since the X address signals AXO to AXi are supplied in synchronization with the fall of the row address strobe signal RAS supplied as a control signal from the outside, the acquisition of the row address signal by the row address buffer RADB is controlled by the timing control circuit TC. This is performed in accordance with a timing signal φar<not shown) which is generated by detecting the fall of the row address strobe signal RAS.

Next, the common complementary data line CD − to which the complementary data line specified by the column switch C8W is selectively connected
CD is coupled to the input terminal of main amplifier MA and to the output terminal of data input buffer DIB. The output terminal of main amplifier MA is further coupled to the input terminal of data output buffer DOB.

The main amplifier MA is brought into operation by the high level of the timing signal φ-a supplied from the timing control circuit TC, and the main amplifier MA is activated by the high level of the timing signal φ-a supplied from the timing control circuit TC.
The read signal inputted through the OSFET and the complementary common data line CD-τ is further amplified and transmitted to the data output buffer DOB.

In the read operation mode of the dynamic RAM, the data output buffer DOB is connected to the timing control circuit TC.
The main amplifier MA is activated by the high level of the timing signal φr supplied from the main amplifier MA, and outputs the output signal of the main amplifier MA to the data output terminal Dout. Dynamic type R
In the AM non-operation state or write operation mode, the output of the data output buffer DOB is placed in a high impedance state.

The data input buffer DIB is a dynamic RAM
In the write operation mode, the timing signal φW is set to the high level and the data input terminal D is activated.
The write data supplied from in is made into a complementary write signal and is supplied to the complementary common data line CD-CD. These complementary write signals are sent to the write switch MOSFET pairs Q25, Q26 to Q27, and the column switch C8W.
It is supplied to the selected complementary data line and memory cell via Q2B. When the dynamic RAM is in a non-operating state or in a read operation mode, the output of the data input buffer DIB is placed in a high impedance state.

The refresh address counter REFC operates in the automatic refresh operation mode of dynamic RAM, and is timing-based! A refresh address signal cxQNc for counting the timing signal φC supplied from the 11 circuit TC and specifying a word line to be refreshed.
xi and supplies it to the address multiplexer AMX.

The timing control diagram 123Tc forms the various internal control signals and timing signals mentioned above based on the row address strobe signal AS, column address strobe signal CAS, and write enable signal WE supplied as control signals from the outside, and supplies them to each circuit. .

FIG. 2 shows a timing diagram of an embodiment in the read operation mode of the dynamic RAM of this embodiment. According to the same figure, the dynamic type R of this embodiment
An outline of the AM read operation will be explained.

In FIG. 2, the Dyna<+7 type RAM is activated by changing the row address strobe signal RAS from high level to low level. Prior to the fall of the row address strobe signal Tw, a write enable signal Wπ (not shown) is set to a high level, and the external terminals AO to Ai are connected to the X address signal AXO-A.
Xi is supplied. Also, a little later than the row address strobe signal H, the column address strobe signal CA
S is changed from high level to low level.

Prior to the fall of the column address strobe signal δ Cτl, the Y address signal AYO''AYi is supplied to the external terminals AO to Ai.

In the dynamic RAM of this embodiment, the time from the fall of the row address strobe signal RAS to the fall of the column address strobe signal CAS is set regardless of the address selection operation and read signal amplification operation in the dynamic RAM. be done. In other words, row address buffer RADB and column address buffer C
The row address strobe signal r
τ1 and the falling interval of the column address strobe signal CAτ, that is, the RAS·στ delay time Trcd are set.

In the dynamic RAM, timing signal φar is generated by the fall of row address strobe signal RAS, and X address signals AXO to AXi are taken into row address buffer RADB. Also, a little later than this timing signal φar, the word line selection timing signal φX is set to high level, and the row address decoder R
A word line selection operation by DCH is started. As a result, each complementary data line (for example, complementary data line DO/DO)
Before the sense amplifier SA operates, a minute read signal is output from the memory cell coupled to the selected word line.

Next, timing signal φac is formed by the fall of column address strobe signal CAS, and Y address signals AYO to AYi are sent to column address buffer CAD.
It is taken into B.

At the point when the word line selection operation is completed, the sense amplifier SA
Timing signals φpal and φpa for activating
2 is formed, and the data line selection timing signal φy is set to high level. As a result, the minute read signal output to the complementary data line DO is amplified by the corresponding unit circuit of the sense amplifier SA, and rapidly
It is a binary read signal of 1 high level or low level. These 21A=! The protruding signal is column switch C.
The signal is transmitted to the complementary common data lines CD-CD via a pair of 5W read switches MOSFE'I', and further amplified by the main amplifier MA.

At the point when the amplification operation by the main amplifier M A is completed,
An evening timing signal ψr is formed. Due to the high level of this timing signal φr, the °C data output vanofer DO
B is in the operating state, and the read data is output to the output terminal Dou.
It is output from t to an external device.

As described above, in the dynamic RAM of this embodiment, the potential of the corresponding complementary data line is connected to the complementary common data line CD.
- Amplified MO3F ETQ 7 for transmitting to CD
Q15. QB・QI6～Q9・Q17, QIO・QIO
is provided, and at the same time as sense amplifier SA is activated by timing signals φpal and φpa2, data line selection operation by column address decoder CDCR and column switch C8W is started. Therefore, the complementary common data line CD/
Although the CD is connected at the same time as the sense amplifier SA is activated, the read signal amplification operation by the sense amplifier SA is not affected by the stray capacitance of the complementary common data line CD-CD. R.A.
The read operation as M is accelerated and its access time is shortened.

As shown in the above embodiment, by applying the present invention to a semiconductor memory device such as a dynamic RAM, the following effects can be obtained. That is, (1) By transmitting the potential of the complementary data line to the complementary common data line via the amplification MOSFET provided corresponding to each complementary data line, the minute read signal output to the complementary data line is This provides the advantage of being able to be amplified by the sense amplifier without being affected by the relatively large stray capacitance coupled to the complementary common data line.

(2) According to the above item (1), it is possible to achieve the effect that the activation of the sense amplifier or the selection operation of the word line and the selection operation of the data line can be performed simultaneously.

(3) According to the above (1) and (2), it is possible to speed up the read operation of the dynamic RAM and shorten the access time.

Although the invention made by the present inventor has been specifically explained above based on examples, this invention is not limited to the above-mentioned examples, and can be modified in various ways without departing from the gist of the invention.) For example, in the embodiment shown in FIG. 1, the activation of the sense amplifier SA and the data line selection operation are performed simultaneously, but the data line selection operation, in other words, the connection operation between the data line and the common data line In other words, it may be performed at the same time as the word line selection operation, in other words, before the sense amplifier starts operating. For example, the word line selection timing signal φX and the data line selection timing signal φy may be set to high level at the same time. There may be. In addition, in the example shown in FIG. 1, the writing switch MOSFET pair and the reading switch MOSFET pair of the column switch C3W are provided separately, and the writing is performed using a common complementary common data line CD-σ stone. Although signals and read signals are transmitted, it is also possible to provide separate complementary common data lines for writing and complementary common data lines for reading.

The amplification MOSFET may be placed separately from the unit circuit of the sense amplifier SA, or the P-channel MOSFET of the amplification MOSFET may be placed in common for each non-inverting signal line of the complementary common data line and the anti-K (line 8). In this case, other load means such as a high resistance may be used instead of a P-chaff single-channel MOSFET. It is desirable to provide a short-circuiting N-channel MOSFET that receives the timing signal φpc at its gate between the two signal lines. In this case, the potential of both signal lines of the complementary common data line in the chip non-selected state is It is set to Vcc/2, which is equal to the level.

In addition to the high input impedance of the connection means, by making these potentials almost the same, it is possible to prevent potential fluctuations on the complementary data line when the complementary data line and the complementary common data line are connected before the sense amplifier starts operating. . Furthermore, the dynamic RAM shown in FIG. 1 has different circuit block configurations and control signal combinations, for example, the memory array is configured with multiple memory mantles, and multiple focus points can be written or read at the same time. Various embodiments are possible.

In the above explanation, the invention made by the inventors of the present application was mainly applied to the Dina E7 type RAM, which is the background field of application, but the invention is not limited to this. type RAM
The present invention can also be applied to various semiconductor memory devices such as a pseudo-imaging static RAM which has a structure that can be used compatible with a static RAM. The present invention can be widely applied to semiconductor devices including cliff conductor memory devices having sense amplifiers and such semiconductor memory devices.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. That is, by transmitting the potential of the complementary data line to the complementary common data line via the amplification MOS FET provided corresponding to each complementary data line, the minute read signal output to the complementary data line is transmitted to the complementary common data line. Semiconductor memory This makes it possible to speed up the read operation of the device.

[Brief explanation of the drawing]

Figure 1 shows a dynamic RAM to which this invention is applied.
FIG. 2 is a timing diagram showing an example of the read operation of the dynamic RAM shown in FIG.
Figure 4 is a circuit block diagram showing an example of the M memory array and its peripheral circuits. FIG. 3 is a timing diagram showing a read operation of the dynamic RAM shown in the fsa diagram. M-ARY...Memory array, PC...Precharge circuit, SA...Sense amplifier, C8W...Column switch, RDCR1...Primary row address decoder, RDCR2...Secondary row address decoder , CDC
R...Column address decoder, RADB...Row address buffer, AMX...Address multiplexer, CADB...Column address buffer, MA...
・Main amplifier, DOB...data output cover sofa, D
IB...Data input buffer, REFC...Refresh counter, TC...Timing control circuit. Cs...Capacitor for information convexity, Qm...Address selection MOSFET, Q2~Q, 10. Q
31~Q33...P channel MOSFET, Q1~Q30. Q34~Q3B...N channel MOSF
E.T. lg＼、

Claims (1)

[Claims] 1. A sense amplifier provided corresponding to a data line constituting a memory array and amplifying a read signal of a memory cell, and a plurality of amplifying MOSFETs whose gates are coupled to the corresponding data line. , a semiconductor memory device comprising a column switch that selectively transmits the output signal of the amplification MOSFET to a common data line. 2. The above sense amplifier has two sets of CMOs that are cross-connected.
It is composed of an S inverter circuit, and the above amplification MOSFE
T is commonly connected to a P-channel MOSFET and an N-channel MOSFET constituting two sets of CMOS inverter circuits of a sense amplifier whose gates and sources are coupled to corresponding data lines, respectively, and whose commonly connected drains are connected to each other. Claim 1, characterized in that it is constituted by two sets of series-type P-channel MOSFETs and N-channel MOSFETs respectively coupled to the non-inverting signal line and the inverting signal line of the corresponding common data line. semiconductor storage device. 3. The column switch is set to a selected state before the sense amplifier is activated in a read operation of the semiconductor memory device, claim 1 or 2. The semiconductor storage device described above. 4. The semiconductor memory device according to claim 1, 2, or 3, wherein the semiconductor memory device is a dynamic RAM.