JP3284281B2 - Semiconductor storage device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device,
In particular, the present invention relates to a semiconductor memory device suitable for application to an LSI as an SRAM.

[0002]

2. Description of the Related Art As a semiconductor memory constituted by an LSI, there is known a synchronous SRAM employing a method for increasing the throughput of the LSI. This semiconductor memory includes an input buffer (input latch circuit), an address decoder, a memory cell array, a sense amplifier, and an output buffer (output latch circuit).
The configuration is such that data holding and updating of the latch circuit can be controlled in response to a clock signal from the outside of the LSI.

As a method for improving the data output throughput of a semiconductor memory composed of an LSI, a method using a pipeline method is known.

[0004]

SUMMARY OF THE INVENTION Synchronous SRAM
Attempts have been made to shorten the access time when increasing the throughput of the semiconductor memory configured with the above. However, in order to shorten the access time of the semiconductor memory, it is necessary to increase the speed of each part of the semiconductor memory. . However, since the speed of the address decoder, the memory cell, and the sense amplifier is in a trade-off relationship with the memory capacity of the semiconductor memory, the speed of the address decoder, the memory cell, and the sense amplifier is reduced as the capacity of the semiconductor memory increases. Has been adopted. Further, it is impossible to make the cycle time of the synchronous SRAM shorter than the time required for data to be transferred from the input latch circuit to the output latch circuit. The minimum cycle time is determined. For this reason, it is difficult to further reduce the cycle time in the conventional semiconductor memory constituted by the synchronous SRAM.

On the other hand, in a semiconductor memory to which the pipeline system is applied, an internal circuit such as a decoder and a sense amplifier that can operate at a speed similar to that of a high-speed external signal is required. In addition, a data latch circuit must be provided in the internal circuit of the LSI chip, and the chip size increases as the circuit scale increases. As the chip size increases, the memory capacity decreases for the same chip size.

An object of the present invention is to provide a semiconductor memory device capable of inputting or outputting a large amount of data within one cycle time.

[0007]

In order to achieve the above object, the present invention provides a plurality of address input buffers for receiving an address signal and a reference clock signal, and holding and outputting the address signal in response to the reference clock signal. A plurality of address decoders for decoding an output signal of each address input buffer; and a plurality of memory cells each having a plurality of memory cells and outputting data according to an output signal of each address decoder from data stored in each memory cell. The output data of each memory cell array in response to the reference clock signal and the length of the output data during the reference clock signal generation cycle.
And a plurality of data output buffers that sequentially hold and output for different periods of time, and data that selects and outputs output data of each data output buffer in response to a reference clock signal during a generation cycle of the reference clock signal. And a selecting means.

[0008] The in place of the address input buffer of the semiconductor memory device, a plurality of address input buffer for outputting holds the address signal each time the reference clock signal receiving an address signal and the reference clock signal is inputted a plurality of times Can be used.

Instead of each data output buffer of the semiconductor memory device, a plurality of data output buffers for holding and outputting the output data of each memory cell for a fixed time, and outputting the output data of each memory cell in response to a reference signal. It is possible to use a plurality of data output buffers that are shorter than the generation cycle of the reference clock signal or hold the same time and sequentially output the data, and, in addition to these data output buffers, one of the data output buffers of the data output buffer group. An auxiliary data output buffer that holds and outputs output data for a certain period of time, or an auxiliary data output buffer that holds and outputs the output data of one of the data output buffers in the data output buffer group for a certain period in response to a reference clock signal Can also be provided. Instead of the data selection means of the semiconductor memory device, data selection means for alternately selecting and outputting the output data of the other data output buffer and the output data of the auxiliary data output buffer of the data output buffer group, Data selecting means for sequentially selecting and outputting the output data of each data output buffer during the generation cycle of the reference clock signal, and outputting the other data output buffer of the data output buffer group in response to the reference clock signal Data selection means for alternately selecting and outputting data and output data of the auxiliary data output buffer during the generation cycle of the reference clock signal, and holding the output data of each data output buffer in response to the reference clock signal in the address signal Data selection means for sequentially selecting and outputting within the time corresponding to the cycle, or the reference clock signal Data selection means for alternately selecting and outputting the output data of the other data output buffer of the data output buffer group and the output data of the auxiliary data output buffer within a time corresponding to the holding period of the address signal in response to can do.

Next, as a second semiconductor memory device in which the data writing speed is increased, a plurality of address inputs which receive an address signal in synchronization with a clock signal, hold the address signal for a certain period of time, and output it are provided. A buffer, a plurality of address decoders for decoding an output signal of each address input buffer, and a plurality of memory cell arrays for receiving write data and storing the data in a designated storage area according to the output signal of each address decoder; A semiconductor memory device comprising: data input means for inputting write data in accordance with a clock signal; and data write means for writing data input to the data input means to each memory cell array within a write cycle. is there.

As the data input means of the second semiconductor memory device, a plurality of data input means for inputting write data in accordance with a clock signal can be used.
Further, a plurality of data writing means for writing data input to each data input means to a specified memory cell array in a writing cycle can be configured as the data writing means, and the data input to the data input means can be written. A plurality of data writing means for writing data to the designated memory cell array in a cycle can be constituted.

As a layout of each of the semiconductor memory devices, each memory cell array is distributed on a plurality of blocks and arranged on a chip, and each address input buffer and each address decoder are provided in a plurality corresponding to each memory cell array block. , And the address input buffer and the address decoder divided into each block are dispersedly arranged in the vicinity of the memory cell array of each block.

[0013]

According to the above-described means, when an address signal is input to each address input buffer, specified data is output from each memory cell array in response to the address signal. This data is stored in the data output buffer or the auxiliary data output buffer for a certain period of time, and then output sequentially or alternately by the data selection means. Therefore, multiple data can be output within the access time,
The speed at which data is not read can be increased.

On the other hand, when writing data, if the data is input to a single data input means or a plurality of data input means, the input data is written to a designated memory cell array. That is, when viewed from the data input means side, a plurality of data writing processes are performed within the access time, and the data writing speed can be increased.

[0015]

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows a block diagram of a semiconductor memory (semiconductor storage device) configured as an SRAM. In FIG. 1, a semiconductor memory includes address registers 10, 12,
The address register 1 includes decoders 14 and 16, memory cell arrays 18 and 20, sense amplifiers 22 and 24, output registers 26 and 28, an auxiliary output register 30, an output secretor 32, and a clock buffer 34.
The address signal is input to 0 and 12, the clock signal is input to the clock buffer 34, and the address register 1
Clock signals are supplied from a clock buffer 34 to 0, 12, output registers 26, 28, auxiliary output register 30, and output selector 32.

Each of the address registers 10 and 12 is configured as an address input buffer for receiving the address signal, holding the address signal for a predetermined time in response to the rise of the clock signal, and outputting the held signal to the decoders 14 and 16. . Decoders 14 and 16 receive address signals from address registers 10 and 12, respectively, decode the address signals, and store data in memory cell arrays 18 and 2 respectively.
It is configured as an address decoder that outputs a decode signal for selecting a specified memory cell among 0 to the memory cell arrays 18 and 20. The memory cell array 18,
Reference numeral 20 includes a plurality of memory cells as a plurality of data storage areas. In response to decode signals from the decoders 14 and 16, the storage data of the memory cells designated by the decode signals are sent to the sense amplifiers 22 and 24, respectively. It is configured to output. Sense amplifiers 22 and 2
Numeral 4 amplifies output data from each of the memory cell arrays 18 and 20 and outputs the amplified data to output registers 26 and 28. The output register 26 is configured as a data output buffer that holds output data from the sense amplifier 22 for a certain period in response to a clock signal and outputs the held data to the output selector 32. The output register 28 is configured as a data output buffer that holds data from the sense amplifier 24 for a certain period in response to a clock signal and outputs the held data to the auxiliary output register 30. The auxiliary output register 30 is configured as an auxiliary data output buffer that holds output data from the output register 28 for a certain period of time and outputs the held data to the output selector 32. The output selector 32
In response to the clock signal, data from the output register 26 and data from the auxiliary output register 30 are alternately input within one cycle time, and are configured as data selection means for sequentially outputting the input data.

In addition, a register system (R) or a latch system (L) can be used as an address input latch.
A register system (R) or a latch system (L) can be used as an output latch, and four types of combinations can be theoretically configured. The specific operation of the R / R system will be described below. .

FIG. 2 shows a timing waveform inside the semiconductor memory to which the R / R system is applied. In FIG. 2, CL
K represents a clock signal, Address represents an address signal, and WE / represents a write enable signal. These signals are all input from outside the semiconductor memory. Dout indicates an output signal from the semiconductor memory. In this embodiment, the clock signal (CLK) is input as a signal having a period of 6 ns.

First, when the device selection control signal (not shown) is at the low level at the rising time of the clock signal, the state of the address signal and the WE / signal at that time are registered. Then, the address registers 10 and 12 of each block
, An address register clock signal and an address signal are input, and these signals are held until the next rising time of the address register clock. The address register clock signal is a clock signal input from the clock buffer 34 to the address registers 10 and 12 and is generated from an external clock signal (CLK). By the time, a delay of t1 occurs. Each of the address registers 10 and 12 holds the current address signal at its output until the next address signal is input. t
reg 1 is the delay time of the address registers 10 and 12 from the address clock input to the address latch data output. The delay time from each of the address registers 10 and 12 to the sense amplifiers 22 and 24 is tdelay.
Are output as data Dn1 and Dn2 corresponding to. These data are registered in the output registers 26 and 28 at the rising time of the sense register clock, and treg
After being delayed by 2 , the data is output from the output registers 26 and 28. Then, when the sense register clock is at the high level, the output of the output register 26 is output to the output selector 32 as it is. On the other hand, the output data of the output register 28 is input to the auxiliary output register 30 and registered in the auxiliary output register 30 at the falling time of the sense register clock.

Next, when the Dout selector clock goes high, the output selector 32 outputs data Dn1, and when the Dout selector clock goes low, the output selector 32 outputs data Dn2.

As described above, when the address signal is latched at time t1, designated data in memory cell arrays 18 and 20 is selected in accordance with the address signal, and after a delay of tdr1 from the next clock signal rising time t3, the memory is selected. The designated data is output from the cell array 18.
Then, from the falling time t4 of the next clock, tdr2
After the delay, the designated data is output from memory cell array 20. In order to minimize the time during which the output signal of the output selector 32 becomes indefinite when data from each of the memory cell arrays 18 and 20 are alternately output, the output register 2 is used as the timing of the selector clock signal.
It is desirable that the timing be changed after the output of the auxiliary output register 30 is determined.

In the above embodiment, the case where the clock generation cycle is set to 6 ns has been described. However, as shown in FIG. 3, the clock generation cycle is set to 3 ns in the R / R system.
It can also be. In this case, the data output throughput is also 3 ns.

When the semiconductor memory shown in FIG. 1 is applied to the R / L system, the operation timing of each section can be set as shown in FIGS.

In this embodiment, as shown in FIG.
Two data can be output within one cycle time similarly to the above embodiment, except that the output of the data is defined by the rise and fall of the clock signal.

FIG. 5 shows the timing when the clock cycle is 6 ns, and the data output throughput is 6 ns cycle. FIG. 6 shows the timing at a clock cycle of 3 ns, and the data output throughput is 3 ns cycle.

In this embodiment, two memory cell arrays 18 and 20 are provided as memory cell arrays, two address signal input systems and two data output systems are provided, and the output data of the output register 28 is fixed by the auxiliary output register 30. By delaying the time, the data from the output register 26 is output in the first half of the one cycle time, and the data from the auxiliary output register 30 is output in the second half of the time. Data can be output, and data reading speed can be increased.

In the above embodiment, two memory cell arrays are provided and the data output from each memory cell array is output alternately. However, three or more memory cell arrays are provided and the address signal input system is provided in three systems. A register or a register for providing three or more data output systems and holding the data output from each memory cell array for different times during the generation cycle of the reference clock signal and sequentially outputting the data in the data output system. With a latch,
An output selector for sequentially selecting and outputting output data of each register or latch during the generation cycle of the reference clock signal may be provided. In this case, n data can be output within one cycle time, which can contribute to an increase in data reading speed.

As a semiconductor memory, as shown in FIG.
6 can be provided to provide two clock signal input systems.

Next, a semiconductor memory having a data writing function will be described with reference to FIG.

The semiconductor memory according to this embodiment includes a data input buffer 38, a data register 40, and a write circuit 42 in addition to the functions of the semiconductor memory shown in FIG. The data input buffer 38 is configured as data input means for inputting data in response to a clock signal from the clock buffer 34 and outputting the input data to the data register 40. The data register 40 holds the input data for a certain period of time, and transfers the held data to the writing circuit 42.
The write circuit 42 is configured to write data from the data register 40 alternately to designated memory cells of the memory cell array 18 or the memory cell array 20. That is, the data register 40 and the write circuit 42 are configured as data write means for writing data to the memory cell arrays 18 and 20 during a data write cycle.

In this embodiment, as shown in FIG.
Assuming that the clock signal generation cycle is 3 ns, data can be written to the memory cell arrays 18 and 20 within a 6 ns cycle. In this case, the writing time requires twice as long as the reading, so that the present invention can be applied to a device having a long writing cycle.

Next, another embodiment of a semiconductor memory having a data writing function will be described with reference to FIGS.

The semiconductor memory according to this embodiment includes a data input buffer 44, a data register 46, and a write circuit 48 in addition to the functions of the semiconductor memory shown in FIG. That is, the memory cell array 1
In order to write data to 8 and 20 in different systems, 2
A system data writing system is provided.

In this embodiment, when data is input at the same timing, data writing is performed in accordance with the timing shown in FIG. 11, and when data is read every 3n cycles, the timing shown in FIG. Is written according to the following. In either case, data is written to the memory cell arrays 18 and 20 in a write cycle of 3 ns. That is, when viewed from the data input side, one data is written to the memory cell array 18 in the first 3 ns cycle of the 6 ns cycle time, and the other data is written to the memory cell array 20 in the second 3 ns cycle.
This corresponds to two data being written in the ns cycle.

Next, a third embodiment of a semiconductor memory having a data writing function will be described with reference to FIGS.

In this embodiment, the data input buffer 50 is used as a buffer common to each system, and the data register 4 is provided for each system.
0, 46, and write circuits 42, 48, and output data of the data input buffer 50 to the data registers 40, 46.
Output to

In this embodiment, the clock cycle is 6 ns.
Even if data is input every 3 ns cycle according to the following equation, two data writing systems are provided.
Each data can be written in a 3 ns cycle without requiring a 6 ns write time to write each data. Therefore, the write cycle time can be shorter than the minimum time required for writing data to each of the memory cell arrays 18 and 20.

FIG. 15 shows a layout when the semiconductor memory in each of the above embodiments is formed on a chip.
As shown in the figure, the memory cell arrays 18 and 20 are each divided into four blocks of memory cell arrays 18A to 18D and 20A.
20D, the output selector 32 is divided into four blocks of output secretors 32A to 32D, and the blocks divided into the blocks can be dispersedly arranged on a chip. Here, when a 128 k × 36 bit semiconductor memory is configured, the memory cell array 1 of each block is used.
8A to 18D and 20A to 20D respectively output 9-bit data, and 3 bits from the entire chip.
6-bit data is output.

As a layout on a semiconductor memory chip, as shown in FIG.
8 and 20 are each a memory cell array 18 of 4 blocks.
A to 18D and 20A to 20D, and the address registers 10 and 12 are divided into four blocks of address registers 10A to 10D.
10D, 12A to 12D and a decoder 1
4 and 16 are 4 block decoders (not shown)
And a clock buffer 34 is arranged in the center of the chip, and a clock signal from the clock buffer 34 is output to the address registers 10A to 10D and 12A to 12D. can do.

In this embodiment, since the distance between each of the address registers 10A to 10D and 12A to 12D and the decoder is reduced, it is possible to prevent the transmission delay time of the address signal from affecting the cycle time. .

When constructing the decoders 14 and 16, as shown in FIG. 17 and FIG.
0, buffer transistor 62, latch inverters 64, 66, MOS transistors 68, 70, 72, 7
4 and a PMOS transistor 76, 78, 80, 82, an NMOS transistor 84,
86, and a NAND circuit having a bipolar transistor 88.

In the present embodiment, since the logic determined by the combination of the address signals is activated by the clock signal, the input capacitance can be reduced and the threshold value of the logic can be reduced. Address decoder can be realized.

[0043]

As described above, according to the present invention,
Since a plurality of data inputs or outputs are performed within one cycle time, it is possible to contribute to an improvement in data input / output throughput.

[Brief description of the drawings]

FIG. 1 is an overall configuration diagram showing one embodiment of a semiconductor memory.

FIG. 2 is a time chart of each part of the semiconductor memory shown in FIG. 1;

FIG. 3 is a time chart of each part of the semiconductor memory when the R / R method is applied.

FIG. 4 is a time chart of each part of the semiconductor memory when the R / L method is applied.

FIG. 5 is a time chart of a semiconductor memory to which the R / L method is applied;

FIG. 6 is a time chart showing another read timing of the semiconductor memory to which the R / L method is applied;

FIG. 7 is a block diagram of a semiconductor memory when there are two clock input systems.

FIG. 8 is an overall configuration diagram showing a first embodiment of a semiconductor memory having read and write functions.

FIG. 9 is a time chart showing write timing of the semiconductor memory shown in FIG. 8;

FIG. 10 is an overall configuration diagram showing a second embodiment of a semiconductor memory having read and write functions.

11 is a time chart showing a write timing of the semiconductor memory shown in FIG.

12 is a time chart showing another write timing of the semiconductor memory shown in FIG.

FIG. 13 is an overall configuration diagram showing a third embodiment of a semiconductor memory having read and write functions.

FIG. 14 is a time chart showing a write timing of the semiconductor memory shown in FIG. 13;

FIG. 15 is a configuration diagram for explaining a layout configuration of a semiconductor memory;

FIG. 16 is a configuration diagram for explaining another layout configuration of the semiconductor memory;

FIG. 17 is a specific circuit configuration diagram of a decoder.

FIG. 18 is a waveform chart for explaining the operation of the decoder.

[Explanation of symbols]

 10, 12 address register 14, 16 decoder 18, 20 memory cell array 22, 24 sense amplifier 26, 28 output register 30 auxiliary output register 32 output selector 34, 36 clock buffer 38, 44, 50 data input buffer 40, 46 data register 42 , 48 writing circuit

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-4-345993 (JP, A) JP-A-5-81864 (JP, A) (58) Fields investigated (Int.Cl. ⁷ , DB name) G11C 11/40-11/419

Claims (4)

(57) [Claims] A plurality of address input buffers for receiving an address signal and a reference clock signal, holding and outputting the address signal in response to the reference clock signal, and a plurality of address decoders for decoding output signals of each address input buffer And a plurality of memory cell arrays having a plurality of memory cells and outputting data according to an output signal of each address decoder from data stored in each memory cell, and a memory cell array of each memory cell array in response to a reference clock signal. Length of output data during the period of generation of reference clock signal
And a plurality of data output buffers that sequentially hold and output for different periods of time, and data that selects and outputs output data of each data output buffer in response to a reference clock signal during a generation cycle of the reference clock signal. A semiconductor storage device comprising a selection unit. 2. A plurality of address input buffers for receiving an address signal and a reference clock signal and holding and outputting the address signal in response to the reference clock signal, and a plurality of address decoders for decoding output signals of each address input buffer And a plurality of memory cell arrays having a plurality of memory cells and outputting data according to an output signal of each address decoder from data stored in each memory cell, and a memory cell array of each memory cell array in response to a reference clock signal. A plurality of data output buffers for holding and outputting output data shorter than or equal to the generation cycle of the reference clock signal, and output data of one of the data output buffers of the data output buffer group in response to the reference clock signal. Auxiliary data output buffer that holds and outputs for a fixed time and responds to the reference clock signal Data storage means for alternately selecting and outputting the output data of the other data output buffer of the data output buffer group and the output data of the auxiliary data output buffer during the generation cycle of the reference clock signal. apparatus. 3. A plurality of address input buffers for receiving an address signal in synchronization with a clock signal and holding and outputting the address signal for a certain period of time, a plurality of address decoders for decoding an output signal of each address input buffer, and a write operation. A plurality of memory cell arrays for receiving data for writing and storing the data in a specified storage area in accordance with an output signal of each address decoder, data input means for inputting write data in accordance with a clock signal, and input to data input means. And a data writing means for writing the written data to each memory cell array in a write cycle. 4. A plurality of address input buffers for receiving an address signal in synchronization with a clock signal and holding and outputting the address signal for a certain period of time, a plurality of address decoders for decoding output signals of each address input buffer, and writing. A plurality of memory cell arrays for receiving data for writing and storing the data in a specified storage area in accordance with an output signal of each address decoder, data input means for inputting write data in accordance with a clock signal, and input to data input means. And a plurality of data writing means for writing the data to a designated memory cell array within a write cycle.