US7447109B2 - Semiconductor storage device - Google Patents
Semiconductor storage device Download PDFInfo
- Publication number
- US7447109B2 US7447109B2 US11/136,484 US13648405A US7447109B2 US 7447109 B2 US7447109 B2 US 7447109B2 US 13648405 A US13648405 A US 13648405A US 7447109 B2 US7447109 B2 US 7447109B2
- Authority
- US
- United States
- Prior art keywords
- data
- address
- write
- input
- output
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related, expires
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/106—Data output latches
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
- G11C5/066—Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
- G11C7/1012—Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1039—Read-write modes for single port memories, i.e. having either a random port or a serial port using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/1066—Output synchronization
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/1087—Data input latches
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/1093—Input synchronization
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
- G11C2207/10—Aspects relating to interfaces of memory device to external buses
- G11C2207/107—Serial-parallel conversion of data or prefetch
Definitions
- This invention relates to a semiconductor storage device and, more particularly, to a semiconductor storage device that lends itself to a reduction in number of pins and an increase in speed.
- SRAM static random-access memory
- MSRAM Mobile Specified RAM Family
- An MSRAM is functionally compatible with a low-power-consumption SRAM and achieves a large increase in capacity (e.g., 16 to 128 M), which is not possible with an SRAM, by employing a DRAM (Dynamic Random-Access Memory) memory cell.
- DRAM Dynamic Random-Access Memory
- SDRAM synchronous DRAM, or “SDRAM”.
- the SDRAM is characterized by the following:
- the burst length (word length of successively output data) is 8 bits, 16 bits (one word) parallel;
- the CAS latency (number of clocks from input of a read command to output of the initial valid data) is 3;
- the time needed to transfer an 8-word burst is 120 ns.
- CLK represents a synchronizing clock signal
- CMD/Add denotes a command/address signal
- Dout/Din represents a data signal at a data input/output terminal.
- a bank active command (ACT) and a row address are input and the bank is activated.
- ACT bank active command
- RD read command
- a column address are input.
- PRE represents a precharge command.
- one clock cycle is equal to 7.5 ns, and the period of time from the ACT command to the next ACT command is 120 ns.
- the cycle that occupies the memory core is long owing to the continuation of row access. Further, one access cycle requires three commands, namely the active command (ACT), the read/write command (RD) and the precharge command (PRE). Furthermore, refresh control from an external SDRAM controller is required. The number of pins is reduced by address multiplexing of the row and column addresses (RAS, CAS).
- FIG. 9A illustrates an example of operation of an MSRAM of SRAM interface specifications in which the cell array is constituted by a DRAM.
- An SDRAM the timing operation of which is exemplified in FIG. 9A is characterized by the following:
- the burst length is 8 bits, 16 bits (one word) parallel;
- the rate latency (RL) is 7;
- the time needed to transfer an 8-word burst is 112.5 ns.
- a WAIT signal is output as the active state when conflict occurs with internal refresh at the instant a chip-select signal /CS (low active) undergoes a transition from the high to the low level. It should be noted that precharging is performed automatically in the MSRAM.
- the time required for transfer of an 8-word burst is 112.5 ns, which is one to two cycles faster in comparison with the SDRAM of FIG. 8 .
- a decline in performance ascribable to refresh basically is nil.
- FIG. 9B illustrates an example of operation in a case where addresses and data are multiplexed in an MSRAM.
- the clock signal CLK is the same as that used in FIG. 9A .
- ADV represents a signal indicating the validity of an address signal supplied from an address bus to a shared access/data terminal ADD/Data of the MSRAM.
- the MSRAM latches the address signal at the shared access/data terminal ADD/Data by a register.
- the shared access/data terminal ADD/Data functions as a data input/output terminal.
- the number of pins is reduced in comparison with an SDRAM when the number of data terminals is greater than 32.
- the shared access/data terminal ADD/Data acting as a data output terminal, outputs readout data QA 0 to QA 7 in the burst mode.
- FIG. 10 is a diagram illustrating the operation of an MSRAM having SRAM interface specifications and equipped with a pipeline burst function.
- CLK represents a synchronizing clock
- CMD/Add denotes a command/address signal
- Dout/Din represents a data signal at a data input/output terminal.
- read commands RDA, RDB, and RDC are input, 8-word successive data QA 0 to QA 7 corresponding to the read command RDA is output upon a delay equivalent to the CAS latency, 8-word successive data QB 0 to QB 7 corresponding to the read command RDB is output from the next clock cycle of the output of data QA 7 , and 8-word successive data QC 0 to QC 7 corresponding to the read command RDC is output from the next clock cycle of the output of data QB 7 .
- readout data (8 words ⁇ 3) of the read commands RDA, RDB and RDC are output successively upon elapse of prescribed clock cycles (e.g., 60 ns).
- burst data is output upon elapse of a fixed period of time.
- data corresponding to the previous read command is being output, the next command is received. Successive data output is made possible by a random-access address.
- Patent Document 1 discloses a semiconductor memory, which has at least one multiplexing signal input terminal serving as a terminal for inputting both a data signal and an address signal.
- a control signal (address-enable signal) for identifying whether a signal applied to the multiplexing signal input terminal is a data signal or an address signal.
- the arrangement is such that while data corresponding to a read command is being output, the next command is received. Read-out data in 8-word units can be output successively without interruption.
- a semiconductor storage device comprises: a shared address/data terminal that shares an address terminal to which an address signal is input and a data terminal for inputting and/or outputting a data signal; a cell array, which has a plurality of memory cells, in which a data signal from a memory cell selected by an address signal is read out, or in which a data signal is written to a memory cell selected and read out; and a circuit for receiving one command to the cell array as an input, accepting at least one other command to the cell array in a period of time from input of the one command to output or input of a data signal, which corresponds to the one command, from the shared address/data terminal, and subjecting the accepted plurality of commands to pipeline processing.
- access to the cell array corresponding to the one command and output of data, which has been read out of the cell array in response to the previous command, to the data terminal are performed in overlapped fashion in terms of time.
- a semiconductor storage device comprising: a shared address/data terminal that shares an address terminal and a data terminal for output and/or input; a cell array, which has a plurality of memory cells, in which a data signal from a memory cell that has been selected by an address signal from the address terminal is read out, or a data signal is written to a memory cell that has been selected for read-out; and a circuit for supplying write data from the shared address/data terminal to the cell array and supplying read-out data from the cell array to the shared address/data terminal; wherein in a period of time from receipt of an access command to access the cell array to input or output of data, which corresponds to this access command, from the shared address/data terminal, at least one other access command is received and data corresponding to this other access command is input or output from the shared address/data terminal following data corresponding to the initial access command.
- the semiconductor storage device is so adapted that a cell-array read or write access command is input, at least one further access command is accepted by the time data corresponding to the first-mentioned access command is output or input, and the plurality of access commands are subjected to pipeline processing.
- the foregoing object is attained by providing a semiconductor storage device having a circuit for exercising control in such a manner that in a cycle that follows a cycle in which a read request and a read address are accepted, read-out data corresponding to the read request is output from a data terminal.
- a semiconductor storage device having a circuit for exercising control in such a manner that in a cycle that follows a cycle in which a read request and a read address are accepted, read-out data corresponding to the read request is output from a data terminal.
- it may be so arranged that in a cycle that follows a cycle in which a write request and a write address are accepted, write data corresponding to the write request is accepted.
- a semiconductor storage device has a read/write-address pipeline function and includes a circuit for exercising control in such a manner that a write request and a write address are accepted so as to overlap a cycle in which a read-out data signal corresponding to an earlier accepted read request is output from a data terminal, and write data corresponding to the write request is accepted from the data terminal after the read-out data is output from the data terminal.
- a semiconductor storage device has a circuit for exercising control in such a manner that a write data signal corresponding to a write request is accepted in a cycle that follows a cycle in which the write request and a write address are accepted, a read request and a read address are accepted so as to overlap a cycle in which the write data signal is input from the data terminal, and read-out data corresponding to a read request is output from the data terminal after the write data is input from the data terminal.
- At least one access command is input in a latency period extending from input of an access command to input/output of data, which corresponds to this command, from a data terminal, a plurality of access commands that have been input are subjected to pipeline control and access is speeded up.
- access to a cell array corresponding to one command and output of data, which has been read out of the cell array in response to the previous command, to a data terminal are performed in overlapped fashion in terms of time and access at higher speed is achieved.
- a semiconductor storage device having an input/output terminal that shares input and output of data is such that it is possible to perform a read/write mutual pipeline operation and to support high-speed data transfer, etc.
- apparent latency is shortened greatly by adopting an arrangement in which read-out data is output in a cycle that follows a cycle in which a read request has been received.
- FIG. 1 is a diagram illustrating the structure of a semiconductor storage device according to an embodiment of the present invention
- FIG. 2 is a timing diagram for describing the operation of the present embodiment
- FIG. 3 is a timing diagram for describing the operation of the present embodiment
- FIG. 4 is a timing diagram for describing the operation of the present embodiment
- FIG. 5 is a diagram illustrating an example of the circuit structure of a DRAM adapted for address and data multiplexing according to this embodiment
- FIG. 6 is a diagram illustrating the circuit structure of another embodiment of the present invention.
- FIGS. 7A , 7 B and 7 C are timing diagrams for describing the operation of the present embodiment.
- FIG. 8 is a diagram for describing the data transfer operation of a semiconductor storage device (SDRAM) according to the prior art
- FIGS. 9A and 9B are diagrams for describing the data transfer operation of a semiconductor storage device (AD MUX MSRAM) according to the prior art;
- FIG. 10 is a diagram for describing the data transfer operation of a semiconductor storage device (pipeline-burst MSRAM) according to the prior art
- FIG. 11 is a diagram for describing an example for comparison purposes, and (B) and (C) of FIG. 11 are diagrams for describing read and write operations, respectively of an embodiment of the present invention
- FIG. 12 is a diagram illustrating the structure of another embodiment of the present invention.
- FIG. 13 is a timing diagram for describing the operation of yet another embodiment of the invention.
- FIG. 14 is a diagram illustrating the structure of a register according to yet another embodiment of the present invention.
- a semiconductor storage device includes a shared address/data ADD/Data that shares an address terminal and a data terminal, and a memory core ( 100 ), which has a plurality of memory cells, from which data of a memory cell that has been selected by an address signal from the address terminal is read out and to which data is written to a memory cell that has been selected.
- a latency period extending from input of one access command to input/output of data, which corresponds to this command, from the shared address/data terminal ADD/Data, at least one access command is input and a plurality of the input access commands undergo pipeline control successively.
- access to the cell array corresponding to the one command and output to a data terminal of data that has been read out of the cell array in response to the previous command are performed in overlapped fashion in terms of time.
- FIG. 1 is a diagram useful in describing the structure of a semiconductor storage device according to an embodiment of the present invention.
- the semiconductor storage device includes a memory core 100 ; a register (command register) 101 for receiving and holding a command; a read/write timing control circuit 102 ; a read/write timing control circuit 102 ; a multiplexer circuit 103 which switchingly connects a shared address/data terminal ADD/Data to an address line 113 or data line 114 based upon an A/D changeover signal 115 from the read/write timing control circuit 102 ; a register 104 for receiving an address signal from the multiplexer circuit 103 and outputting an internal address 117 ; a serial/parallel converting circuit 106 for serially receiving a plurality of items of write data from the multiplexer 103 and converting the data to parallel data; a register 107 for receiving the output of the serial/parallel converting circuit 106 ; a data register 110 connected via the register 107 and a data bus
- the memory core 100 has memory cells at the intersections of bit lines and word lines, although none of these are illustrated.
- Data that has been read out to a bit line from a memory cell selected by decoders for decoding respective ones of column and row addresses is amplified by an amplifier and the data is output to a local data bus 112 via a selected Y switch. Further, write data from the local data bus 112 is amplified by an amplifier and the data is written to the selected memory cell.
- the register 101 stores a command that is input thereto and outputs the command to the read/write timing control circuit 102 .
- the register 101 is constituted by a FIFO (first in, first out) register having a storage capacity for the maximum number of commands that can input successively.
- the register 101 samples, holds and outputs a command at an edge, such as a rising edge, of a clock signal CLK.
- the read/write timing control circuit 102 receives a command from the register 101 and generates and outputs a read timing signal Read-K and a write timing signal Write-K in dependence upon read/write access. Further, in accordance with a command ADV, the read/write timing control circuit 102 outputs the A/D changeover signal 115 to the multiplexer 103 .
- the A/D changeover signal 115 is for controlling changeover between an address and data with regard to the shared address/data terminal ADD/Data.
- the read/write timing control circuit 102 receives the command from the register 101 and outputs the R/W changeover signal 116 to the tri-state buffer 105 in accordance with read/write access.
- the tri-state buffer 105 is placed in an output-enable state when the R/W changeover signal 116 indicates read and in an output-disable state (a state in which the output is in a high impedance state) when the R/W changeover signal 116 indicates write. Furthermore, a core control signal 118 (e.g., a strobe signal that controls row drive such as the driving of word lines, or a signal that controls the activation of columns in a sense amplifier and Y switch) from the read/write timing control circuit 102 is output to the memory core 100 .
- a core control signal 118 e.g., a strobe signal that controls row drive such as the driving of word lines, or a signal that controls the activation of columns in a sense amplifier and Y switch
- the semiconductor storage device shown in FIG. 1 is not limited to a dynamic-type semiconductor storage device (it may just as well be an SRAM). In the case of a dynamic semiconductor storage device, the read/write timing control circuit 102 may be adapted so as to
- the register 104 which receives the address signal, receives the read timing signal Read-K and the write timing signal Write-K and supplies an internal address to the memory core 100 .
- the memory core 100 receives the core control signal 118 from the read/write timing control circuit 102 and decodes an internal address signal 117 by a decoder (not shown). A selected word line is activated and a memory access operation is performed via the selected Y switch.
- the register 104 outputs the internal address signal 117 upon receiving the write timing signal Write-K, which is activated after a delay of prescribed cycles following input of an address signal to the shared address/data terminal ADD/Data. For this reason the register 104 is also referred to as a “late-write register”.
- a write address is supplied from the shared address/data terminal ADD/Data and a Write command is sampled by the register 101 .
- the multiplexer 103 connects the shared address/data terminal ADD/Data to the address line 113 so that the address signal that has entered from the shared address/data terminal ADD/Data is supplied to the input terminal of register 104 .
- the latter samples the address signal in response to the write timing signal Write-K and supplies it to the memory core 100 as the internal address signal 117 .
- the multiplexer 103 connects the shared address/data terminal ADD/Data to the data line 114 so that a data signal is input from the shared address/data terminal ADD/Data to the data line 114 serially sequentially in a number of words of the burst length.
- the serial data is input to the serial/parallel converting circuit 106 .
- the latter converts the serial data to parallel data and supplies the parallel data to the data register 110 via the register 107 .
- the data register 110 accepts the parallel data from the data bus 111 and supplies it to the memory core 100 so that a plurality of items of data are written to selected memory cells.
- the next command may be input before data corresponding to the Write command enters. In this case, the next command is held in the register 101 .
- a Read command is sampled by the register 101 , and a read address is supplied from the shared address/data terminal ADD/Data.
- the multiplexer 103 connects the shared address/data terminal ADD/Data to the address line 113 so that the address signal is sampled by register 104 based upon the read timing signal Read-K and supplied to the memory core 100 .
- the command and the address signal are held in the registers 101 and 104 , respectively.
- the multiplexer 103 connects the shared address/data terminal ADD/Data to the data line 114 .
- a plurality of items of data are read out of the memory core 100 and transferred to the data register 110 .
- the read-out data which is transferred from the data register 110 in parallel via the data bus 111 , is supplied to the register 109 .
- the parallel/serial converting circuit 108 which receives a parallel output from the register 109 , converts the parallel data to serial data and outputs the serial data.
- the tri-state buffer 105 which is in the output-enable state, outputs the read-out data signal sequentially in a number of words of the burst length. The signal is output from the shared address/data terminal ADD/Data via the multiplexer 103 .
- This embodiment is such that in a case where a succeeding Read command has been input in a latency period that extends from input of the previous Read command to output of initial read-out data corresponding to this Read command, the succeeding command is stored in the register 101 in FIFO (first in, first out) fashion.
- FIFO first in, first out
- FIG. 2 is a timing diagram for describing the operation of the present embodiment.
- an address-valid signal ADV which is activated when an address signal supplied from the CPU side to a memory is valid, is used as the address-data changeover signal.
- one address signal (A) is input to the shared address/data terminal ADD/Data and the address-valid signal ADV is activated.
- an address signal (C) is input from the shared address/data terminal ADD/Data, the address-valid signal ADV is activated, and address signal (C) is latched in the register.
- FIG. 3 is a timing diagram for describing the operation of the present embodiment.
- FIG. 3 illustrates a read operation of a double-data rate (DDR) semiconductor storage device in which operation at both rising and falling edges of a clock is specified in a clock-synchronized DRAM adapted for address/data multiplexing that makes shared use of an address terminal and data terminal. It should be noted that the period between times t 4 and t 4 has been deleted.
- DDR double-data rate
- CLK and /CLK are complementary clock signals; /ADV is an address-valid signal that is in the activated state at the low level and in this state indicates that an address signal is valid; L, UDQS is a control signal indicating that input/output data is data of a lower order byte and higher order byte; ADD/DQ is an address/data signal at the shared address/data terminal ADD/Data that shares and uses an address and data in multiplexing; /CE 1 is a chip-enable signal that is in the activated state at the low level; and /OE is an output-enable signal that is in the activated state at the low level, thereby turning on a buffer circuit so that read-out data is output from the shared address/data terminal ADD/Data.
- /WE is a write-enable signal that is in the activated state at the low level. When this signal is at the low level and chip enable is in the activated state, a write operation is performed. When this signal is at the high level, a read operation is performed.
- the address-valid signal ADV is a signal which, when at the low level, indicates that the address signal on the address bus is valid. An address signal that is valid is sampled in the register 104 . Owing to latency, read-out data from the shared address/data terminal ADD/Data is output in a burst in accordance with a data strobe signal (LDQS, UDQS) of lower and higher order bits.
- LQS data strobe signal
- the address-valid signal /ADV is activated (assumes the low level) at time t 3 , and read-out data Q 0 , Q 1 is output at time t 7 , which is at the falling edge of the clock /CLK, and at time t 8 , which is at the rising edge of the clock /CLK, respectively.
- the address-valid signal /ADV may be activated and another read access inserted in the interval of t 4 to t 7 of the latency period.
- FIG. 4 is a timing diagram for describing the operation of the present embodiment.
- FIG. 4 illustrates an example of a write operation in a clock-synchronizing semiconductor storage device the read operation of which is illustrated in FIG. 3 .
- the address signal is sampled in the register 104 at the low level of the address-valid signal ADV.
- Write data is input from the shared address/data terminal ADD/Data with latency.
- the address-valid signal /ADV may be activated and another write access inserted in the interval of t4 to t7 of the latency period.
- tCMS and tCMH are command setup time and hold time, respectively;
- tAS and tAH are address setup time and hold time, respectively; and
- tAC represents access time.
- these signals and other timing information do not have a direct bearing upon the present invention, they are not described here.
- FIG. 5 is a diagram illustrating an example of structure in a case where the semiconductor storage device adapted for address and data multiplexing shown in FIG. 1 is applied to a DRAM that requires a refresh operation for data retention.
- this semiconductor storage device includes a first register 202 for sampling an address, which has been generated by a refresh-address generating circuit 201 , and outputting the address as a refresh address; a second register 203 for sampling the address signal from the shared address/data terminal ADD/Data; a third register 204 for sampling read-out data from the memory core; and a fourth register 205 for sampling write data from the shared address/data terminal ADD/Data.
- FIG. 6 is a diagram illustrating the structure of another embodiment of the present invention.
- the number of circuit elements is reduced by unifying the first register 202 , second register 203 and fourth register 205 of FIG. 5 .
- the semiconductor storage device includes a first switch 301 having one end connected to the shared address/data terminal ADD/Data and comprising a path transistor turned on and off by a control signal KME connected to the gate of the transistor, and a second switch 302 having one end connected to the output of the refresh-address generating circuit 201 (see FIG. 5 ) and comprising a path transistor turned on and off by a control signal KMR connected to the gate of the transistor.
- the other ends of the first and second switches 301 and 302 are tied together and connected to a first flip-flop (which comprises inverters 303 and 304 , the input and output whereof are mutually connected).
- the device further includes third and fourth switches 305 and 306 , respectively, having one end tied together and connected to the output of the first flip-flop.
- the third switch 305 which comprises a path transistor turned on and off by a control signal KSA connected to the gate of the transistor, has its other end connected to a second flip-flop (which comprises inverters 307 and 308 , the input and output whereof are mutually connected) for outputting an internally activated address (the internal address of FIG. 1 ) that is supplied to a row decoder.
- the fourth switch 306 which comprises a path transistor turned on and off by a control signal KSW connected to the gate of the transistor, has its other end connected to a third flip-flop (which comprises inverters 309 and 310 the input and output whereof are mutually connected) for outputting Write Data.
- a third flip-flop which comprises inverters 309 and 310 the input and output whereof are mutually connected
- FIG. 7A is a diagram for describing the sampling of an external address signal in the implementation shown in FIG. 6 .
- the first switch 301 With KME at the high level, the first switch 301 turns on and an address signal enters from the shared address/data terminal ADD/Data.
- the control signal KSA is in the high level, the third switch 305 is turned on and the address signal is output as an internal address signal.
- FIG. 7B is a diagram for describing the sampling of a refresh address in the implementation shown in FIG. 6 .
- the second switch 302 With KMR at the high level, the second switch 302 turns on and a refresh address signal enters from the refresh-address generating circuit.
- the control signal KSA attains the high level, the third switch 305 is turned on and the refresh address is output as an internal address signal.
- FIG. 7C is a diagram for describing the sampling of write data in the implementation shown in FIG. 6 .
- the first switch 301 With KME at the high level, the first switch 301 turns on and a data signal enters from the shared address/data terminal ADD/Data.
- the control signal KSA attains the high level, the fourth switch 306 is turned on and the signal is output as Write Data.
- registers are shared and changed over by switches so that various registers are used, thereby reducing the scale of the circuitry further besides providing an address/data multiplexing function (A/D MUX).
- A/D MUX address/data multiplexing function
- RL latency period
- a semiconductor storage device having a data input/output terminal, in which an address signal and a data signal are separated.
- Another embodiment of a semiconductor storage device according to the present invention is a semiconductor storage device having a read/write-access pipeline function. In this semiconductor storage device, a write request and a write address are input in the same cycle as that in which a read-out data signal from a cell array corresponding to a read request accepted previously is output from the data input/output terminal.
- a write data signal corresponding to the write request is input from the data input/output terminal after read-out data corresponding to the read request is output from the data input/output terminal.
- read/write pipeline processing is implemented. Even if a read request is issued following a write request, pipeline processing is implemented in similar fashion. That is, in a cycle that follows a cycle in which a write request and a write address have been accepted, a write data signal corresponding to the write request is accepted, a read request and a read address are input in the same cycle as that in which the write data signal will be input from the data input/output terminal, and read-out data corresponding to this read request is output from the data terminal after the write signal has been input from the data input/output terminal.
- a two-state late-write scheme in which the write data signal is written to the cell array upon receiving the write request twice, is adopted. Another embodiment of the present invention will be described with reference to the drawings.
- FIG. 11 is a diagram for describing an overview of the operating principle of another embodiment of the present invention.
- (A) is a diagram for comparison purposes illustrating the operation timing of a semiconductor storage device according to the invention in which pipeline processing is not executed. This corresponds to the timing diagrams of FIGS. 9A and 9B .
- (B) is a diagram useful in describing an example of a read operation in a semiconductor storage device according to this embodiment of the present invention
- (C) is a diagram useful in describing an example of a write operation in a semiconductor storage device according to this embodiment of the present invention.
- read-out data A 0 to A 7 corresponding to address A is output from the data input/output terminal in a cycle the same as that in which the address was input.
- burst length is assumed to be eight in the example shown in FIG. 11 .
- read-out data B 0 to B 7 , C 0 to C 7 corresponding to addresses B, C, respectively is output from the data input/output terminal following elapse of the latency period regarding addresses B, C, respectively.
- a read address (addA) is sampled in a cycle (Cycle 1 ) one earlier than that in which data is output from the data input/output terminal, read-out of data from the cell array is performed in this cycle (Cycle 1 ), and this data is sampled in a data register of a peripheral circuit (not shown) (e.g., in an output latch circuit 134 in FIG. 12 , described later).
- latency becomes two or three in a case where the address input (input of addB) in the next cycle (Cycle 2 ) is adopted as the timing reference.
- write data should happen to be supplied to the data input/output terminal in Cycle 2 , this data will collide with the read-out data. As a consequence, write data corresponding to write address B cannot be input from the data input/output terminal in Cycle 2 .
- the read-out data signal corresponding to the read address applied in Cycle 1 is output from the data input/output terminal in Cycle 2
- the write data signal corresponding to write address B (addB) is input from the data input/output terminal in the next cycle (Cycle 3 ) and this signal is latched in a data register circuit (not shown) (an input latch circuit 131 in FIG. 12 , described later).
- write data cannot be input in a cycle that follows a cycle in which a read address is input.
- Write access takes place after read address ends (i.e., after read-out data has been output from the data input/output terminal). Access performance declines, the data bus, etc., cannot be utilized effectively and high-speed data transfer cannot be supported.
- FIG. 12 is a diagram schematically illustrating an example of the overall structure of a semiconductor storage device according to the other embodiment of the present invention described with reference to (B) and (C) of FIG. 11 .
- the semiconductor storage device includes an address latch circuit 120 ; changeover switches 126 , 127 ; an address buffer 128 ; an R/W control-timing control circuit 129 ; a data latch circuit 130 ; switches 135 , 136 ; a changeover switch 137 ; a data input buffer 139 ; a data output buffer 140 ; and a control signal generating circuit 141 for generating a control signal CWCNT.
- a chip-select signal /CS, address-valid signal /ADV, write-enable signal /WE and output-enable signal /OE, etc. are input as control signals supplied from the outside.
- the address latch circuit 120 has first and second write latch circuits 121 and 122 of two-stage construction for latching a write address, and a read latch circuit 124 for latching a read address.
- a switch 123 is provided between the output of the first write latch circuit 121 and the input of the second write latch circuit 122 .
- the R/W control-timing control circuit 129 generates a latch timing signal of the address latch circuit 120 (the write latch circuits 121 , 122 and read latch circuit 124 ). It is of course permissible to use a signal synchronized to an internal clock signal (a clock signal generated internally of the semiconductor storage device and synchronized to an external clock signal) as the latch timing signal.
- the control signal CWCNT is input to the changeover switches 126 and 127 as a changeover control signal.
- terminals a and b of the changeover switches 126 and 127 conduct so that the output of the address buffer 128 is supplied to the input of the first write latch circuit 121 .
- terminals b and c of the changeover switches 126 and 127 conduct so that the output of the address buffer 128 is supplied to the input of the read latch circuit 124 .
- the switch 123 is turned on and off by the control signal CWCNT. This switch is turned on when the control signal CWCNT is activated and is turned off when the control signal CWCNT is deactivated.
- the chip-select signal /CS and write-enable signal /WE are input to the control signal generating circuit 141 .
- the control signal CWCNT is activated (high level).
- the control signal CWCNT is reset to the deactivated state (low level).
- control signal generating circuit 141 may comprise an SR latch having a set terminal the input to which is the output of a NAND gate whose inputs are the chip-select signal /CS and write-enable signal /WE, and a reset terminal the input to which is the write-enable signal /WE.
- the control signal CWCNT rises to the high level and the circuitry comprising the changeover switch 126 , address latch circuit 120 and changeover switch 127 operate in such a manner that the output of the address buffer 128 is latched by the first write latch circuit 121 .
- switch 123 is turned on.
- the second write latch circuit 122 latches and outputs the output of the first write latch circuit 121 , and the output of the second write latch circuit 122 is supplied from the changeover switch 127 to the address decoder (not shown) of the memory core 100 .
- the control signal CWCNT is activated and the switch 135 is turned off.
- the switch 136 which is turned on and off by a signal that is the inverse of the control signal CWCNT (namely by the output of the inverter 138 ), is turned on.
- the switch 133 is turned off, the terminals a and b are rendered conductive by the changeover switch 137 and the output of an input latch circuit 132 is connected to an input/output bus. At this time an address signal that is output from the address latch circuit 120 by two write-enable signals /WE is supplied from the changeover switch 127 to the memory core.
- read-out data that has been latched in the output latch circuit 134 is output from the data input/output terminal Data via the switch 136 and the output-enabled data output buffer 140 (output-enable signal /OE is at the low level) if a read-access request was input in the previous cycle.
- the input latch circuit 132 latches and outputs the output of the input latch circuit 131 , and this output (write data) is supplied to the input/output bus line via the changeover switch 137 .
- the write data is applied to the memory core 100 .
- the read-out data that has been latched in the output latch circuit 134 is output from the data input/output terminal via the output buffer 140 .
- the control signal CWCNT is set to the deactivated state (the low level) and the circuitry comprising the changeover switch 126 , address latch circuit 120 and changeover switch 127 operate in such a manner that the output of the address buffer 128 is latched by the read latch circuit 124 .
- This latched output is supplied to the address decoder (not shown) of the memory core 100 as an internal address.
- the switch 135 When the control signal CWCNT is in the deactivated state (at the low level), the switch 135 is turned on, the switch 136 is turned off, the switch 133 is turned off, terminals a and c are connected by the changeover switch 137 and the output from the input/output bus is supplied to the input of the output latch circuit 134 . That is, write data from the data input/output terminal is latched in the input latch circuit 131 via the data input buffer 139 and the switch 135 , which is in the ON state. Since the switch 133 is in the OFF state, the output of the input latch circuit 131 is not transmitted to the input latch circuit 132 .
- Read-out data from the cell array is supplied to an latched in the output latch circuit 134 via the changeover switch 137 .
- the latch circuits may be constituted by edge-trigger-type registers as a matter of course.
- the switches 123 , 133 , 135 and 136 may be constituted by path transistors or CMOS-type transfer gates.
- FIG. 13 is a timing diagram for describing the operation of the semiconductor storage device of the embodiment illustrated in FIG. 12 .
- the timing waveform of the control signal CWCNT is shown in FIG. 13 .
- the control signal CWCNT rises to the high level (for the duration of the write-address input interval) at the falling edges of the chip-select signal /CS and write-enable signal /WE and is reset to the low level at the rising edge of the chip-select signal /CS.
- Cycle 2 the control signal CWCNT is set to the low level (for the duration of the read-address input interval).
- the read address is input to the address terminal and write data corresponding to the address of Cycle 2 is input to the data terminal.
- control signal CWCNT rises to the high level at the falling edges of the chip-select signal /CS and write-enable signal /WE and read-out data corresponding to the read address that was input in Cycle 2 is output from the data terminal.
- the control signal CWCNT is reset to the low level at the rising edge of the chip-select signal /CS.
- FIG. 14 is a diagram illustrating the structure of a register in a case where the cells of the cell array in the memory core 100 are constituted by DRAM cells that require refresh for data retention.
- this embodiment differs from FIG. 5 in that the DRAM-cell refresh instruction enters from an external terminal (pin).
- a counter constituting the refresh-address generating circuit 201 outputs a refresh address.
- the refresh address is held by the register 202 and then supplied from the multiplexer 206 to the memory core 100 ( FIG. 12 ) as an internal row address.
- the address signal and data signal are not multiplexed, unlike the arrangement of FIG. 5 .
- this embodiment may be applied to a pseudo-SRAM such as the above-mentioned MSRAM as a matter of course.
- a pin for performing reset (flush) of a pipeline processing register may be made to serve also as the refresh instruction input pin.
- pipeline control is carried out in this embodiment can be set from an external terminal.
- the device may be so arranged that by activating the address-valid signal /ADV, which indicates that the address signal on the address bus is valid, two times in succession, the device enters the pipeline control mode, and by activating the address-valid signal ADV two times in succession in the pipeline control mode, the pipeline control mode is exited.
- the external pin (Flush) in FIG. 14 is used in order to reset the pipeline registers, etc., when the pipeline control mode is exited.
Abstract
Description
Claims (17)
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004-156470 | 2004-05-26 | ||
JP2004156470 | 2004-05-26 | ||
JP2004312281A JP4827399B2 (en) | 2004-05-26 | 2004-10-27 | Semiconductor memory device |
JP2004-312281 | 2004-10-27 |
Publications (2)
Publication Number | Publication Date |
---|---|
US20050265086A1 US20050265086A1 (en) | 2005-12-01 |
US7447109B2 true US7447109B2 (en) | 2008-11-04 |
Family
ID=35425015
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US11/136,484 Expired - Fee Related US7447109B2 (en) | 2004-05-26 | 2005-05-25 | Semiconductor storage device |
Country Status (2)
Country | Link |
---|---|
US (1) | US7447109B2 (en) |
JP (1) | JP4827399B2 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060129701A1 (en) * | 2004-12-15 | 2006-06-15 | Shekoufeh Qawami | Communicating an address to a memory device |
US20090238014A1 (en) * | 2008-03-19 | 2009-09-24 | Chia-Jen Chang | Low power synchronous memory command address scheme |
US20230105305A1 (en) * | 2021-07-27 | 2023-04-06 | Stmicroelectronics International N.V. | Atpg testing method for latch based memories, for area reduction |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4234126B2 (en) | 2005-09-28 | 2009-03-04 | インターナショナル・ビジネス・マシーンズ・コーポレーション | Memory, memory access control method |
US7652922B2 (en) * | 2005-09-30 | 2010-01-26 | Mosaid Technologies Incorporated | Multiple independent serial link memory |
JP2007200504A (en) * | 2006-01-30 | 2007-08-09 | Fujitsu Ltd | Semiconductor memory, memory controller, and control method of semiconductor memory |
JP4813937B2 (en) * | 2006-03-20 | 2011-11-09 | ルネサスエレクトロニクス株式会社 | Semiconductor device |
JP5087870B2 (en) * | 2006-07-12 | 2012-12-05 | 富士通セミコンダクター株式会社 | Semiconductor memory, controller and method of operating semiconductor memory |
JP4984872B2 (en) * | 2006-12-15 | 2012-07-25 | 富士通セミコンダクター株式会社 | Semiconductor memory, semiconductor memory operating method, memory controller and system |
JP2011048876A (en) * | 2009-08-27 | 2011-03-10 | Renesas Electronics Corp | Semiconductor memory device and method for controlling the same |
JP5439567B1 (en) * | 2012-10-11 | 2014-03-12 | 株式会社東芝 | Semiconductor device |
Citations (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2232797A (en) * | 1989-06-16 | 1990-12-19 | Samsung Semiconductor Inc | Ram based serial memory with pipelined look-ahead reading |
US5280597A (en) * | 1990-03-30 | 1994-01-18 | Mitsubishi Denki Kabushiki Kaisha | Pipeline processor with self timed data transfer |
US5394529A (en) * | 1990-06-29 | 1995-02-28 | Digital Equipment Corporation | Branch prediction unit for high-performance processor |
JPH07296593A (en) * | 1994-04-28 | 1995-11-10 | Mega Chips:Kk | Semiconductor storage device |
US5584044A (en) * | 1990-09-28 | 1996-12-10 | Fuji Photo Film Co., Ltd. | Integrated circuit memory card for write in/read out capability having plurality of latching means for expandable addressing using counting means for enabling latches thereof |
US5960458A (en) * | 1995-08-28 | 1999-09-28 | Hitachi, Ltd. | Shared memory system |
JPH11328971A (en) | 1998-04-03 | 1999-11-30 | Hyundai Electronics Ind Co Ltd | Semiconductor memory device |
US20010000819A1 (en) * | 1998-07-30 | 2001-05-03 | Manning Troy A. | Method and system for bypassing pipelines in a pipelined memory command generator |
US6285611B1 (en) * | 1999-07-14 | 2001-09-04 | Samsung Electronics Co., Ltd. | Memory device having input and output sense amplifiers that occupy less circuit area |
US20010053106A1 (en) * | 2000-06-16 | 2001-12-20 | Matsushita Electric Industrial Co., Ltd. | Semiconductor memory device |
US20020018395A1 (en) * | 1995-06-30 | 2002-02-14 | Mclaury Loren L. | Method and apparatus for multiple latency synchronous dynamic random access memory |
US6427197B1 (en) * | 1998-09-16 | 2002-07-30 | Fujitsu Limited | Semiconductor memory device operating in synchronization with a clock signal for high-speed data write and data read operations |
US20030151966A1 (en) * | 2000-07-07 | 2003-08-14 | Paul Demone | High speed DRAM architecture with uniform access latency |
US6691204B1 (en) * | 2000-08-25 | 2004-02-10 | Micron Technology, Inc. | Burst write in a non-volatile memory device |
US6751717B2 (en) * | 2001-01-23 | 2004-06-15 | Micron Technology, Inc. | Method and apparatus for clock synchronization between a system clock and a burst data clock |
US20040246783A1 (en) * | 2003-06-03 | 2004-12-09 | Yun-Sang Lee | High burst rate write data paths for integrated circuit memory devices and methods of operating same |
US6839821B2 (en) * | 1999-11-16 | 2005-01-04 | Lexar Media, Inc. | Method and apparatus for memory control circuit |
US6871254B2 (en) * | 2001-12-12 | 2005-03-22 | Matsushita Electric Industrial Co., Ltd. | Processor and storage apparatus |
US20050127945A1 (en) * | 2003-12-13 | 2005-06-16 | Min-Sang Park | Data inversion circuits having a bypass mode of operation and methods of operating the same |
US20060041713A1 (en) * | 2004-08-18 | 2006-02-23 | Gordon Charles | Method and system for reducing pin count in an integrated circuit when interfacing to a memory |
US7047375B2 (en) * | 1997-10-10 | 2006-05-16 | Rambus Inc. | Memory system and method for two step memory write operations |
US7225312B2 (en) * | 2002-08-28 | 2007-05-29 | Micron Technology, Inc. | Multi-bank memory accesses using posted writes |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3304577B2 (en) * | 1993-12-24 | 2002-07-22 | 三菱電機株式会社 | Semiconductor memory device and operation method thereof |
JP3170146B2 (en) * | 1994-07-29 | 2001-05-28 | 株式会社東芝 | Semiconductor storage device |
JPH10233091A (en) * | 1997-02-21 | 1998-09-02 | Hitachi Ltd | Semiconductor storage device and data processor |
JP3604861B2 (en) * | 1997-03-11 | 2004-12-22 | 株式会社ルネサステクノロジ | Semiconductor storage device |
JP3567318B2 (en) * | 1997-08-21 | 2004-09-22 | 株式会社ルネサステクノロジ | Semiconductor memory device and design method thereof |
JP2000137983A (en) * | 1998-08-26 | 2000-05-16 | Toshiba Corp | Semiconductor storage |
JP2001135084A (en) * | 1999-11-08 | 2001-05-18 | Mitsubishi Electric Corp | Semiconductor memory |
JP4588158B2 (en) * | 2000-03-28 | 2010-11-24 | 富士通セミコンダクター株式会社 | Semiconductor integrated circuit |
JP2002175692A (en) * | 2000-12-07 | 2002-06-21 | Hitachi Ltd | Semiconductor memory and data processing system |
JP2002358783A (en) * | 2001-03-29 | 2002-12-13 | Internatl Business Mach Corp <Ibm> | Data input/output method, and dram |
JP2003157676A (en) * | 2001-11-22 | 2003-05-30 | Hitachi Ltd | Semiconductor memory |
-
2004
- 2004-10-27 JP JP2004312281A patent/JP4827399B2/en not_active Expired - Fee Related
-
2005
- 2005-05-25 US US11/136,484 patent/US7447109B2/en not_active Expired - Fee Related
Patent Citations (25)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2232797A (en) * | 1989-06-16 | 1990-12-19 | Samsung Semiconductor Inc | Ram based serial memory with pipelined look-ahead reading |
US5280597A (en) * | 1990-03-30 | 1994-01-18 | Mitsubishi Denki Kabushiki Kaisha | Pipeline processor with self timed data transfer |
US5394529A (en) * | 1990-06-29 | 1995-02-28 | Digital Equipment Corporation | Branch prediction unit for high-performance processor |
US5584044A (en) * | 1990-09-28 | 1996-12-10 | Fuji Photo Film Co., Ltd. | Integrated circuit memory card for write in/read out capability having plurality of latching means for expandable addressing using counting means for enabling latches thereof |
JPH07296593A (en) * | 1994-04-28 | 1995-11-10 | Mega Chips:Kk | Semiconductor storage device |
US20020018395A1 (en) * | 1995-06-30 | 2002-02-14 | Mclaury Loren L. | Method and apparatus for multiple latency synchronous dynamic random access memory |
US5960458A (en) * | 1995-08-28 | 1999-09-28 | Hitachi, Ltd. | Shared memory system |
US7047375B2 (en) * | 1997-10-10 | 2006-05-16 | Rambus Inc. | Memory system and method for two step memory write operations |
JPH11328971A (en) | 1998-04-03 | 1999-11-30 | Hyundai Electronics Ind Co Ltd | Semiconductor memory device |
US6272053B1 (en) * | 1998-04-03 | 2001-08-07 | Hyundai Electronics Industries Co., Ltd. | Semiconductor device with common pin for address and data |
US20010000819A1 (en) * | 1998-07-30 | 2001-05-03 | Manning Troy A. | Method and system for bypassing pipelines in a pipelined memory command generator |
US6427197B1 (en) * | 1998-09-16 | 2002-07-30 | Fujitsu Limited | Semiconductor memory device operating in synchronization with a clock signal for high-speed data write and data read operations |
US6285611B1 (en) * | 1999-07-14 | 2001-09-04 | Samsung Electronics Co., Ltd. | Memory device having input and output sense amplifiers that occupy less circuit area |
US6839821B2 (en) * | 1999-11-16 | 2005-01-04 | Lexar Media, Inc. | Method and apparatus for memory control circuit |
US20010053106A1 (en) * | 2000-06-16 | 2001-12-20 | Matsushita Electric Industrial Co., Ltd. | Semiconductor memory device |
US20030151966A1 (en) * | 2000-07-07 | 2003-08-14 | Paul Demone | High speed DRAM architecture with uniform access latency |
US6691204B1 (en) * | 2000-08-25 | 2004-02-10 | Micron Technology, Inc. | Burst write in a non-volatile memory device |
US7051178B2 (en) * | 2000-08-25 | 2006-05-23 | Micron Technology, Inc. | Burst write in a non-volatile memory device |
US6751717B2 (en) * | 2001-01-23 | 2004-06-15 | Micron Technology, Inc. | Method and apparatus for clock synchronization between a system clock and a burst data clock |
US6871254B2 (en) * | 2001-12-12 | 2005-03-22 | Matsushita Electric Industrial Co., Ltd. | Processor and storage apparatus |
US7225312B2 (en) * | 2002-08-28 | 2007-05-29 | Micron Technology, Inc. | Multi-bank memory accesses using posted writes |
US20040246783A1 (en) * | 2003-06-03 | 2004-12-09 | Yun-Sang Lee | High burst rate write data paths for integrated circuit memory devices and methods of operating same |
US20050127945A1 (en) * | 2003-12-13 | 2005-06-16 | Min-Sang Park | Data inversion circuits having a bypass mode of operation and methods of operating the same |
US7142021B2 (en) * | 2003-12-13 | 2006-11-28 | Samsung Electronics Co., Ltd. | Data inversion circuits having a bypass mode of operation and methods of operating the same |
US20060041713A1 (en) * | 2004-08-18 | 2006-02-23 | Gordon Charles | Method and system for reducing pin count in an integrated circuit when interfacing to a memory |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060129701A1 (en) * | 2004-12-15 | 2006-06-15 | Shekoufeh Qawami | Communicating an address to a memory device |
US20090238014A1 (en) * | 2008-03-19 | 2009-09-24 | Chia-Jen Chang | Low power synchronous memory command address scheme |
US7940543B2 (en) * | 2008-03-19 | 2011-05-10 | Nanya Technology Corp. | Low power synchronous memory command address scheme |
US20110176376A1 (en) * | 2008-03-19 | 2011-07-21 | Chia-Jen Chang | Low power synchronous memory command address scheme |
US20230105305A1 (en) * | 2021-07-27 | 2023-04-06 | Stmicroelectronics International N.V. | Atpg testing method for latch based memories, for area reduction |
Also Published As
Publication number | Publication date |
---|---|
JP2006012374A (en) | 2006-01-12 |
JP4827399B2 (en) | 2011-11-30 |
US20050265086A1 (en) | 2005-12-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7447109B2 (en) | Semiconductor storage device | |
KR100306966B1 (en) | Synchronous Burst Semiconductor Memory Device | |
US5835443A (en) | High speed semiconductor memory with burst mode | |
JP5160770B2 (en) | Latency control circuit and method thereof, and automatic precharge control circuit and method thereof | |
US5926434A (en) | Synchronous semiconductor memory device capable of reducing electricity consumption on standby | |
US20160189763A1 (en) | Memory device command decoding system and memory device and processor-based system using same | |
US6359813B1 (en) | Semiconductor memory device having improved data transfer rate without providing a register for holding write data | |
US20120144131A1 (en) | Semiconductor memory asynchronous pipeline | |
US20030026138A1 (en) | Semiconductor memory device having write latency operation and method thereof | |
JP2000163969A (en) | Semiconductor storage | |
US20090244986A1 (en) | Semiconductor memory device and methods thereof | |
EP0936619B1 (en) | Signal delay device for use in semiconductor storage device for improved burst mode operation | |
US6708255B2 (en) | Variable input/output control device in synchronous semiconductor device | |
KR20040022378A (en) | Semiconductor memory device requiring refresh operation | |
KR20020014563A (en) | Semiconductor memory device | |
US7136312B2 (en) | Semiconductor device having read and write operations corresponding to read and write row control signals | |
US5341488A (en) | N-word read/write access achieving double bandwidth without increasing the width of external data I/O bus | |
US6229758B1 (en) | Semiconductor memory device that can read out data faster than writing it | |
EP1248267A2 (en) | Semiconductor memory device and information processing system | |
JP3123473B2 (en) | Semiconductor storage device | |
US20220284943A1 (en) | Semiconductor memory device capable of operating at high speed, low power environment by optimizing latency of read command and write command depending on various operation modes | |
US10535395B2 (en) | Memory device with improved latency and operating method thereof | |
US6909665B2 (en) | Semiconductor memory device having high-speed input/output architecture | |
JP2012113819A (en) | Automatic precharge control circuit, semiconductor memory device and precharging operation control method | |
US6917563B2 (en) | Integrated memory |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
AS | Assignment |
Owner name: RENESAS ELECTRONICS CORPORATION, JAPAN Free format text: CHANGE OF NAME;ASSIGNOR:NEC ELECTRONICS CORPORATION;REEL/FRAME:025346/0868 Effective date: 20100401 |
|
FPAY | Fee payment |
Year of fee payment: 4 |
|
FPAY | Fee payment |
Year of fee payment: 8 |
|
AS | Assignment |
Owner name: RENESAS ELECTRONICS CORPORATION, JAPAN Free format text: CHANGE OF ADDRESS;ASSIGNOR:RENESAS ELECTRONICS CORPORATION;REEL/FRAME:044928/0001 Effective date: 20150806 |
|
FEPP | Fee payment procedure |
Free format text: MAINTENANCE FEE REMINDER MAILED (ORIGINAL EVENT CODE: REM.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
LAPS | Lapse for failure to pay maintenance fees |
Free format text: PATENT EXPIRED FOR FAILURE TO PAY MAINTENANCE FEES (ORIGINAL EVENT CODE: EXP.); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
STCH | Information on status: patent discontinuation |
Free format text: PATENT EXPIRED DUE TO NONPAYMENT OF MAINTENANCE FEES UNDER 37 CFR 1.362 |
|
FP | Lapsed due to failure to pay maintenance fee |
Effective date: 20201104 |